Fix duplicate package declaration

[luizademelo]

Currently, ChiGen can sometimes generate SystemVerilog code where the same package name is declared multiple times. While Chimera.cpp is designed to update package names, this issue indicates there's still a bug elsewhere preventing unique package names from being consistently generated.

// Seed: 4085962677
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
package package_0;
endpackage
module module_24 (
    output supply0 id_0,
    output tri id_1,
    input wand id_2
);
  wire id_4;
  assign module_25.id_2 = 0;
endmodule
module module_25 (
    input wand id_0,
    output supply0 id_1,
    output supply0 id_2,
    output tri0 id_3
);
  wire id_5;
  module_24 modCall_1 (
      id_3,
      id_3,
      id_0
  );
  assign id_3 = id_0;
  integer id_6;
endmodule