Fix "all identifiers need to have initial value"

[luizademelo]

Today, when there are multiple variables being declared, all of them need to have values, not just only one of them. For example:

supply1 id_17, id_18 = -1;

[markram1729]

Hey can I try this issue!

Here identifier needs to be initialised as in , can it be random or strictly with 0

[joaovam]

Hi @markram1729,

Sure you can!

Identifiers can be initialized with random values within a range, for example [-100, 100]. If you have any doubts please, let us know.

[markram1729]

I have generated a file which has

module module_0 (
    input  wire id_0,
    output wire id_1,
    output tri0 id_2,
    output wire id_3
);
  wire id_5 = 1'd0;
  assign module_2.id_0 = 0;
  localparam id_6 = 1;
  assign module_1.id_1 = 0;
endmodule
module module_1 (
    output logic id_0,
    output tri   id_1,
    input  wor   id_2,
    input  uwire id_3
);
  always begin : LABEL_0
    id_0 <= -1; 
    @(posedge id_3) id_0 <= 1 != 1;
  end 
  module_0 modCall_1 (
      id_2,
      id_1,
      id_1,
      id_1
  );  
endmodule
module module_2 (
    output logic id_0,
    input  wire  id_1,
    output logic id_2,
    input  tri   id_3,
    input  tri   id_4,
    output wand  id_5
);
  always id_0 <= id_4;
  wire id_7;
  reg  id_8;
  wor  id_9 = id_7 * -1; 
  module_0 modCall_1 (
      id_3,
      id_5,
      id_5,
      id_5
  );  
  localparam id_10 = 1;
  always id_8 <= -1; 
  wire id_11;
  always id_2 <= -1; 
endmodule

here in module_0 id_5 value is initialised where as in module_2 id_7,id_8,id_11 are not
just want to clear here we need every wire reg which are not in the port list to be initialised

and in module_2 module_0 is instantiated with name modCall_1 can ports in them also to be initialised randomly or just above statement is fine

[joaovam]

Hi @markram1729,

Good question. I'm not sure if uninitialized values in Verilog are a problem, it can lead to unspecified behavior but for the purpose of our tool, it's not a problem. Right now, we can only cover lines that cause an error like supply1 id_17, id_18 = -1;.

About the second question, I'm not sure if I understood correctly, today the ports selected when calling another module are chosen randomly. Could you clarify it to me?

[markram1729]

Thank you @joaovam ,your answer clears my two questions
now i will initialise the variables that are non ports(local variables ) in the module , i think supply1 id_17, id_18 = -1; will be covered in that
i see in most generated verilog modules i don't see vectors regs wires , i suppose it will be in future version

[markram1729]

Hey , my apologies for the delay
I have a one observation and would like to have your help , its happening in the build_syntax stage , which variable should have assign value / empty
net_variable_or_decl_assign -> net_variable
net_variable_or_decl_assign -> net_decl_assign this random at build_syntax when creating a chooseProds from map

here i need help is
when net_variable_or_decl_assign -> net_variable araises this should be changed to have net_decl_assign which will at the end comes with value

or should i change in verible to give only one possibility to have property net_decl_assign as shown in json file below

 "net_variable_or_decl_assign": {
    "net_decl_assign": 4,
    "net_variable": 4
  },

[luizademelo]

Hi Rishik, I'm not sure if I fully understood the question, but I think making the change in Verible might be easier. However, not all variables necessarily need to be declared. The issue is that when multiple variables are declared, like in this part of the JSON:

"net_variable_or_decl_assigns ',' net_variable_or_decl_assign"

either none of them should have values, or all of them should.

[markram1729]

My apologies for not making my question clear

when i seen json file -> net_variable_or_decl_assign have two attributes

"net_decl_assign": 4,
    "net_variable": 4

in buildsyntaxtree stage at chimera.cpp , chooseProds will randomly select either net_decl_assign or net_variable

if it selected net_decl_assign then {Generic Identifer ,expression,=} will be its children
or
if it selected net_variable then it won't have value assigned

i have created a draft of possible solution , is this the correct way ?

[markram1729]

I have tried only with seed 1 , have to check if my code breaks more than seed 1

[luizademelo]

Hi! Your PR looks correct. You can also use the scripts/generate_programs script to generate random programs instead of testing with just one seed.

[markram1729]

Yes , I have used it

My bad it's actually ngram =1
All the generated files have consistency of the problem statement

[markram1729]

I have opened the pull request , please check it