From 71b61467e4d9fb4d0b4bcad5c585d2987e3f8d09 Mon Sep 17 00:00:00 2001 From: Martin Erhart Date: Thu, 11 May 2023 08:18:17 +0200 Subject: [PATCH] [Arc] Include the addressing type in the memory type --- include/circt/Dialect/Arc/ArcOps.td | 23 +++++---- include/circt/Dialect/Arc/ArcTypes.td | 6 ++- lib/Dialect/Arc/Transforms/InferMemories.cpp | 27 ++++++++++- .../ArcToLLVM/lower-arc-to-llvm.mlir | 22 ++++----- test/Dialect/Arc/allocate-state.mlir | 24 +++++----- test/Dialect/Arc/basic-errors.mlir | 12 ++--- test/Dialect/Arc/basic.mlir | 48 +++++++++---------- test/Dialect/Arc/canonicalizers.mlir | 22 ++++----- test/Dialect/Arc/infer-memories.mlir | 22 ++++----- test/Dialect/Arc/isolate-clocks.mlir | 12 ++--- .../Arc/legalize-state-update-error.mlir | 12 ++--- test/Dialect/Arc/legalize-state-update.mlir | 32 ++++++------- test/Dialect/Arc/lower-state.mlir | 38 +++++++-------- test/Dialect/Arc/print-state-info-errors.mlir | 6 +-- test/Dialect/Arc/print-state-info.mlir | 2 +- 15 files changed, 171 insertions(+), 137 deletions(-) diff --git a/include/circt/Dialect/Arc/ArcOps.td b/include/circt/Dialect/Arc/ArcOps.td index 916ed148a5ae..051f5c5e6cf9 100644 --- a/include/circt/Dialect/Arc/ArcOps.td +++ b/include/circt/Dialect/Arc/ArcOps.td @@ -281,9 +281,14 @@ def MemoryOp : ArcOp<"memory", [MemoryEffects<[MemAlloc]>]> { class MemoryAndDataTypesMatch : TypesMatchWith< "memory and data types must match", mem, data, "$_self.cast().getWordType()">; +class MemoryAndAddressTypesMatch : TypesMatchWith< + "memory and address types must match", mem, address, + "$_self.cast().getAddressType()">; def MemoryReadPortOp : ArcOp<"memory_read_port", [ - Pure, MemoryAndDataTypesMatch<"memory", "data"> + Pure, + MemoryAndDataTypesMatch<"memory", "data">, + MemoryAndAddressTypesMatch<"memory", "address"> ]> { let summary = "Read port from a memory"; let description = [{ @@ -301,13 +306,14 @@ def MemoryReadPortOp : ArcOp<"memory_read_port", [ let results = (outs AnyInteger:$data); let assemblyFormat = [{ - $memory `[` $address `]` attr-dict `:` type($memory) `,` type($address) + $memory `[` $address `]` attr-dict `:` type($memory) }]; } def MemoryWritePortOp : ArcOp<"memory_write_port", [ MemoryEffects<[MemWrite]>, MemoryAndDataTypesMatch<"memory", "data">, + MemoryAndAddressTypesMatch<"memory", "address">, AttrSizedOperandSegments, ClockedOpInterface ]> { @@ -323,8 +329,7 @@ def MemoryWritePortOp : ArcOp<"memory_write_port", [ let assemblyFormat = [{ $memory `[` $address `]` `,` $data (`mask` `(` $mask^ `:` type($mask) `)`)? - (`if` $enable^)? (`clock` $clock^)? - attr-dict `:` type($memory) `,` type($address) + (`if` $enable^)? (`clock` $clock^)? attr-dict `:` type($memory) }]; let hasVerifier = 1; @@ -334,7 +339,8 @@ def MemoryWritePortOp : ArcOp<"memory_write_port", [ def MemoryReadOp : ArcOp<"memory_read", [ MemoryEffects<[MemRead]>, - MemoryAndDataTypesMatch<"memory", "data"> + MemoryAndDataTypesMatch<"memory", "data">, + MemoryAndAddressTypesMatch<"memory", "address"> ]> { let summary = "Read word from memory"; let arguments = (ins @@ -344,13 +350,14 @@ def MemoryReadOp : ArcOp<"memory_read", [ let results = (outs AnyInteger:$data); let assemblyFormat = [{ - $memory `[` $address `]` attr-dict `:` type($memory) `,` type($address) + $memory `[` $address `]` attr-dict `:` type($memory) }]; } def MemoryWriteOp : ArcOp<"memory_write", [ MemoryEffects<[MemWrite]>, - MemoryAndDataTypesMatch<"memory", "data"> + MemoryAndDataTypesMatch<"memory", "data">, + MemoryAndAddressTypesMatch<"memory", "address"> ]> { let summary = "Write word to memory"; let arguments = (ins @@ -362,7 +369,7 @@ def MemoryWriteOp : ArcOp<"memory_write", [ let assemblyFormat = [{ $memory `[` $address `]` `,` $data (`if` $enable^)? - attr-dict `:` type($memory) `,` type($address) + attr-dict `:` type($memory) }]; let hasFolder = 1; diff --git a/include/circt/Dialect/Arc/ArcTypes.td b/include/circt/Dialect/Arc/ArcTypes.td index c77fccd8e888..7d15b0b46350 100644 --- a/include/circt/Dialect/Arc/ArcTypes.td +++ b/include/circt/Dialect/Arc/ArcTypes.td @@ -27,8 +27,10 @@ def StateType : ArcTypeDef<"State"> { def MemoryType : ArcTypeDef<"Memory"> { let mnemonic = "memory"; - let parameters = (ins "unsigned":$numWords, "::mlir::IntegerType":$wordType); - let assemblyFormat = "`<` $numWords `x` $wordType `>`"; + let parameters = (ins "unsigned":$numWords, + "::mlir::IntegerType":$wordType, + "::mlir::IntegerType":$addressType); + let assemblyFormat = "`<` $numWords `x` $wordType `,` $addressType `>`"; let extraClassDeclaration = [{ unsigned getStride(); diff --git a/lib/Dialect/Arc/Transforms/InferMemories.cpp b/lib/Dialect/Arc/Transforms/InferMemories.cpp index 502dbdb5532e..4ea2fb5dc919 100644 --- a/lib/Dialect/Arc/Transforms/InferMemories.cpp +++ b/lib/Dialect/Arc/Transforms/InferMemories.cpp @@ -77,7 +77,13 @@ void InferMemoriesPass::runOnOperation() { ImplicitLocOpBuilder builder(instOp.getLoc(), instOp); auto wordType = builder.getIntegerType(width); - auto memType = MemoryType::get(&getContext(), depth, wordType); + auto addressTy = dyn_cast(instOp.getOperand(0).getType()); + if (!addressTy) { + instOp.emitError("expected integer type for memory addressing, got ") + << addressTy; + return signalPassFailure(); + } + auto memType = MemoryType::get(&getContext(), depth, wordType, addressTy); auto memOp = builder.create(memType); if (!instOp.getInstanceName().empty()) memOp->setAttr("name", instOp.getInstanceNameAttr()); @@ -101,6 +107,13 @@ void InferMemoriesPass::runOnOperation() { ++argIdx; // skip enable argument auto clock = instOp.getOperand(argIdx++); auto data = instOp.getResult(resultIdx++); + + if (address.getType() != addressTy) { + instOp.emitOpError("expected ") + << addressTy << ", but got " << address.getType(); + return signalPassFailure(); + } + // NOTE: the result of a disabled read port is undefined, currently we // define it to be the same as if it was enabled, but we could also set it // to any constant (e.g., by inserting a mux). @@ -124,6 +137,12 @@ void InferMemoriesPass::runOnOperation() { auto writeMask = maskBits > 1 ? instOp.getOperand(argIdx++) : Value{}; auto readData = instOp.getResult(resultIdx++); + if (address.getType() != addressTy) { + instOp.emitOpError("expected ") + << addressTy << ", but got " << address.getType(); + return signalPassFailure(); + } + // NOTE: the result of a disabled read port is undefined, currently we // define it to be the same as if it was enabled, but we could also set it // to any constant (e.g., by inserting a mux). @@ -161,6 +180,12 @@ void InferMemoriesPass::runOnOperation() { auto data = instOp.getOperand(argIdx++); auto mask = maskBits > 1 ? instOp.getOperand(argIdx++) : Value{}; + if (address.getType() != addressTy) { + instOp.emitOpError("expected ") + << addressTy << ", but got " << address.getType(); + return signalPassFailure(); + } + if (mask) { unsigned maskWidth = mask.getType().cast().getWidth(); SmallVector toConcat; diff --git a/test/Conversion/ArcToLLVM/lower-arc-to-llvm.mlir b/test/Conversion/ArcToLLVM/lower-arc-to-llvm.mlir index 423e03634b2f..53d2a28925a1 100644 --- a/test/Conversion/ArcToLLVM/lower-arc-to-llvm.mlir +++ b/test/Conversion/ArcToLLVM/lower-arc-to-llvm.mlir @@ -18,31 +18,31 @@ arc.define @EmptyArc() { func.func @Types( %arg0: !arc.storage, %arg1: !arc.state, - %arg2: !arc.memory<4 x i7> + %arg2: !arc.memory<4 x i7, i2> ) -> ( !arc.storage, !arc.state, - !arc.memory<4 x i7> + !arc.memory<4 x i7, i2> ) { - return %arg0, %arg1, %arg2 : !arc.storage, !arc.state, !arc.memory<4 x i7> + return %arg0, %arg1, %arg2 : !arc.storage, !arc.state, !arc.memory<4 x i7, i2> // CHECK: llvm.return // CHECK-SAME: !llvm.struct<(ptr, ptr, ptr)> } // CHECK-NEXT: } // CHECK-LABEL: llvm.func @StorageTypes(%arg0: !llvm.ptr) -> !llvm.struct<(ptr, ptr, ptr)> { -func.func @StorageTypes(%arg0: !arc.storage) -> (!arc.state, !arc.memory<4 x i1>, !arc.storage) { +func.func @StorageTypes(%arg0: !arc.storage) -> (!arc.state, !arc.memory<4 x i1, i2>, !arc.storage) { %0 = arc.storage.get %arg0[42] : !arc.storage -> !arc.state // CHECK-NEXT: [[OFFSET:%.+]] = llvm.mlir.constant(42 : // CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[[[OFFSET]]] // CHECK-NEXT: llvm.bitcast [[PTR]] : !llvm.ptr to !llvm.ptr - %1 = arc.storage.get %arg0[43] : !arc.storage -> !arc.memory<4 x i1> + %1 = arc.storage.get %arg0[43] : !arc.storage -> !arc.memory<4 x i1, i2> // CHECK-NEXT: [[OFFSET:%.+]] = llvm.mlir.constant(43 : // CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[[[OFFSET]]] %2 = arc.storage.get %arg0[44] : !arc.storage -> !arc.storage // CHECK-NEXT: [[OFFSET:%.+]] = llvm.mlir.constant(44 : // CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[[[OFFSET]]] - return %0, %1, %2 : !arc.state, !arc.memory<4 x i1>, !arc.storage + return %0, %1, %2 : !arc.state, !arc.memory<4 x i1, i2>, !arc.storage // CHECK: llvm.return } // CHECK-NEXT: } @@ -58,7 +58,7 @@ func.func @StateAllocation(%arg0: !arc.storage<10>) { arc.alloc_state %arg0 {offset = 2} : (!arc.storage<10>) -> !arc.state // CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[2] // CHECK-NEXT: llvm.bitcast [[PTR]] : !llvm.ptr to !llvm.ptr - arc.alloc_memory %arg0 {offset = 3, stride = 1} : (!arc.storage<10>) -> !arc.memory<4 x i1> + arc.alloc_memory %arg0 {offset = 3, stride = 1} : (!arc.storage<10>) -> !arc.memory<4 x i1, i2> // CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[3] arc.alloc_storage %arg0[7] : (!arc.storage<10>) -> !arc.storage<3> // CHECK-NEXT: [[PTR:%.+]] = llvm.getelementptr %arg0[7] @@ -91,7 +91,7 @@ func.func @StateUpdates(%arg0: !arc.storage<1>) { // CHECK-LABEL: llvm.func @MemoryUpdates(%arg0: !llvm.ptr, %arg1: i1) { func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) { - %0 = arc.alloc_memory %arg0 {offset = 0, stride = 6} : (!arc.storage<24>) -> !arc.memory<4 x i42> + %0 = arc.alloc_memory %arg0 {offset = 0, stride = 6} : (!arc.storage<24>) -> !arc.memory<4 x i42, i19> // CHECK-NEXT: [[RAW_PTR:%.+]] = llvm.getelementptr %arg0[0] // CHECK-NEXT: [[PTR:%.+]] = llvm.bitcast [[RAW_PTR]] : !llvm.ptr to !llvm.ptr @@ -100,7 +100,7 @@ func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) { // CHECK-NEXT: llvm.mlir.constant(true // CHECK-NEXT: [[THREE:%.+]] = llvm.mlir.constant(3 - %1 = arc.memory_read %0[%c3_i19] : <4 x i42>, i19 + %1 = arc.memory_read %0[%c3_i19] : <4 x i42, i19> %2 = arith.addi %1, %1 : i42 // CHECK-NEXT: [[ADDR:%.+]] = llvm.zext [[THREE]] : i19 to i20 // CHECK-NEXT: [[FOUR:%.+]] = llvm.mlir.constant(4 @@ -116,7 +116,7 @@ func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) { // CHECK-NEXT: [[BB_RESUME]]([[LOADED:%.+]]: i42): // CHECK: [[ADDED:%.+]] = llvm.add [[LOADED]], [[LOADED]] - arc.memory_write %0[%c3_i19], %2 if %enable : <4 x i42>, i19 + arc.memory_write %0[%c3_i19], %2 if %enable : <4 x i42, i19> // CHECK-NEXT: [[ADDR:%.+]] = llvm.zext [[THREE]] : i19 to i20 // CHECK-NEXT: [[FOUR:%.+]] = llvm.mlir.constant(4 // CHECK-NEXT: [[INBOUNDS:%.+]] = llvm.icmp "ult" [[ADDR]], [[FOUR]] @@ -128,7 +128,7 @@ func.func @MemoryUpdates(%arg0: !arc.storage<24>, %enable: i1) { // CHECK-NEXT: llvm.br [[BB_RESUME]] // CHECK-NEXT: [[BB_RESUME]]: - arc.memory_write %0[%c3_i19], %2 : <4 x i42>, i19 + arc.memory_write %0[%c3_i19], %2 : <4 x i42, i19> // CHECK-NEXT: [[ADDR:%.+]] = llvm.zext [[THREE]] : i19 to i20 // CHECK-NEXT: [[FOUR:%.+]] = llvm.mlir.constant(4 // CHECK-NEXT: [[INBOUNDS:%.+]] = llvm.icmp "ult" [[ADDR]], [[FOUR]] diff --git a/test/Dialect/Arc/allocate-state.mlir b/test/Dialect/Arc/allocate-state.mlir index 011276124818..7f0a172974c6 100644 --- a/test/Dialect/Arc/allocate-state.mlir +++ b/test/Dialect/Arc/allocate-state.mlir @@ -43,25 +43,25 @@ arc.model "test" { // CHECK-NEXT: arc.passthrough { arc.passthrough { // CHECK-NEXT: [[SUBPTR:%.+]] = arc.storage.get [[PTR]][1144] : !arc.storage<5724> -> !arc.storage<4577> - arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i1> - arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i8> - arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i16> - arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i32> - arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i64> - arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i9001> + arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i1, i1> + arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i8, i1> + arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i16, i1> + arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i32, i1> + arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i64, i1> + arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<4 x i9001, i1> arc.alloc_state %arg0 : (!arc.storage) -> !arc.state // CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 0 : i32, stride = 1 : i32} - // CHECK-SAME: -> !arc.memory<4 x i1> + // CHECK-SAME: -> !arc.memory<4 x i1, i1> // CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 4 : i32, stride = 1 : i32} - // CHECK-SAME: -> !arc.memory<4 x i8> + // CHECK-SAME: -> !arc.memory<4 x i8, i1> // CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 8 : i32, stride = 2 : i32} - // CHECK-SAME: -> !arc.memory<4 x i16> + // CHECK-SAME: -> !arc.memory<4 x i16, i1> // CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 16 : i32, stride = 4 : i32} - // CHECK-SAME: -> !arc.memory<4 x i32> + // CHECK-SAME: -> !arc.memory<4 x i32, i1> // CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 32 : i32, stride = 8 : i32} - // CHECK-SAME: -> !arc.memory<4 x i64> + // CHECK-SAME: -> !arc.memory<4 x i64, i1> // CHECK-NEXT: arc.alloc_memory [[SUBPTR]] {offset = 64 : i32, stride = 1128 : i32} - // CHECK-SAME: -> !arc.memory<4 x i9001> + // CHECK-SAME: -> !arc.memory<4 x i9001, i1> // CHECK-NEXT: arc.alloc_state [[SUBPTR]] {offset = 4576 : i32} } // CHECK-NEXT: } diff --git a/test/Dialect/Arc/basic-errors.mlir b/test/Dialect/Arc/basic-errors.mlir index 1d9fc72f03f6..9948743c35af 100644 --- a/test/Dialect/Arc/basic-errors.mlir +++ b/test/Dialect/Arc/basic-errors.mlir @@ -199,8 +199,8 @@ arc.define @lutSideEffects () -> i32 { %0 = arc.lut () : () -> i32 { %true = hw.constant true // expected-note @+1 {{first operation with side-effects here}} - %1 = arc.memory !arc.memory<20 x i32> - %2 = arc.memory_read_port %1[%true] : !arc.memory<20 x i32>, i1 + %1 = arc.memory !arc.memory<20 x i32, i1> + %2 = arc.memory_read_port %1[%true] : !arc.memory<20 x i32, i1> arc.output %2 : i32 } arc.output %0 : i32 @@ -286,10 +286,10 @@ arc.define @dummyArc() { hw.module @memoryWritePortOpInsideClockDomain(%clk: i1) { arc.clock_domain (%clk) clock %clk : (i1) -> () { ^bb0(%arg0: i1): - %mem = arc.memory <4 x i32> + %mem = arc.memory <4 x i32, i32> %c0_i32 = hw.constant 0 : i32 // expected-error @+1 {{inside a clock domain cannot have a clock}} - arc.memory_write_port %mem[%c0_i32], %c0_i32 if %arg0 clock %arg0 : !arc.memory<4 x i32>, i32 + arc.memory_write_port %mem[%c0_i32], %c0_i32 if %arg0 clock %arg0 : !arc.memory<4 x i32, i32> arc.output } } @@ -297,10 +297,10 @@ hw.module @memoryWritePortOpInsideClockDomain(%clk: i1) { // ----- hw.module @memoryWritePortOpOutsideClockDomain(%en: i1) { - %mem = arc.memory <4 x i32> + %mem = arc.memory <4 x i32, i32> %c0_i32 = hw.constant 0 : i32 // expected-error @+1 {{outside a clock domain requires a clock}} - arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en : !arc.memory<4 x i32>, i32 + arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en : !arc.memory<4 x i32, i32> } // ----- diff --git a/test/Dialect/Arc/basic.mlir b/test/Dialect/Arc/basic.mlir index 7ed0ff30737e..e9e68dfbdffa 100644 --- a/test/Dialect/Arc/basic.mlir +++ b/test/Dialect/Arc/basic.mlir @@ -57,10 +57,10 @@ arc.define @LookupTable(%arg0: i32, %arg1: i8) -> () { // CHECK-LABEL: func.func @StorageAccess func.func @StorageAccess(%arg0: !arc.storage<10000>) { // CHECK-NEXT: arc.storage.get %arg0[42] : !arc.storage<10000> -> !arc.state - // CHECK-NEXT: arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19> + // CHECK-NEXT: arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19, i32> // CHECK-NEXT: arc.storage.get %arg0[9001] : !arc.storage<10000> -> !arc.storage<123> %0 = arc.storage.get %arg0[42] : !arc.storage<10000> -> !arc.state - %1 = arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19> + %1 = arc.storage.get %arg0[1337] : !arc.storage<10000> -> !arc.memory<4 x i19, i32> %2 = arc.storage.get %arg0[9001] : !arc.storage<10000> -> !arc.storage<123> return } @@ -110,35 +110,35 @@ hw.module @clockDomainTest(%clk: i1, %in0: i32, %in1: i16) { // CHECK-LABEL: hw.module @memoryOps hw.module @memoryOps(%clk: i1, %en: i1) { %c0_i32 = hw.constant 0 : i32 - // CHECK: [[MEM:%.+]] = arc.memory <4 x i32> - %mem = arc.memory <4 x i32> + // CHECK: [[MEM:%.+]] = arc.memory <4 x i32, i32> + %mem = arc.memory <4 x i32, i32> - // CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM]][%c0_i32] : <4 x i32>, i32 - %0 = arc.memory_read_port %mem[%c0_i32] : <4 x i32>, i32 - // CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 if %en clock %clk : <4 x i32>, i32 - arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en clock %clk : <4 x i32>, i32 - // CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 clock %clk : <4 x i32>, i32 - arc.memory_write_port %mem[%c0_i32], %c0_i32 clock %clk : <4 x i32>, i32 + // CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM]][%c0_i32] : <4 x i32, i32> + %0 = arc.memory_read_port %mem[%c0_i32] : <4 x i32, i32> + // CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 if %en clock %clk : <4 x i32, i32> + arc.memory_write_port %mem[%c0_i32], %c0_i32 if %en clock %clk : <4 x i32, i32> + // CHECK-NEXT: arc.memory_write_port [[MEM]][%c0_i32], %c0_i32 clock %clk : <4 x i32, i32> + arc.memory_write_port %mem[%c0_i32], %c0_i32 clock %clk : <4 x i32, i32> // CHECK-NEXT: arc.clock_domain arc.clock_domain (%clk) clock %clk : (i1) -> () { ^bb0(%arg0: i1): %c1_i32 = hw.constant 1 : i32 - // CHECK: [[MEM2:%.+]] = arc.memory <4 x i32> - %mem2 = arc.memory <4 x i32> - // CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM2]][%c1_i32] : <4 x i32>, i32 - %2 = arc.memory_read_port %mem2[%c1_i32] : <4 x i32>, i32 - // CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 if %arg0 : <4 x i32>, i32 - arc.memory_write_port %mem2[%c1_i32], %c1_i32 if %arg0 : <4 x i32>, i32 - // CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 : <4 x i32>, i32 - arc.memory_write_port %mem2[%c1_i32], %c1_i32 : <4 x i32>, i32 + // CHECK: [[MEM2:%.+]] = arc.memory <4 x i32, i32> + %mem2 = arc.memory <4 x i32, i32> + // CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM2]][%c1_i32] : <4 x i32, i32> + %2 = arc.memory_read_port %mem2[%c1_i32] : <4 x i32, i32> + // CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 if %arg0 : <4 x i32, i32> + arc.memory_write_port %mem2[%c1_i32], %c1_i32 if %arg0 : <4 x i32, i32> + // CHECK-NEXT: arc.memory_write_port [[MEM2]][%c1_i32], %c1_i32 : <4 x i32, i32> + arc.memory_write_port %mem2[%c1_i32], %c1_i32 : <4 x i32, i32> } - // CHECK: %{{.+}} = arc.memory_read [[MEM]][%c0_i32] : <4 x i32>, i32 - %2 = arc.memory_read %mem[%c0_i32] : <4 x i32>, i32 - // CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 if %en : <4 x i32>, i32 - arc.memory_write %mem[%c0_i32], %c0_i32 if %en : <4 x i32>, i32 + // CHECK: %{{.+}} = arc.memory_read [[MEM]][%c0_i32] : <4 x i32, i32> + %2 = arc.memory_read %mem[%c0_i32] : <4 x i32, i32> + // CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 if %en : <4 x i32, i32> + arc.memory_write %mem[%c0_i32], %c0_i32 if %en : <4 x i32, i32> - // CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 : <4 x i32>, i32 - arc.memory_write %mem[%c0_i32], %c0_i32 : <4 x i32>, i32 + // CHECK-NEXT: arc.memory_write [[MEM]][%c0_i32], %c0_i32 : <4 x i32, i32> + arc.memory_write %mem[%c0_i32], %c0_i32 : <4 x i32, i32> } diff --git a/test/Dialect/Arc/canonicalizers.mlir b/test/Dialect/Arc/canonicalizers.mlir index f5b3a1f9dc17..c5c995fcb558 100644 --- a/test/Dialect/Arc/canonicalizers.mlir +++ b/test/Dialect/Arc/canonicalizers.mlir @@ -67,32 +67,32 @@ hw.module @clockDomainDCE(%clk: i1) { } // CHECK-LABEL: hw.module @memoryOps -hw.module @memoryOps(%clk: i1, %mem: !arc.memory<4 x i32>, %addr: i32, %data: i32) { +hw.module @memoryOps(%clk: i1, %mem: !arc.memory<4 x i32, i32>, %addr: i32, %data: i32) { %true = hw.constant true - // CHECK: arc.memory_write_port %mem[%addr], %data clock %clk : <4 x i32>, i32 - arc.memory_write_port %mem[%addr], %data if %true clock %clk : <4 x i32>, i32 - // CHECK-NEXT: arc.memory_write %mem[%addr], %data : <4 x i32>, i32 - arc.memory_write %mem[%addr], %data if %true : <4 x i32>, i32 + // CHECK: arc.memory_write_port %mem[%addr], %data clock %clk : <4 x i32, i32> + arc.memory_write_port %mem[%addr], %data if %true clock %clk : <4 x i32, i32> + // CHECK-NEXT: arc.memory_write %mem[%addr], %data : <4 x i32, i32> + arc.memory_write %mem[%addr], %data if %true : <4 x i32, i32> %false = hw.constant false - arc.memory_write_port %mem[%addr], %data if %false clock %clk : <4 x i32>, i32 - arc.memory_write %mem[%addr], %data if %false : <4 x i32>, i32 + arc.memory_write_port %mem[%addr], %data if %false clock %clk : <4 x i32, i32> + arc.memory_write %mem[%addr], %data if %false : <4 x i32, i32> } // CHECK-LABEL: hw.module @clockDomainCanonicalizer hw.module @clockDomainCanonicalizer(%clk: i1, %data: i32) -> (out0: i32, out1: i1, out2: i32, out3: i32, out4: i32) { %c0_i32 = hw.constant 0 : i32 %true = hw.constant true - %mem = arc.memory <4 x i32> + %mem = arc.memory <4 x i32, i32> // COM: check that memories only used in one clock domain are pulled in and // COM: constants are cloned when used in multiple clock domains. // CHECK: arc.clock_domain () // CHECK-NEXT: [[C0:%.+]] = hw.constant 0 // CHECK-NEXT: [[MEM:%.+]] = arc.memory // CHECK-NEXT: arc.memory_write_port [[MEM]][[[C0]]], [[C0]] : - %0 = arc.clock_domain (%c0_i32, %mem, %true) clock %clk : (i32, !arc.memory<4 x i32>, i1) -> i32 { - ^bb0(%arg0: i32, %arg1: !arc.memory<4 x i32>, %arg2: i1): - arc.memory_write_port %arg1[%arg0], %arg0 if %arg2 : !arc.memory<4 x i32>, i32 + %0 = arc.clock_domain (%c0_i32, %mem, %true) clock %clk : (i32, !arc.memory<4 x i32, i32>, i1) -> i32 { + ^bb0(%arg0: i32, %arg1: !arc.memory<4 x i32, i32>, %arg2: i1): + arc.memory_write_port %arg1[%arg0], %arg0 if %arg2 : !arc.memory<4 x i32, i32> arc.output %arg0 : i32 } // COM: check that unused inputs are removed, and constants are cloned into it diff --git a/test/Dialect/Arc/infer-memories.mlir b/test/Dialect/Arc/infer-memories.mlir index dbf2717ece68..374b476439f9 100644 --- a/test/Dialect/Arc/infer-memories.mlir +++ b/test/Dialect/Arc/infer-memories.mlir @@ -6,8 +6,8 @@ hw.generator.schema @FIRRTLMem, "FIRRTL_Memory", ["depth", "numReadPorts", "numW // CHECK-LABEL: hw.module @TestWOMemory( hw.module @TestWOMemory(%clock: i1, %addr: i10, %enable: i1, %data: i8) { // CHECK-NOT: hw.instance - // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8> {name = "foo"} - // CHECK-NEXT: arc.memory_write_port [[FOO]][%addr], %data if %enable clock %clock : <1024 x i8>, i10 + // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"} + // CHECK-NEXT: arc.memory_write_port [[FOO]][%addr], %data if %enable clock %clock : <1024 x i8, i10> // CHECK-NEXT: hw.output hw.instance "foo" @WOMemory(W0_addr: %addr: i10, W0_en: %enable: i1, W0_clk: %clock: i1, W0_data: %data: i8) -> () } @@ -19,13 +19,13 @@ hw.module.generated @WOMemory, @FIRRTLMem(%W0_addr: i10, %W0_en: i1, %W0_clk: i1 // CHECK-LABEL: hw.module @TestWOMemoryWithMask( hw.module @TestWOMemoryWithMask(%clock: i1, %addr: i10, %enable: i1, %data: i16, %mask: i2) { // CHECK-NOT: hw.instance - // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i16> {name = "foo"} + // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i16, i10> {name = "foo"} // CHECK-NEXT: [[MASK_BIT0:%.+]] = comb.extract %mask from 0 : (i2) -> i1 // CHECK-NEXT: [[MASK_BYTE0:%.+]] = comb.replicate [[MASK_BIT0]] : (i1) -> i8 // CHECK-NEXT: [[MASK_BIT1:%.+]] = comb.extract %mask from 1 : (i2) -> i1 // CHECK-NEXT: [[MASK_BYTE1:%.+]] = comb.replicate [[MASK_BIT1]] : (i1) -> i8 // CHECK-NEXT: [[MASK:%.+]] = comb.concat [[MASK_BYTE0]], [[MASK_BYTE1]] - // CHECK-NEXT: arc.memory_write_port [[FOO]][%addr], %data mask([[MASK]] : i16) if %enable clock %clock : <1024 x i16>, i10 + // CHECK-NEXT: arc.memory_write_port [[FOO]][%addr], %data mask([[MASK]] : i16) if %enable clock %clock : <1024 x i16, i10> // CHECK-NEXT: hw.output hw.instance "foo" @WOMemoryWithMask(W0_addr: %addr: i10, W0_en: %enable: i1, W0_clk: %clock: i1, W0_data: %data: i16, W0_mask: %mask: i2) -> () } @@ -37,8 +37,8 @@ hw.module.generated @WOMemoryWithMask, @FIRRTLMem(%W0_addr: i10, %W0_en: i1, %W0 // CHECK-LABEL: hw.module @TestROMemory( hw.module @TestROMemory(%clock: i1, %addr: i10, %enable: i1) -> (data: i8) { // CHECK-NOT: hw.instance - // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8> {name = "foo"} - // CHECK-NEXT: [[RDATA:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8>, i10 + // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"} + // CHECK-NEXT: [[RDATA:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8, i10> // CHECK-NEXT: hw.output [[RDATA]] %0 = hw.instance "foo" @ROMemory(R0_addr: %addr: i10, R0_en: %enable: i1, R0_clk: %clock: i1) -> (R0_data: i8) hw.output %0 : i8 @@ -51,8 +51,8 @@ hw.module.generated @ROMemory, @FIRRTLMem(%R0_addr: i10, %R0_en: i1, %R0_clk: i1 // CHECK-LABEL: hw.module @TestROMemoryWithLatency( hw.module @TestROMemoryWithLatency(%clock: i1, %addr: i10, %enable: i1) -> (data: i8) { // CHECK-NOT: hw.instance - // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8> {name = "foo"} - // CHECK-NEXT: [[D0:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8>, i10 + // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"} + // CHECK-NEXT: [[D0:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8, i10> // CHECK-NEXT: [[D1:%.+]] = seq.compreg {{.+}} [[D0]], %clock // CHECK-NEXT: [[D2:%.+]] = seq.compreg {{.+}} [[D1]], %clock // CHECK-NEXT: [[D3:%.+]] = seq.compreg {{.+}} [[D2]], %clock @@ -68,10 +68,10 @@ hw.module.generated @ROMemoryWithLatency, @FIRRTLMem(%R0_addr: i10, %R0_en: i1, // CHECK-LABEL: hw.module @TestRWMemory( hw.module @TestRWMemory(%clock: i1, %addr: i10, %enable: i1, %wmode: i1, %wdata: i8) -> (rdata: i8) { // CHECK-NOT: hw.instance - // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8> {name = "foo"} - // CHECK-NEXT: [[RDATA:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8>, i10 + // CHECK-NEXT: [[FOO:%.+]] = arc.memory <1024 x i8, i10> {name = "foo"} + // CHECK-NEXT: [[RDATA:%.+]] = arc.memory_read_port [[FOO]][%addr] : <1024 x i8, i10> // CHECK-NEXT: [[WENABLE:%.+]] = comb.and %enable, %wmode - // CHECK-NEXT: arc.memory_write_port [[FOO]][%addr], %wdata if [[WENABLE]] clock %clock : <1024 x i8>, i10 + // CHECK-NEXT: arc.memory_write_port [[FOO]][%addr], %wdata if [[WENABLE]] clock %clock : <1024 x i8, i10> // CHECK-NEXT: hw.output [[RDATA]] %0 = hw.instance "foo" @RWMemory(RW0_addr: %addr: i10, RW0_en: %enable: i1, RW0_clk: %clock: i1, RW0_wmode: %wmode: i1, RW0_wdata: %wdata: i8) -> (RW0_rdata: i8) hw.output %0 : i8 diff --git a/test/Dialect/Arc/isolate-clocks.mlir b/test/Dialect/Arc/isolate-clocks.mlir index e23143972656..3ad87ab46495 100644 --- a/test/Dialect/Arc/isolate-clocks.mlir +++ b/test/Dialect/Arc/isolate-clocks.mlir @@ -6,10 +6,10 @@ hw.module @basics(%clk0: i1, %clk1: i1, %clk2: i1, %c0: i1, %c1: i1, %in: i32) - // COM: are not considered clocked, clock domain materialization %0 = comb.and %c0, %c1 : i1 %1 = arc.state @DummyArc(%in) clock %clk0 enable %0 reset %c1 lat 1 : (i32) -> i32 - %mem = arc.memory <2 x i32> - arc.memory_write_port %mem[%c0], %2 clock %clk0 : <2 x i32>, i1 + %mem = arc.memory <2 x i32, i1> + arc.memory_write_port %mem[%c0], %2 clock %clk0 : <2 x i32, i1> %2 = arc.state @DummyArc(%in) clock %clk0 lat 1 : (i32) -> i32 - arc.memory_write_port %mem[%c1], %1 clock %clk0 : <2 x i32>, i1 + arc.memory_write_port %mem[%c1], %1 clock %clk0 : <2 x i32, i1> %3 = arc.state @DummyArc(%4) clock %clk1 enable %0 reset %c1 lat 1 : (i32) -> i32 %4 = arc.state @DummyArc(%2) lat 0 : (i32) -> i32 %5 = arc.state @DummyArc(%4) clock %clk2 lat 1 : (i32) -> i32 @@ -19,10 +19,10 @@ hw.module @basics(%clk0: i1, %clk1: i1, %clk2: i1, %c0: i1, %c1: i1, %in: i32) - // CHECK-NEXT: [[V1:%.+]] = arc.state @DummyArc([[V2:%.+]]) lat 0 : (i32) -> i32 // CHECK-NEXT: [[V2]] = arc.clock_domain (%c1, %in, %c0, [[V0]]) clock %clk0 : (i1, i32, i1, i1) -> i32 { // CHECK-NEXT: ^bb0(%arg0: i1, %arg1: i32, %arg2: i1, %arg3: i1): - // CHECK-NEXT: [[MEM:%.+]] = arc.memory <2 x i32> - // CHECK-NEXT: arc.memory_write_port [[MEM]][%arg0], [[V7:%.+]] : <2 x i32>, i1 + // CHECK-NEXT: [[MEM:%.+]] = arc.memory <2 x i32, i1> + // CHECK-NEXT: arc.memory_write_port [[MEM]][%arg0], [[V7:%.+]] : <2 x i32, i1> // CHECK-NEXT: [[V6:%.+]] = arc.state @DummyArc(%arg1) lat 1 : (i32) -> i32 - // CHECK-NEXT: arc.memory_write_port [[MEM]][%arg2], [[V6]] : <2 x i32>, i1 + // CHECK-NEXT: arc.memory_write_port [[MEM]][%arg2], [[V6]] : <2 x i32, i1> // CHECK-NEXT: [[V7]] = arc.state @DummyArc(%arg1) enable %arg3 reset %arg0 lat 1 : (i32) -> i32 // CHECK-NEXT: arc.output [[V6]] : i32 // CHECK-NEXT: } diff --git a/test/Dialect/Arc/legalize-state-update-error.mlir b/test/Dialect/Arc/legalize-state-update-error.mlir index 42bdda25d40e..b19d395f75cb 100644 --- a/test/Dialect/Arc/legalize-state-update-error.mlir +++ b/test/Dialect/Arc/legalize-state-update-error.mlir @@ -7,16 +7,16 @@ arc.model "Memory" { %r1 = arc.state_read %s1 : scf.if %false { // expected-error @+1 {{could not be moved to be after all reads to the same memory}} - arc.memory_write %mem2[%false], %r1 : <2 x i32>, i1 - %mr1 = arc.memory_read %mem1[%false] : <2 x i32>, i1 + arc.memory_write %mem2[%false], %r1 : <2 x i32, i1> + %mr1 = arc.memory_read %mem1[%false] : <2 x i32, i1> } scf.if %false { - arc.memory_write %mem1[%false], %r1 : <2 x i32>, i1 + arc.memory_write %mem1[%false], %r1 : <2 x i32, i1> // expected-note @+1 {{could not be moved after this read}} - %mr1 = arc.memory_read %mem2[%false] : <2 x i32>, i1 + %mr1 = arc.memory_read %mem2[%false] : <2 x i32, i1> } } - %mem1 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32> - %mem2 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32> + %mem1 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32, i1> + %mem2 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32, i1> %s1 = arc.alloc_state %arg0 : (!arc.storage) -> !arc.state } diff --git a/test/Dialect/Arc/legalize-state-update.mlir b/test/Dialect/Arc/legalize-state-update.mlir index a3affccc4133..a3e93d3a0f02 100644 --- a/test/Dialect/Arc/legalize-state-update.mlir +++ b/test/Dialect/Arc/legalize-state-update.mlir @@ -199,10 +199,10 @@ arc.model "Memory" { // CHECK-NEXT: arc.memory_read [[MEM2:%.+]][%false] // CHECK-NEXT: arc.memory_write [[MEM2]] %r1 = arc.state_read %s1 : - arc.memory_write %mem2[%false], %r1 : <2 x i32>, i1 - arc.memory_write %mem1[%false], %r1 : <2 x i32>, i1 - %mr1 = arc.memory_read %mem1[%false] : <2 x i32>, i1 - %mr2 = arc.memory_read %mem2[%false] : <2 x i32>, i1 + arc.memory_write %mem2[%false], %r1 : <2 x i32, i1> + arc.memory_write %mem1[%false], %r1 : <2 x i32, i1> + %mr1 = arc.memory_read %mem1[%false] : <2 x i32, i1> + %mr2 = arc.memory_read %mem2[%false] : <2 x i32, i1> // CHECK-NEXT: } } // CHECK: arc.clock_tree %false attributes {ct2} @@ -214,10 +214,10 @@ arc.model "Memory" { // CHECK-NEXT: } // CHECK-NEXT: arc.memory_write %r1 = arc.state_read %s1 : - arc.memory_write %mem1[%false], %r1 : <2 x i32>, i1 - %mr1 = arc.memory_read %mem1[%false] : <2 x i32>, i1 + arc.memory_write %mem1[%false], %r1 : <2 x i32, i1> + %mr1 = arc.memory_read %mem1[%false] : <2 x i32, i1> scf.if %false { - %mr2 = arc.memory_read %mem1[%false] : <2 x i32>, i1 + %mr2 = arc.memory_read %mem1[%false] : <2 x i32, i1> } // CHECK-NEXT: } } @@ -235,19 +235,19 @@ arc.model "Memory" { // CHECK-NEXT: } scf.if %false { %r1 = arc.state_read %s1 : - arc.memory_write %mem1[%false], %r1 : <2 x i32>, i1 + arc.memory_write %mem1[%false], %r1 : <2 x i32, i1> scf.if %false { - arc.memory_write %mem2[%false], %r1 : <2 x i32>, i1 - %mr3 = arc.memory_read %mem1[%false] : <2 x i32>, i1 + arc.memory_write %mem2[%false], %r1 : <2 x i32, i1> + %mr3 = arc.memory_read %mem1[%false] : <2 x i32, i1> } } - %mr1 = arc.memory_read %mem1[%false] : <2 x i32>, i1 - %mr2 = arc.memory_read %mem2[%false] : <2 x i32>, i1 + %mr1 = arc.memory_read %mem1[%false] : <2 x i32, i1> + %mr2 = arc.memory_read %mem2[%false] : <2 x i32, i1> // CHECK-NEXT: } } - // CHECK: [[MEM1]] = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32> - // CHECK: [[MEM2]] = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32> - %mem1 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32> - %mem2 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32> + // CHECK: [[MEM1]] = arc.alloc_memory %arg0 : + // CHECK: [[MEM2]] = arc.alloc_memory %arg0 : + %mem1 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32, i1> + %mem2 = arc.alloc_memory %arg0 : (!arc.storage) -> !arc.memory<2 x i32, i1> %s1 = arc.alloc_state %arg0 : (!arc.storage) -> !arc.state } diff --git a/test/Dialect/Arc/lower-state.mlir b/test/Dialect/Arc/lower-state.mlir index 13961caa4a75..dba0c01b69b3 100644 --- a/test/Dialect/Arc/lower-state.mlir +++ b/test/Dialect/Arc/lower-state.mlir @@ -79,34 +79,34 @@ arc.define @DummyArc(%arg0: i42) -> i42 { hw.module @NonMaskedMemoryWrite(%clk0: i1) { %c0_i2 = hw.constant 0 : i2 %c9001_i42 = hw.constant 9001 : i42 - %mem = arc.memory <4 x i42> - arc.memory_write_port %mem[%c0_i2], %c9001_i42 clock %clk0 : <4 x i42>, i2 + %mem = arc.memory <4 x i42, i2> + arc.memory_write_port %mem[%c0_i2], %c9001_i42 clock %clk0 : <4 x i42, i2> // CHECK-NEXT: ([[PTR:%.+]]: !arc.storage): // CHECK-NEXT: [[INCLK0:%.+]] = arc.root_input "clk0", [[PTR]] : (!arc.storage) -> !arc.state - // CHECK-NEXT: [[MEM:%.+]] = arc.alloc_memory [[PTR]] : (!arc.storage) -> !arc.memory<4 x i42> + // CHECK-NEXT: [[MEM:%.+]] = arc.alloc_memory [[PTR]] : (!arc.storage) -> !arc.memory<4 x i42, i2> // CHECK-NEXT: [[CLK0:%.+]] = arc.state_read [[INCLK0]] : // CHECK-NEXT: arc.clock_tree [[CLK0]] { - // CHECK: arc.memory_write [[MEM]][%c0_i2], %c9001_i42 : <4 x i42>, i2 + // CHECK: arc.memory_write [[MEM]][%c0_i2], %c9001_i42 : <4 x i42, i2> // CHECK-NEXT: } } // CHECK-LABEL: arc.model "lowerMemoryReadPorts" hw.module @lowerMemoryReadPorts() -> (out0: i42, out1: i42) { %c0_i2 = hw.constant 0 : i2 - %mem = arc.memory <4 x i42> - // CHECK: arc.memory_read {{%.+}}[%c0_i2] : <4 x i42>, i2 - %0 = arc.memory_read_port %mem[%c0_i2] : <4 x i42>, i2 + %mem = arc.memory <4 x i42, i2> + // CHECK: arc.memory_read {{%.+}}[%c0_i2] : <4 x i42, i2> + %0 = arc.memory_read_port %mem[%c0_i2] : <4 x i42, i2> // CHECK: func.call @arcWithMemoryReadsIsLowered - %1 = arc.call @arcWithMemoryReadsIsLowered(%mem) : (!arc.memory<4 x i42>) -> i42 + %1 = arc.call @arcWithMemoryReadsIsLowered(%mem) : (!arc.memory<4 x i42, i2>) -> i42 hw.output %0, %1 : i42, i42 } -// CHECK-LABEL: func.func @arcWithMemoryReadsIsLowered(%arg0: !arc.memory<4 x i42>) -> i42 attributes {llvm.linkage = #llvm.linkage} -arc.define @arcWithMemoryReadsIsLowered(%mem: !arc.memory<4 x i42>) -> i42 { +// CHECK-LABEL: func.func @arcWithMemoryReadsIsLowered(%arg0: !arc.memory<4 x i42, i2>) -> i42 attributes {llvm.linkage = #llvm.linkage} +arc.define @arcWithMemoryReadsIsLowered(%mem: !arc.memory<4 x i42, i2>) -> i42 { %c0_i2 = hw.constant 0 : i2 - // CHECK: arc.memory_read {{%.+}}[%c0_i2] : <4 x i42>, i2 - %0 = arc.memory_read_port %mem[%c0_i2] : <4 x i42>, i2 + // CHECK: arc.memory_read {{%.+}}[%c0_i2] : <4 x i42, i2> + %0 = arc.memory_read_port %mem[%c0_i2] : <4 x i42, i2> // CHECK-NEXT: return arc.output %0 : i42 } @@ -117,18 +117,18 @@ hw.module @maskedMemoryWrite(%clk: i1) { %c0_i2 = hw.constant 0 : i2 %c9001_i42 = hw.constant 9001 : i42 %c1010_i42 = hw.constant 1010 : i42 - %mem = arc.memory <4 x i42> - arc.memory_write_port %mem[%c0_i2], %c9001_i42 mask (%c1010_i42 : i42) if %true clock %clk : <4 x i42>, i2 + %mem = arc.memory <4 x i42, i2> + arc.memory_write_port %mem[%c0_i2], %c9001_i42 mask (%c1010_i42 : i42) if %true clock %clk : <4 x i42, i2> } // CHECK: %c9001_i42 = hw.constant 9001 : i42 // CHECK: %c1010_i42 = hw.constant 1010 : i42 -// CHECK: [[RD:%.+]] = arc.memory_read [[MEM:%.+]][%c0_i2] : <4 x i42>, i2 +// CHECK: [[RD:%.+]] = arc.memory_read [[MEM:%.+]][%c0_i2] : <4 x i42, i2> // CHECK: %c-1_i42 = hw.constant -1 : i42 // CHECK: [[NEG_MASK:%.+]] = comb.xor bin %c1010_i42, %c-1_i42 : i42 // CHECK: [[OLD_MASKED:%.+]] = comb.and bin [[NEG_MASK]], [[RD]] : i42 // CHECK: [[NEW_MASKED:%.+]] = comb.and bin %c1010_i42, %c9001_i42 : i42 // CHECK: [[DATA:%.+]] = comb.or bin [[OLD_MASKED]], [[NEW_MASKED]] : i42 -// CHECK: arc.memory_write [[MEM]][%c0_i2], [[DATA]] if %true : <4 x i42>, i2 +// CHECK: arc.memory_write [[MEM]][%c0_i2], [[DATA]] if %true : <4 x i42, i2> // CHECK-LABEL: arc.model "Taps" hw.module @Taps() { @@ -273,9 +273,9 @@ arc.define @CombLoopRegressionArc2(%arg0: i1) -> (i1, i1) { // Regression check for invalid memory port lowering errors. // CHECK-LABEL: arc.model "MemoryPortRegression" hw.module private @MemoryPortRegression(%clock: i1, %reset: i1, %in: i3) -> (x: i3) { - %0 = arc.memory <2 x i3> {name = "ram_ext"} - %1 = arc.memory_read_port %0[%3] : <2 x i3>, i1 - arc.memory_write_port %0[%3], %in clock %clock : <2 x i3>, i1 + %0 = arc.memory <2 x i3, i1> {name = "ram_ext"} + %1 = arc.memory_read_port %0[%3] : <2 x i3, i1> + arc.memory_write_port %0[%3], %in clock %clock : <2 x i3, i1> %3 = arc.state @Queue_arc_0(%reset) clock %clock lat 1 {names = ["value"]} : (i1) -> i1 %4 = arc.state @Queue_arc_1(%1) lat 0 : (i3) -> i3 hw.output %4 : i3 diff --git a/test/Dialect/Arc/print-state-info-errors.mlir b/test/Dialect/Arc/print-state-info-errors.mlir index 83173ac94346..8b2d306bb260 100644 --- a/test/Dialect/Arc/print-state-info-errors.mlir +++ b/test/Dialect/Arc/print-state-info-errors.mlir @@ -37,14 +37,14 @@ arc.model "Foo" { arc.model "Foo" { ^bb0(%arg0: !arc.storage<42>): // ignore unnamed - arc.alloc_memory %arg0 : (!arc.storage<42>) -> !arc.memory<4 x i1> + arc.alloc_memory %arg0 : (!arc.storage<42>) -> !arc.memory<4 x i1, i2> // expected-error @below {{'arc.alloc_memory' op without allocated offset}} - arc.alloc_memory %arg0 {name = "foo"} : (!arc.storage<42>) -> !arc.memory<4 x i1> + arc.alloc_memory %arg0 {name = "foo"} : (!arc.storage<42>) -> !arc.memory<4 x i1, i2> } // ----- arc.model "Foo" { ^bb0(%arg0: !arc.storage<42>): // expected-error @below {{'arc.alloc_memory' op without allocated stride}} - arc.alloc_memory %arg0 {name = "foo", offset = 8} : (!arc.storage<42>) -> !arc.memory<4 x i1> + arc.alloc_memory %arg0 {name = "foo", offset = 8} : (!arc.storage<42>) -> !arc.memory<4 x i1, i2> } diff --git a/test/Dialect/Arc/print-state-info.mlir b/test/Dialect/Arc/print-state-info.mlir index 1724150f9400..9d9bc8a5b097 100644 --- a/test/Dialect/Arc/print-state-info.mlir +++ b/test/Dialect/Arc/print-state-info.mlir @@ -37,7 +37,7 @@ arc.model "Bar" { // CHECK-NEXT: "type": "memory" // CHECK-NEXT: "stride": 3 // CHECK-NEXT: "depth": 5 - arc.alloc_memory %arg0 {name = "y", offset = 48, stride = 3} : (!arc.storage<9001>) -> !arc.memory<5 x i17> + arc.alloc_memory %arg0 {name = "y", offset = 48, stride = 3} : (!arc.storage<9001>) -> !arc.memory<5 x i17, i3> // CHECK: "name": "z" // CHECK-NEXT: "offset": 92