From b3a54e355706470ccc4f2e6e4c0cab21343aad9b Mon Sep 17 00:00:00 2001
From: Will Dietz <will.dietz@sifive.com>
Date: Fri, 9 Aug 2024 18:56:27 -0500
Subject: [PATCH] LLVM bump to include upstream verifier performance fix.
 (#7496)

Bump LLVM [1] to include an upstream verifier performance fix [2].

This required two minor fixes to CIRCT:

  * [HW] Qualify types for safer use in other dialects.
  * [ImportVerilog] Fix ternary with diff types, both become Value.

[1]: https://github.com/llvm/llvm-project/compare/5689cccead7b70d8eeae4c641e8078e6d3c50b9a...c69b8c445a6b7efd29e67b665adaf04575f3ed92
[2]: https://github.com/llvm/llvm-project/commit/7a98071da2d3e126bacd6c004d2f5d8ecaae7819
---
 include/circt/Dialect/HW/HWTypes.td          | 4 ++--
 lib/Conversion/ImportVerilog/Expressions.cpp | 4 +++-
 llvm                                         | 2 +-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/include/circt/Dialect/HW/HWTypes.td b/include/circt/Dialect/HW/HWTypes.td
index f2f8c1c8bceb..431ed6c34857 100644
--- a/include/circt/Dialect/HW/HWTypes.td
+++ b/include/circt/Dialect/HW/HWTypes.td
@@ -39,7 +39,7 @@ def HWNonInOutType : DialectType<HWDialect,
 
 def InOutType : DialectType<HWDialect,
     CPred<"::circt::hw::type_isa<circt::hw::InOutType>($_self)">,
-          "InOutType", "InOutType">;
+          "InOutType", "::circt::hw::InOutType">;
 
 class InOutTypeOf<list<Type> allowedTypes>
   : ContainerType<AnyTypeOf<allowedTypes>, CPred<"::circt::hw::type_isa<::circt::hw::InOutType>($_self)">,
@@ -62,7 +62,7 @@ def StructType : DialectType<HWDialect,
 // A handle to refer to circt::hw::UnionType in ODS.
 def UnionType : DialectType<HWDialect,
     CPred<"::circt::hw::type_isa<circt::hw::UnionType>($_self)">,
-          "a UnionType", "::circt::hw::TypeAliasOr<hw::UnionType>">;
+          "a UnionType", "::circt::hw::TypeAliasOr<::circt::hw::UnionType>">;
 
 // A handle to refer to circt::hw::EnumType in ODS.
 def EnumType : DialectType<HWDialect,
diff --git a/lib/Conversion/ImportVerilog/Expressions.cpp b/lib/Conversion/ImportVerilog/Expressions.cpp
index b9e26c8590ca..dc8b370129c7 100644
--- a/lib/Conversion/ImportVerilog/Expressions.cpp
+++ b/lib/Conversion/ImportVerilog/Expressions.cpp
@@ -178,7 +178,9 @@ struct RvalueExprVisitor {
         isInc ? builder.create<moore::AddOp>(loc, preValue, one).getResult()
               : builder.create<moore::SubOp>(loc, preValue, one).getResult();
     builder.create<moore::BlockingAssignOp>(loc, arg, postValue);
-    return isPost ? preValue : postValue;
+    if (isPost)
+      return preValue;
+    return postValue;
   }
 
   // Handle unary operators.
diff --git a/llvm b/llvm
index 5689cccead7b..c69b8c445a6b 160000
--- a/llvm
+++ b/llvm
@@ -1 +1 @@
-Subproject commit 5689cccead7b70d8eeae4c641e8078e6d3c50b9a
+Subproject commit c69b8c445a6b7efd29e67b665adaf04575f3ed92