diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
index bd34f4430c3a..587eaf654e87 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
@@ -1424,6 +1424,23 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
   case Builtin::BI__builtin_matrix_column_major_store:
     llvm_unreachable("BI__builtin_matrix_column_major_store NYI");
 
+  case Builtin::BI__builtin_isinf_sign: {
+    CIRGenFunction::CIRGenFPOptionsRAII FPOptsRAII(*this, E);
+    mlir::Location Loc = getLoc(E->getBeginLoc());
+    mlir::Value Arg = emitScalarExpr(E->getArg(0));
+    mlir::Value AbsArg = builder.create<cir::FAbsOp>(Loc, Arg.getType(), Arg);
+    mlir::Value IsInf =
+        builder.createIsFPClass(Loc, AbsArg, FPClassTest::fcInf);
+    mlir::Value IsNeg = emitSignBit(Loc, *this, Arg);
+    auto IntTy = convertType(E->getType());
+    auto Zero = builder.getNullValue(IntTy, Loc);
+    auto One = builder.getConstant(Loc, cir::IntAttr::get(IntTy, 1));
+    auto NegativeOne = builder.getConstant(Loc, cir::IntAttr::get(IntTy, -1));
+    auto SignResult = builder.createSelect(Loc, IsNeg, NegativeOne, One);
+    auto Result = builder.createSelect(Loc, IsInf, SignResult, Zero);
+    return RValue::get(Result);
+  }
+
   case Builtin::BI__builtin_flt_rounds:
     llvm_unreachable("BI__builtin_flt_rounds NYI");
 
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index 833d256d0404..7832d77335e0 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -4067,9 +4067,7 @@ mlir::LogicalResult CIRToLLVMSignBitOpLowering::matchAndRewrite(
   auto zero = rewriter.create<mlir::LLVM::ConstantOp>(op->getLoc(), intTy, 0);
   auto cmpResult = rewriter.create<mlir::LLVM::ICmpOp>(
       op.getLoc(), mlir::LLVM::ICmpPredicate::slt, bitcast.getResult(), zero);
-  auto converted = rewriter.create<mlir::LLVM::ZExtOp>(
-      op.getLoc(), getTypeConverter()->convertType(op.getType()), cmpResult);
-  rewriter.replaceOp(op, converted);
+  rewriter.replaceOp(op, cmpResult);
   return mlir::success();
 }
 
diff --git a/clang/test/CIR/CodeGen/builtin-isinf-sign.c b/clang/test/CIR/CodeGen/builtin-isinf-sign.c
new file mode 100644
index 000000000000..887cf12d875c
--- /dev/null
+++ b/clang/test/CIR/CodeGen/builtin-isinf-sign.c
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll
+// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
+
+int test_float_isinf_sign(float x) {
+    // CIR-LABEL: test_float_isinf_sign
+    // CIR: %[[TMP0:.*]] = cir.load %{{.*}} : !cir.ptr<!cir.float>, !cir.float
+    // CIR: %[[TMP1:.*]] = cir.fabs %[[TMP0]] : !cir.float
+    // CIR: %[[IS_INF:.*]] = cir.is_fp_class %[[TMP1]], 516 : (!cir.float) -> !cir.bool
+    // CIR: %[[IS_NEG:.*]] = cir.signbit %[[TMP0]] : !cir.float -> !cir.bool
+    // CIR: %[[C_0:.*]] = cir.const #cir.int<0> : !s32i
+    // CIR: %[[C_1:.*]] = cir.const #cir.int<1> : !s32i
+    // CIR: %[[C_m1:.*]] = cir.const #cir.int<-1> : !s32i
+    // CIR: %[[TMP4:.*]] = cir.select if %[[IS_NEG]] then %[[C_m1]] else %[[C_1]] : (!cir.bool, !s32i, !s32i) -> !s32i
+    // CIR: %[[RET:.*]] = cir.select if %[[IS_INF]] then %[[TMP4]] else %[[C_0]] : (!cir.bool, !s32i, !s32i) -> !s32i
+    // CIR: cir.store %[[RET]], %{{.*}} : !s32i, !cir.ptr<!s32i>
+
+    // LLVM-LABEL: test_float_isinf_sign
+    // LLVM: %[[TMP0:.*]] = load float, ptr %{{.*}}
+    // LLVM: %[[TMP1:.*]] = call float @llvm.fabs.f32(float %[[TMP0]])
+    // LLVM: %[[IS_INF:.*]] = call i1 @llvm.is.fpclass.f32(float %[[TMP1]], i32 516)
+    // LLVM: %[[TMP1:.*]] = bitcast float %[[TMP0]] to i32
+    // LLVM: %[[IS_NEG:.*]] = icmp slt i32 %[[TMP1]], 0
+    // LLVM: %[[TMP2:.*]] = select i1 %[[IS_NEG]], i32 -1, i32 1
+    // LLVM: %[[RET:.*]] = select i1 %[[IS_INF]], i32 %[[TMP2]], i32 0
+    // LLVM: store i32 %[[RET]], ptr %{{.*}}, align 4
+    return __builtin_isinf_sign(x);
+}