Autogenerate test.

Author: jofrn

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -456,10 +456,10 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
 
-  SDValue Result = DAG.getAtomic(ISD::ATOMIC_LOAD, SDLoc(N),
-      N->getMemoryVT().getVectorElementType(),
-      N->getValueType(0).getVectorElementType(),
-      N->getChain(), N->getBasePtr(), N->getMemOperand());
+  SDValue Result = DAG.getAtomic(
+      ISD::ATOMIC_LOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
+      N->getValueType(0).getVectorElementType(), N->getChain(), N->getBasePtr(),
+      N->getMemOperand());
 
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.

llvm/test/CodeGen/X86/atomic-scalarization.ll

@@ -1,16 +1,11 @@
-; RUN: llc %s --mtriple=x86_64 -print-after=unpack-mi-bundles -disable-verify 2>&1 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc %s --mtriple=x86_64 | FileCheck %s
 
-define i32 @atomic_scalar() {
-; CHECK: # *** IR Dump After Unpack machine instruction bundles (unpack-mi-bundles) ***:
-; CHECK-NEXT: # Machine code for function atomic_scalar: NoPHIs, TracksLiveness, NoVRegs, TiedOpsRewritten, TracksDebugUserValues
-; CHECK-NEXT: Frame Objects:
-; CHECK-NEXT:   fi#0: size=4, align=4, at location [SP-4]
-; CHECK:      bb.0 (%ir-block.0):
-; CHECK-NEXT:   renamable $eax = MOV32rm $rsp, 1, $noreg, -4, $noreg :: (dereferenceable load acquire (s32) from %ir.1)
-; CHECK-NEXT:   RET64 $eax
-; CHECK:      # End machine code for function atomic_scalar.
-  %1 = alloca <1 x i32>
-  %2 = load atomic <1 x i32>, ptr %1 acquire, align 4
-  %3 = extractelement <1 x i32> %2, i32 0
-  ret i32 %3
+define <1 x i32> @atomic_scalar_i32(ptr %x) {
+; CHECK-LABEL: atomic_scalar_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    retq
+  %ret = load atomic <1 x i32>, ptr %x acquire, align 4
+  ret <1 x i32> %ret
 }