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petar-avramovicpetar-avramovic
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AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc
Uniform S1: Truncs to uniform S1 and AnyExts from S1 are left as is as they are meant to be combined away. Uniform S1 ZExt and SExt are lowered using select. Divergent S1: Trunc of VGPR to VCC is lowered as compare. Extends of VCC are lowered using select. For remaining types: S32 to S64 ZExt and SExt are lowered using merge values, AnyExt and Trunc are again left as is to be combined away. Notably uniform S16 for SExt and Zext is not lowered to S32 and left as is for instruction select to deal with them. This is because there are patterns that check for S16 type.
1 parent 8f5d0d7 commit 2ac46e4

8 files changed

+262
-114
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,8 @@ class AMDGPURegBankLegalizeCombiner {
216216
return;
217217
}
218218

219-
if (DstTy == S32 && TruncSrcTy == S16) {
219+
if ((DstTy == S64 && TruncSrcTy == S32) ||
220+
(DstTy == S32 && TruncSrcTy == S16)) {
220221
B.buildAnyExt(Dst, TruncSrc);
221222
cleanUpAfterCombine(MI, Trunc);
222223
return;

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

+45-6
Original file line numberDiff line numberDiff line change
@@ -173,13 +173,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
173173
case Ext32To64: {
174174
const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg());
175175
MachineInstrBuilder Hi;
176-
177-
if (MI.getOpcode() == AMDGPU::G_ZEXT) {
176+
switch (MI.getOpcode()) {
177+
case AMDGPU::G_ZEXT: {
178178
Hi = B.buildConstant({RB, S32}, 0);
179-
} else {
179+
break;
180+
}
181+
case AMDGPU::G_SEXT: {
180182
// Replicate sign bit from 32-bit extended part.
181183
auto ShiftAmt = B.buildConstant({RB, S32}, 31);
182184
Hi = B.buildAShr({RB, S32}, MI.getOperand(1).getReg(), ShiftAmt);
185+
break;
186+
}
187+
case AMDGPU::G_ANYEXT: {
188+
Hi = B.buildUndef({RB, S32});
189+
break;
190+
}
191+
default:
192+
llvm_unreachable("Unsuported Opcode in Ext32To64");
183193
}
184194

185195
B.buildMergeLikeInstr(MI.getOperand(0).getReg(),
@@ -202,7 +212,7 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
202212
// compares all bits in register.
203213
Register BoolSrc = MRI.createVirtualRegister({VgprRB, Ty});
204214
if (Ty == S64) {
205-
auto Src64 = B.buildUnmerge({VgprRB, Ty}, Src);
215+
auto Src64 = B.buildUnmerge(VgprRB_S32, Src);
206216
auto One = B.buildConstant(VgprRB_S32, 1);
207217
auto AndLo = B.buildAnd(VgprRB_S32, Src64.getReg(0), One);
208218
auto Zero = B.buildConstant(VgprRB_S32, 0);
@@ -396,8 +406,11 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
396406
case Sgpr32AExt:
397407
case Sgpr32AExtBoolInReg:
398408
case Sgpr32SExt:
409+
case Sgpr32ZExt:
399410
case UniInVgprS32:
400411
case Vgpr32:
412+
case Vgpr32SExt:
413+
case Vgpr32ZExt:
401414
return LLT::scalar(32);
402415
case Sgpr64:
403416
case Vgpr64:
@@ -508,6 +521,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
508521
case Sgpr32AExt:
509522
case Sgpr32AExtBoolInReg:
510523
case Sgpr32SExt:
524+
case Sgpr32ZExt:
511525
return SgprRB;
512526
case Vgpr16:
513527
case Vgpr32:
@@ -524,6 +538,8 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
524538
case VgprB128:
525539
case VgprB256:
526540
case VgprB512:
541+
case Vgpr32SExt:
542+
case Vgpr32ZExt:
527543
return VgprRB;
528544
default:
529545
return nullptr;
@@ -729,8 +745,8 @@ void RegBankLegalizeHelper::applyMappingSrc(
729745
assert(Ty.getSizeInBits() == 1);
730746
assert(RB == SgprRB);
731747
auto Aext = B.buildAnyExt(SgprRB_S32, Reg);
732-
// Zext SgprS1 is not legal, this instruction is most of times meant to be
733-
// combined away in RB combiner, so do not make AND with 1.
748+
// Zext SgprS1 is not legal, make AND with 1 instead. This instruction is
749+
// most of times meant to be combined away in AMDGPURegBankCombiner.
734750
auto Cst1 = B.buildConstant(SgprRB_S32, 1);
735751
auto BoolInReg = B.buildAnd(SgprRB_S32, Aext, Cst1);
736752
Op.setReg(BoolInReg.getReg(0));
@@ -743,6 +759,29 @@ void RegBankLegalizeHelper::applyMappingSrc(
743759
Op.setReg(Sext.getReg(0));
744760
break;
745761
}
762+
case Sgpr32ZExt: {
763+
assert(1 < Ty.getSizeInBits() && Ty.getSizeInBits() < 32);
764+
assert(RB == SgprRB);
765+
auto Zext = B.buildZExt({SgprRB, S32}, Reg);
766+
Op.setReg(Zext.getReg(0));
767+
break;
768+
}
769+
case Vgpr32SExt: {
770+
// Note this ext allows S1, and it is meant to be combined away.
771+
assert(Ty.getSizeInBits() < 32);
772+
assert(RB == VgprRB);
773+
auto Sext = B.buildSExt({VgprRB, S32}, Reg);
774+
Op.setReg(Sext.getReg(0));
775+
break;
776+
}
777+
case Vgpr32ZExt: {
778+
// Note this ext allows S1, and it is meant to be combined away.
779+
assert(Ty.getSizeInBits() < 32);
780+
assert(RB == VgprRB);
781+
auto Zext = B.buildZExt({VgprRB, S32}, Reg);
782+
Op.setReg(Zext.getReg(0));
783+
break;
784+
}
746785
default:
747786
llvm_unreachable("ID not supported");
748787
}

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

+43-4
Original file line numberDiff line numberDiff line change
@@ -489,22 +489,61 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
489489
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
490490

491491
addRulesForGOpcs({G_ANYEXT})
492+
.Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away
492493
.Any({{UniS32, S1}, {{None}, {None}}}) // should be combined away
493-
.Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}});
494+
.Any({{UniS64, S1}, {{None}, {None}}}) // should be combined away
495+
.Any({{{DivS16, S1}}, {{Vgpr16}, {Vcc}, VccExtToSel}})
496+
.Any({{{DivS32, S1}}, {{Vgpr32}, {Vcc}, VccExtToSel}})
497+
.Any({{{DivS64, S1}}, {{Vgpr64}, {Vcc}, VccExtToSel}})
498+
.Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
499+
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}, Ext32To64}})
500+
.Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}})
501+
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}});
494502

495503
// In global-isel G_TRUNC in-reg is treated as no-op, inst selected into COPY.
496504
// It is up to user to deal with truncated bits.
497505
addRulesForGOpcs({G_TRUNC})
506+
.Any({{UniS1, UniS16}, {{None}, {None}}}) // should be combined away
498507
.Any({{UniS1, UniS32}, {{None}, {None}}}) // should be combined away
508+
.Any({{UniS1, UniS64}, {{None}, {None}}}) // should be combined away
499509
.Any({{UniS16, S32}, {{Sgpr16}, {Sgpr32}}})
510+
.Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
511+
.Any({{UniS32, S64}, {{Sgpr32}, {Sgpr64}}})
512+
.Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}})
500513
// This is non-trivial. VgprToVccCopy is done using compare instruction.
501-
.Any({{DivS1, DivS32}, {{Vcc}, {Vgpr32}, VgprToVccCopy}});
514+
.Any({{DivS1, DivS16}, {{Vcc}, {Vgpr16}, VgprToVccCopy}})
515+
.Any({{DivS1, DivS32}, {{Vcc}, {Vgpr32}, VgprToVccCopy}})
516+
.Any({{DivS1, DivS64}, {{Vcc}, {Vgpr64}, VgprToVccCopy}});
502517

503-
addRulesForGOpcs({G_ZEXT, G_SEXT})
518+
addRulesForGOpcs({G_ZEXT})
519+
.Any({{UniS16, S1}, {{Sgpr32Trunc}, {Sgpr32AExtBoolInReg}, UniExtToSel}})
520+
.Any({{UniS32, S1}, {{Sgpr32}, {Sgpr32AExtBoolInReg}, UniExtToSel}})
521+
.Any({{UniS64, S1}, {{Sgpr64}, {Sgpr32AExtBoolInReg}, UniExtToSel}})
522+
.Any({{DivS16, S1}, {{Vgpr16}, {Vcc}, VccExtToSel}})
523+
.Any({{DivS32, S1}, {{Vgpr32}, {Vcc}, VccExtToSel}})
524+
.Any({{DivS64, S1}, {{Vgpr64}, {Vcc}, VccExtToSel}})
525+
.Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
526+
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}, Ext32To64}})
527+
// not extending S16 to S32 is questionable.
528+
.Any({{UniS64, S16}, {{Sgpr64}, {Sgpr32ZExt}, Ext32To64}})
529+
.Any({{DivS64, S16}, {{Vgpr64}, {Vgpr32ZExt}, Ext32To64}})
530+
.Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}})
531+
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}});
532+
533+
addRulesForGOpcs({G_SEXT})
534+
.Any({{UniS16, S1}, {{Sgpr32Trunc}, {Sgpr32AExtBoolInReg}, UniExtToSel}})
504535
.Any({{UniS32, S1}, {{Sgpr32}, {Sgpr32AExtBoolInReg}, UniExtToSel}})
536+
.Any({{UniS64, S1}, {{Sgpr64}, {Sgpr32AExtBoolInReg}, UniExtToSel}})
537+
.Any({{DivS16, S1}, {{Vgpr16}, {Vcc}, VccExtToSel}})
505538
.Any({{DivS32, S1}, {{Vgpr32}, {Vcc}, VccExtToSel}})
539+
.Any({{DivS64, S1}, {{Vgpr64}, {Vcc}, VccExtToSel}})
506540
.Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
507-
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}, Ext32To64}});
541+
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}, Ext32To64}})
542+
// not extending S16 to S32 is questionable.
543+
.Any({{UniS64, S16}, {{Sgpr64}, {Sgpr32SExt}, Ext32To64}})
544+
.Any({{DivS64, S16}, {{Vgpr64}, {Vgpr32SExt}, Ext32To64}})
545+
.Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}})
546+
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}});
508547

509548
bool hasUnalignedLoads = ST->getGeneration() >= AMDGPUSubtarget::GFX12;
510549
bool hasSMRDSmall = ST->hasScalarSubwordLoads();

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h

+3
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,9 @@ enum RegBankLLTMappingApplyID {
159159
Sgpr32AExt,
160160
Sgpr32AExtBoolInReg,
161161
Sgpr32SExt,
162+
Sgpr32ZExt,
163+
Vgpr32SExt,
164+
Vgpr32ZExt,
162165
};
163166

164167
// Instruction needs to be replaced with sequence of instructions. Lowering was

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir

+30-31
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3-
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
2+
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
43

54
---
65
name: anyext_s32_to_s64_s
@@ -13,7 +12,8 @@ body: |
1312
; CHECK: liveins: $sgpr0
1413
; CHECK-NEXT: {{ $}}
1514
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
16-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[COPY]](s32)
15+
; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
16+
; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
1717
%0:_(s32) = COPY $sgpr0
1818
%1:_(s64) = G_ANYEXT %0
1919
...
@@ -29,9 +29,8 @@ body: |
2929
; CHECK: liveins: $vgpr0
3030
; CHECK-NEXT: {{ $}}
3131
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
32-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
3332
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
34-
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[DEF]](s32)
33+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
3534
%0:_(s32) = COPY $vgpr0
3635
%1:_(s64) = G_ANYEXT %0
3736
...
@@ -49,8 +48,7 @@ body: |
4948
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
5049
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
5150
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
52-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
53-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
51+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[ICMP]](s32)
5452
%0:_(s32) = COPY $sgpr0
5553
%1:_(s32) = COPY $sgpr1
5654
%2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -70,8 +68,6 @@ body: |
7068
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
7169
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
7270
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
73-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
74-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
7571
%0:_(s32) = COPY $sgpr0
7672
%1:_(s32) = COPY $sgpr1
7773
%2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -91,8 +87,7 @@ body: |
9187
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
9288
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
9389
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
94-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
95-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
90+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[ICMP]](s32)
9691
%0:_(s32) = COPY $sgpr0
9792
%1:_(s32) = COPY $sgpr1
9893
%2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -112,10 +107,9 @@ body: |
112107
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
113108
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
114109
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
115-
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
116-
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
117-
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
118-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[SELECT]](s32)
110+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s16) = G_CONSTANT i16 1
111+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s16) = G_CONSTANT i16 0
112+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s16) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
119113
%0:_(s32) = COPY $vgpr0
120114
%1:_(s32) = COPY $vgpr1
121115
%2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -160,8 +154,7 @@ body: |
160154
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
161155
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
162156
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
163-
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
164-
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[DEF]](s32)
157+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[C1]](s32)
165158
%0:_(s32) = COPY $vgpr0
166159
%1:_(s32) = COPY $vgpr1
167160
%2:_(s1) = G_ICMP intpred(eq), %0, %1
@@ -179,8 +172,7 @@ body: |
179172
; CHECK: liveins: $sgpr0
180173
; CHECK-NEXT: {{ $}}
181174
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
182-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
183-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
175+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
184176
%0:_(s32) = COPY $sgpr0
185177
%1:_(s1) = G_TRUNC %0
186178
%2:_(s16) = G_ANYEXT %1
@@ -197,8 +189,6 @@ body: |
197189
; CHECK: liveins: $sgpr0
198190
; CHECK-NEXT: {{ $}}
199191
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
200-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
201-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
202192
%0:_(s32) = COPY $sgpr0
203193
%1:_(s1) = G_TRUNC %0
204194
%2:_(s32) = G_ANYEXT %1
@@ -215,8 +205,7 @@ body: |
215205
; CHECK: liveins: $sgpr0
216206
; CHECK-NEXT: {{ $}}
217207
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
218-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
219-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
208+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[COPY]](s32)
220209
%0:_(s32) = COPY $sgpr0
221210
%1:_(s1) = G_TRUNC %0
222211
%2:_(s64) = G_ANYEXT %1
@@ -233,8 +222,13 @@ body: |
233222
; CHECK: liveins: $vgpr0
234223
; CHECK-NEXT: {{ $}}
235224
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
236-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
237-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)
225+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
226+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
227+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
228+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
229+
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s16) = G_CONSTANT i16 1
230+
; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s16) = G_CONSTANT i16 0
231+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
238232
%0:_(s32) = COPY $vgpr0
239233
%1:_(s1) = G_TRUNC %0
240234
%2:_(s16) = G_ANYEXT %1
@@ -251,8 +245,11 @@ body: |
251245
; CHECK: liveins: $vgpr0
252246
; CHECK-NEXT: {{ $}}
253247
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
254-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
255-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
248+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
249+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
250+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
251+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
252+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
256253
%0:_(s32) = COPY $vgpr0
257254
%1:_(s1) = G_TRUNC %0
258255
%2:_(s32) = G_ANYEXT %1
@@ -269,10 +266,12 @@ body: |
269266
; CHECK: liveins: $vgpr0
270267
; CHECK-NEXT: {{ $}}
271268
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
272-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
273-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
274-
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr(s32) = G_IMPLICIT_DEF
275-
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[ANYEXT]](s32), [[DEF]](s32)
269+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
270+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
271+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
272+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
273+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
274+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[C1]](s32)
276275
%0:_(s32) = COPY $vgpr0
277276
%1:_(s1) = G_TRUNC %0
278277
%2:_(s64) = G_ANYEXT %1

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