Add <2 x i32> test. Add DL as optional to isValidAtomicTy

Author: jofrn

llvm/include/llvm/IR/Instructions.h

@@ -252,7 +252,8 @@ class LoadInst : public UnaryInstruction {
 
   /// Returns false if this type would be invalid in the
   /// creation of a load atomic instruction.
-  static bool isValidAtomicTy(Type *Ty);
+  static bool isValidAtomicTy(Type *Ty, const DataLayout *DL = nullptr,
+                              AtomicOrdering AO = AtomicOrdering::NotAtomic);
 
   Value *getPointerOperand() { return getOperand(0); }
   const Value *getPointerOperand() const { return getOperand(0); }

llvm/lib/IR/Instructions.cpp

@@ -1247,9 +1247,17 @@ void LoadInst::AssertOK() {
          "Ptr must have pointer type.");
 }
 
-bool LoadInst::isValidAtomicTy(Type *Ty) {
+bool LoadInst::isValidAtomicTy(Type *Ty, const DataLayout *DL,
+                               AtomicOrdering AO) {
+  // TODO: Share methods with IR/Verifier.
   if (!Ty->isIntOrPtrTy() && !Ty->isFloatingPointTy())
     return false;
+  if (AO == AtomicOrdering::Release || AO == AtomicOrdering::AcquireRelease)
+    return false;
+  if (DL) {
+    unsigned Size = DL->getTypeSizeInBits(Ty);
+    return Size >= 8 && !(Size & (Size - 1));
+  }
   return true;
 }
 

llvm/lib/Transforms/Scalar/SROA.cpp

@@ -2854,7 +2854,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
   bool visitLoadInst(LoadInst &LI) {
     LLVM_DEBUG(dbgs() << "    original: " << LI << "\n");
 
-    // load atomic vector would be generated, which is illegal
+    // Load atomic vector would be generated, which is illegal.
+    // TODO: Generate a generic bitcast in machine codegen instead.
     if (LI.isAtomic() && !LoadInst::isValidAtomicTy(NewAI.getAllocatedType()))
       return false;
 

llvm/test/Transforms/SROA/atomic-vector.ll

@@ -51,3 +51,20 @@ define ptr @atomic_vector_ptr() {
   %ret = load atomic volatile ptr, ptr %indirect acquire, align 4
   ret ptr %ret
 }
+
+define i32 @atomic_2vector_int() {
+; CHECK-LABEL: define i32 @atomic_2vector_int() {
+; CHECK-NEXT:    [[VAL_SROA_0:%.*]] = alloca i32, align 8
+; CHECK-NEXT:    store i32 undef, ptr [[VAL_SROA_0]], align 8
+; CHECK-NEXT:    [[VAL_SROA_0_0_VAL_SROA_0_0_RET:%.*]] = load atomic volatile i32, ptr [[VAL_SROA_0]] acquire, align 4
+; CHECK-NEXT:    ret i32 [[VAL_SROA_0_0_VAL_SROA_0_0_RET]]
+;
+  %src = alloca <2 x i32>
+  %val = alloca <2 x i32>
+  %direct = alloca ptr
+  call void @llvm.memcpy.p0.p0.i64(ptr %val, ptr %src, i64 4, i1 false)
+  store ptr %val, ptr %direct
+  %indirect = load ptr, ptr %direct
+  %ret = load atomic volatile i32, ptr %indirect acquire, align 4
+  ret i32 %ret
+}