update ballot test, update nor test

Author: mihajlovicana

llvm/test/CodeGen/AMDGPU/isel-nor-32.ll

@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="+wavefrontsize32,-wavefrontsize64" -o - < %s | FileCheck -check-prefixes=SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="+wavefrontsize32,-wavefrontsize64" -o - < %s | FileCheck -check-prefixes=GISEL %s
+
+; Use ballot for easy access to lanemask
+
+define amdgpu_ps i32 @test_nor(i32 inreg %a, i32 inreg %b) {
+; SDAG-LABEL: test_nor:
+; SDAG:       ; %bb.0:
+; SDAG-NEXT:    s_nor_b32 s0, s0, s1
+; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; SDAG-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
+; SDAG-NEXT:    ; return to shader part epilog
+;
+; GISEL-LABEL: test_nor:
+; GISEL:       ; %bb.0:
+; GISEL-NEXT:    s_nor_b32 s0, s0, s1
+; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT:    s_and_b32 s0, s0, exec_lo
+; GISEL-NEXT:    ; return to shader part epilog
+  %a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i32(i32 %a)
+  %b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i32(i32 %b)
+  %or = or i1 %a.lanemask, %b.lanemask
+  %xor = xor i1 %or, true
+  %r = call i32 @llvm.amdgcn.ballot.i32(i1 %xor)
+  ret i32 %r
+}
+
+define amdgpu_ps i32 @test_or_two_uses(i32 inreg %a, i32 inreg %b) {
+; SDAG-LABEL: test_or_two_uses:
+; SDAG:       ; %bb.0:
+; SDAG-NEXT:    s_or_b32 s0, s0, s1
+; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; SDAG-NEXT:    s_xor_b32 s0, s0, -1
+; SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s0
+; SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-NEXT:    v_cmp_ne_u32_e64 s0, 0, v0
+; SDAG-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; SDAG-NEXT:    s_and_b32 s0, vcc_lo, s0
+; SDAG-NEXT:    ; return to shader part epilog
+;
+; GISEL-LABEL: test_or_two_uses:
+; GISEL:       ; %bb.0:
+; GISEL-NEXT:    s_or_b32 s0, s0, s1
+; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GISEL-NEXT:    s_xor_b32 s1, s0, -1
+; GISEL-NEXT:    s_and_b32 s0, s0, exec_lo
+; GISEL-NEXT:    s_and_b32 s1, s1, exec_lo
+; GISEL-NEXT:    s_and_b32 s0, s1, s0
+; GISEL-NEXT:    ; return to shader part epilog
+  %a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i32(i32 %a)
+  %b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i32(i32 %b)
+  %or = or i1 %a.lanemask, %b.lanemask
+  %xor = xor i1 %or, true
+  %r0 = call i32 @llvm.amdgcn.ballot.i32(i1 %xor)
+  %r1 = call i32 @llvm.amdgcn.ballot.i32(i1 %or)
+  %r = and i32 %r0, %r1
+  ret i32 %r
+}

llvm/test/CodeGen/AMDGPU/isel-nor-64.ll

@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="-wavefrontsize32,+wavefrontsize64" -o - < %s | FileCheck -check-prefixes=SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="-wavefrontsize32,+wavefrontsize64" -o - < %s | FileCheck -check-prefixes=GISEL %s
+
+; Use ballot for easy access to lanemask
+
+define amdgpu_ps i64 @test_nor(i64 inreg %a, i64 inreg %b) {
+; SDAG-LABEL: test_nor:
+; SDAG:       ; %bb.0:
+; SDAG-NEXT:    s_nor_b64 s[0:1], s[0:1], s[2:3]
+; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; SDAG-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v0
+; SDAG-NEXT:    ; return to shader part epilog
+;
+; GISEL-LABEL: test_nor:
+; GISEL:       ; %bb.0:
+; GISEL-NEXT:    s_nor_b64 s[0:1], s[0:1], s[2:3]
+; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT:    s_and_b64 s[0:1], s[0:1], exec
+; GISEL-NEXT:    ; return to shader part epilog
+  %a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %a)
+  %b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %b)
+  %or = or i1 %a.lanemask, %b.lanemask
+  %xor = xor i1 %or, true
+  %r = call i64 @llvm.amdgcn.ballot.i64(i1 %xor)
+  ret i64 %r
+}
+
+define amdgpu_ps i64 @test_or_two_uses(i64 inreg %a, i64 inreg %b) {
+; SDAG-LABEL: test_or_two_uses:
+; SDAG:       ; %bb.0:
+; SDAG-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
+; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; SDAG-NEXT:    s_xor_b64 s[0:1], s[0:1], -1
+; SDAG-NEXT:    s_waitcnt_depctr 0xfffe
+; SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[0:1]
+; SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v1
+; SDAG-NEXT:    s_and_b64 s[0:1], s[0:1], vcc
+; SDAG-NEXT:    s_waitcnt_depctr 0xfffe
+; SDAG-NEXT:    ; return to shader part epilog
+;
+; GISEL-LABEL: test_or_two_uses:
+; GISEL:       ; %bb.0:
+; GISEL-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
+; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GISEL-NEXT:    s_xor_b64 s[2:3], s[0:1], -1
+; GISEL-NEXT:    s_and_b64 s[0:1], s[0:1], exec
+; GISEL-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; GISEL-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
+; GISEL-NEXT:    ; return to shader part epilog
+  %a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %a)
+  %b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %b)
+  %or = or i1 %a.lanemask, %b.lanemask
+  %xor = xor i1 %or, true
+  %r0 = call i64 @llvm.amdgcn.ballot.i64(i1 %xor)
+  %r1 = call i64 @llvm.amdgcn.ballot.i64(i1 %or)
+  %r = and i64 %r0, %r1
+  ret i64 %r
+}