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[AMDGPU] Update EXECZ retention in SIPreEmitPeephole for GFX10/12 (#97676)
The check to maintain EXECZ branches only checks S_WAITCNT. Add handling for new waitcnt instructions in GFX10 and GFX12.
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -967,6 +967,29 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
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}
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}
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bool isWaitcnt(unsigned Opcode) const {
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switch (getNonSoftWaitcntOpcode(Opcode)) {
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case AMDGPU::S_WAITCNT:
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case AMDGPU::S_WAITCNT_VSCNT:
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case AMDGPU::S_WAITCNT_VMCNT:
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case AMDGPU::S_WAITCNT_EXPCNT:
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case AMDGPU::S_WAITCNT_LGKMCNT:
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case AMDGPU::S_WAIT_LOADCNT:
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case AMDGPU::S_WAIT_LOADCNT_DSCNT:
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case AMDGPU::S_WAIT_STORECNT:
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case AMDGPU::S_WAIT_STORECNT_DSCNT:
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case AMDGPU::S_WAIT_SAMPLECNT:
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case AMDGPU::S_WAIT_BVHCNT:
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case AMDGPU::S_WAIT_EXPCNT:
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case AMDGPU::S_WAIT_DSCNT:
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case AMDGPU::S_WAIT_KMCNT:
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case AMDGPU::S_WAIT_IDLE:
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return true;
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default:
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return false;
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}
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}
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bool isVGPRCopy(const MachineInstr &MI) const {
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assert(isCopyInstr(MI));
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Register Dest = MI.getOperand(0).getReg();

‎llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -328,7 +328,7 @@ bool SIPreEmitPeephole::mustRetainExeczBranch(
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// These instructions are potentially expensive even if EXEC = 0.
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if (TII->isSMRD(MI) || TII->isVMEM(MI) || TII->isFLAT(MI) ||
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TII->isDS(MI) || MI.getOpcode() == AMDGPU::S_WAITCNT)
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TII->isDS(MI) || TII->isWaitcnt(MI.getOpcode()))
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return true;
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++NumInstr;

‎llvm/test/CodeGen/AMDGPU/insert-skips-gfx10.mir

Lines changed: 186 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,186 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass si-pre-emit-peephole -amdgpu-skip-threshold=10 -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: skip_waitcnt_vscnt
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body: |
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; CHECK-LABEL: name: skip_waitcnt_vscnt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: V_NOP_e32 implicit $exec
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; CHECK-NEXT: S_WAITCNT_VSCNT $sgpr_null, 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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V_NOP_e32 implicit $exec
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S_WAITCNT_VSCNT $sgpr_null, 0
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bb.2:
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S_ENDPGM 0
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...
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---
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name: skip_waitcnt_expcnt
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body: |
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; CHECK-LABEL: name: skip_waitcnt_expcnt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: V_NOP_e32 implicit $exec
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; CHECK-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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V_NOP_e32 implicit $exec
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S_WAITCNT_EXPCNT $sgpr_null, 0
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bb.2:
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S_ENDPGM 0
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...
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---
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name: skip_waitcnt_vmcnt
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body: |
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; CHECK-LABEL: name: skip_waitcnt_vmcnt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: V_NOP_e32 implicit $exec
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; CHECK-NEXT: S_WAITCNT_VMCNT $sgpr_null, 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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V_NOP_e32 implicit $exec
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S_WAITCNT_VMCNT $sgpr_null, 0
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bb.2:
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S_ENDPGM 0
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...
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---
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name: skip_waitcnt_lgkmcnt
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body: |
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; CHECK-LABEL: name: skip_waitcnt_lgkmcnt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: V_NOP_e32 implicit $exec
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; CHECK-NEXT: S_WAITCNT_LGKMCNT $sgpr_null, 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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V_NOP_e32 implicit $exec
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S_WAITCNT_LGKMCNT $sgpr_null, 0
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bb.2:
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S_ENDPGM 0
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...
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---
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name: skip_wait_idle
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body: |
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; CHECK-LABEL: name: skip_wait_idle
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: V_NOP_e32 implicit $exec
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; CHECK-NEXT: S_WAIT_IDLE
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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V_NOP_e32 implicit $exec
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S_WAIT_IDLE
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bb.2:
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S_ENDPGM 0
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...
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---
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name: skip_bvh
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body: |
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; CHECK-LABEL: name: skip_bvh
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: V_NOP_e32 implicit $exec
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; CHECK-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14 = IMPLICIT_DEF
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; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx11 $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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V_NOP_e32 implicit $exec
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$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14 = IMPLICIT_DEF
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$sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
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$vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx11 $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
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bb.2:
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S_ENDPGM 0
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...

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