Skip to content

Commit a5afaec

Browse files
jofrnjofrn
committed
[SelectionDAG][X86] Widen <2 x T> vector types for atomic load
Vector types of 2 elements must be widened. This change does this for vector types of atomic load in SelectionDAG so that it can translate aligned vectors of >1 size. Also, it also adds Pats to remove an extra MOV. commit-id:2894ccd1
1 parent 86d8d1c commit a5afaec

File tree

5 files changed

+178
-2
lines changed

5 files changed

+178
-2
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

+1
Original file line numberDiff line numberDiff line change
@@ -1048,6 +1048,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
10481048
SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N);
10491049
SDValue WidenVecRes_INSERT_SUBVECTOR(SDNode *N);
10501050
SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
1051+
SDValue WidenVecRes_ATOMIC_LOAD(AtomicSDNode *N);
10511052
SDValue WidenVecRes_LOAD(SDNode* N);
10521053
SDValue WidenVecRes_VP_LOAD(VPLoadSDNode *N);
10531054
SDValue WidenVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+88
Original file line numberDiff line numberDiff line change
@@ -4521,6 +4521,9 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
45214521
break;
45224522
case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
45234523
case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
4524+
case ISD::ATOMIC_LOAD:
4525+
Res = WidenVecRes_ATOMIC_LOAD(cast<AtomicSDNode>(N));
4526+
break;
45244527
case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
45254528
case ISD::STEP_VECTOR:
45264529
case ISD::SPLAT_VECTOR:
@@ -5907,6 +5910,91 @@ SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
59075910
N->getOperand(1), N->getOperand(2));
59085911
}
59095912

5913+
static std::optional<EVT> findMemType(SelectionDAG &DAG,
5914+
const TargetLowering &TLI, unsigned Width,
5915+
EVT WidenVT, unsigned Align,
5916+
unsigned WidenEx);
5917+
5918+
SDValue DAGTypeLegalizer::WidenVecRes_ATOMIC_LOAD(AtomicSDNode *LD) {
5919+
SmallVector<SDValue, 16> LdChain; // Chain for the series of load
5920+
5921+
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
5922+
EVT LdVT = LD->getMemoryVT();
5923+
SDLoc dl(LD);
5924+
assert(LdVT.isVector() && WidenVT.isVector());
5925+
assert(LdVT.isScalableVector() == WidenVT.isScalableVector());
5926+
assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
5927+
5928+
// Load information
5929+
SDValue Chain = LD->getChain();
5930+
SDValue BasePtr = LD->getBasePtr();
5931+
MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
5932+
AAMDNodes AAInfo = LD->getAAInfo();
5933+
5934+
TypeSize LdWidth = LdVT.getSizeInBits();
5935+
TypeSize WidenWidth = WidenVT.getSizeInBits();
5936+
TypeSize WidthDiff = WidenWidth - LdWidth;
5937+
// Allow wider loads if they are sufficiently aligned to avoid memory faults
5938+
// and if the original load is simple.
5939+
unsigned LdAlign =
5940+
(!LD->isSimple() || LdVT.isScalableVector()) ? 0 : LD->getAlign().value();
5941+
5942+
// Find the vector type that can load from.
5943+
std::optional<EVT> FirstVT =
5944+
findMemType(DAG, TLI, LdWidth.getKnownMinValue(), WidenVT, LdAlign,
5945+
WidthDiff.getKnownMinValue());
5946+
5947+
if (!FirstVT)
5948+
return SDValue();
5949+
5950+
SmallVector<EVT, 8> MemVTs;
5951+
TypeSize FirstVTWidth = FirstVT->getSizeInBits();
5952+
5953+
SDValue LdOp = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, *FirstVT, *FirstVT, Chain,
5954+
BasePtr, LD->getMemOperand());
5955+
LdChain.push_back(LdOp.getValue(1));
5956+
5957+
// Load the element with one instruction.
5958+
SDValue Result;
5959+
assert(TypeSize::isKnownLE(LdWidth, FirstVTWidth));
5960+
if (!FirstVT->isVector()) {
5961+
unsigned NumElts =
5962+
WidenWidth.getFixedValue() / FirstVTWidth.getFixedValue();
5963+
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), *FirstVT, NumElts);
5964+
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
5965+
Result = DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
5966+
}
5967+
else if (FirstVT == WidenVT)
5968+
Result = LdOp;
5969+
else {
5970+
// TODO: We don't currently have any tests that exercise this code path.
5971+
assert(WidenWidth.getFixedValue() % FirstVTWidth.getFixedValue() == 0);
5972+
unsigned NumConcat =
5973+
WidenWidth.getFixedValue() / FirstVTWidth.getFixedValue();
5974+
SmallVector<SDValue, 16> ConcatOps(NumConcat);
5975+
SDValue UndefVal = DAG.getUNDEF(*FirstVT);
5976+
ConcatOps[0] = LdOp;
5977+
for (unsigned i = 1; i != NumConcat; ++i)
5978+
ConcatOps[i] = UndefVal;
5979+
Result = DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
5980+
}
5981+
5982+
if (Result) {
5983+
// Build a factor node to remember the multiple loads are independent and
5984+
// chain to that.
5985+
SDValue NewChain =
5986+
DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
5987+
5988+
// Modified the chain - switch anything that used the old chain to use
5989+
// the new one.
5990+
ReplaceValueWith(SDValue(LD, 1), NewChain);
5991+
5992+
return Result;
5993+
}
5994+
5995+
report_fatal_error("Unable to widen atomic vector load");
5996+
}
5997+
59105998
SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
59115999
LoadSDNode *LD = cast<LoadSDNode>(N);
59126000
ISD::LoadExtType ExtType = LD->getExtensionType();

‎llvm/lib/Target/X86/X86InstrCompiler.td

+7
Original file line numberDiff line numberDiff line change
@@ -1198,6 +1198,13 @@ def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>;
11981198
def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>;
11991199
def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>;
12001200

1201+
def : Pat<(v4i32 (scalar_to_vector (i32 (anyext (i16 (atomic_load_16 addr:$src)))))),
1202+
(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i8>
1203+
def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32 addr:$src)))),
1204+
(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i16>
1205+
def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src)))),
1206+
(MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float>
1207+
12011208
// Floating point loads/stores.
12021209
def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),
12031210
(MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>;

‎llvm/test/CodeGen/X86/atomic-load-store.ll

+81
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,64 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {
146146
ret <1 x i64> %ret
147147
}
148148

149+
define <2 x i8> @atomic_vec2_i8(ptr %x) {
150+
; CHECK3-LABEL: atomic_vec2_i8:
151+
; CHECK3: ## %bb.0:
152+
; CHECK3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
153+
; CHECK3-NEXT: retq
154+
;
155+
; CHECK0-LABEL: atomic_vec2_i8:
156+
; CHECK0: ## %bb.0:
157+
; CHECK0-NEXT: movw (%rdi), %cx
158+
; CHECK0-NEXT: ## implicit-def: $eax
159+
; CHECK0-NEXT: movw %cx, %ax
160+
; CHECK0-NEXT: movd %eax, %xmm0
161+
; CHECK0-NEXT: retq
162+
%ret = load atomic <2 x i8>, ptr %x acquire, align 4
163+
ret <2 x i8> %ret
164+
}
165+
166+
define <2 x i16> @atomic_vec2_i16(ptr %x) {
167+
; CHECK3-LABEL: atomic_vec2_i16:
168+
; CHECK3: ## %bb.0:
169+
; CHECK3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
170+
; CHECK3-NEXT: retq
171+
;
172+
; CHECK0-LABEL: atomic_vec2_i16:
173+
; CHECK0: ## %bb.0:
174+
; CHECK0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
175+
; CHECK0-NEXT: retq
176+
%ret = load atomic <2 x i16>, ptr %x acquire, align 4
177+
ret <2 x i16> %ret
178+
}
179+
180+
define <2 x ptr addrspace(270)> @atomic_vec2_ptr270(ptr %x) {
181+
; CHECK-LABEL: atomic_vec2_ptr270:
182+
; CHECK: ## %bb.0:
183+
; CHECK-NEXT: movq (%rdi), %xmm0
184+
; CHECK-NEXT: retq
185+
%ret = load atomic <2 x ptr addrspace(270)>, ptr %x acquire, align 8
186+
ret <2 x ptr addrspace(270)> %ret
187+
}
188+
189+
define <2 x i32> @atomic_vec2_i32_align(ptr %x) {
190+
; CHECK-LABEL: atomic_vec2_i32_align:
191+
; CHECK: ## %bb.0:
192+
; CHECK-NEXT: movq (%rdi), %xmm0
193+
; CHECK-NEXT: retq
194+
%ret = load atomic <2 x i32>, ptr %x acquire, align 8
195+
ret <2 x i32> %ret
196+
}
197+
198+
define <2 x float> @atomic_vec2_float_align(ptr %x) {
199+
; CHECK-LABEL: atomic_vec2_float_align:
200+
; CHECK: ## %bb.0:
201+
; CHECK-NEXT: movq (%rdi), %xmm0
202+
; CHECK-NEXT: retq
203+
%ret = load atomic <2 x float>, ptr %x acquire, align 8
204+
ret <2 x float> %ret
205+
}
206+
149207
define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {
150208
; CHECK3-LABEL: atomic_vec1_ptr:
151209
; CHECK3: ## %bb.0:
@@ -295,6 +353,29 @@ define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
295353
ret <2 x i32> %ret
296354
}
297355

356+
define <4 x i8> @atomic_vec4_i8(ptr %x) nounwind {
357+
; CHECK3-LABEL: atomic_vec4_i8:
358+
; CHECK3: ## %bb.0:
359+
; CHECK3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
360+
; CHECK3-NEXT: retq
361+
;
362+
; CHECK0-LABEL: atomic_vec4_i8:
363+
; CHECK0: ## %bb.0:
364+
; CHECK0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
365+
; CHECK0-NEXT: retq
366+
%ret = load atomic <4 x i8>, ptr %x acquire, align 4
367+
ret <4 x i8> %ret
368+
}
369+
370+
define <4 x i16> @atomic_vec4_i16(ptr %x) nounwind {
371+
; CHECK-LABEL: atomic_vec4_i16:
372+
; CHECK: ## %bb.0:
373+
; CHECK-NEXT: movq (%rdi), %xmm0
374+
; CHECK-NEXT: retq
375+
%ret = load atomic <4 x i16>, ptr %x acquire, align 8
376+
ret <4 x i16> %ret
377+
}
378+
298379
define <4 x float> @atomic_vec4_float_align(ptr %x) nounwind {
299380
; CHECK-LABEL: atomic_vec4_float_align:
300381
; CHECK: ## %bb.0:

‎llvm/test/CodeGen/X86/atomic-unordered.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -2275,8 +2275,7 @@ define i64 @load_i16_anyext_i64(ptr %ptr) {
22752275
;
22762276
; CHECK-O3-LABEL: load_i16_anyext_i64:
22772277
; CHECK-O3: # %bb.0:
2278-
; CHECK-O3-NEXT: movzwl (%rdi), %eax
2279-
; CHECK-O3-NEXT: vmovd %eax, %xmm0
2278+
; CHECK-O3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
22802279
; CHECK-O3-NEXT: vmovq %xmm0, %rax
22812280
; CHECK-O3-NEXT: retq
22822281
%v = load atomic i16, ptr %ptr unordered, align 8

0 commit comments

Comments
 (0)