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[CodeGen] Remove some implict conversions of MCRegister to unsigned by using(). NFC
Many of these are indexing BitVectors or something where we can't using MCRegister and need the register number.
1 parent 69d3ba3 commit b7eee2c

19 files changed

+41
-38
lines changed

Diff for: ‎llvm/include/llvm/CodeGen/CallingConvLower.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -254,7 +254,7 @@ class CCState {
254254
/// isAllocated - Return true if the specified register (or an alias) is
255255
/// allocated.
256256
bool isAllocated(MCRegister Reg) const {
257-
return UsedRegs[Reg / 32] & (1 << (Reg & 31));
257+
return UsedRegs[Reg.id() / 32] & (1 << (Reg.id() & 31));
258258
}
259259

260260
/// AnalyzeFormalArguments - Analyze an array of argument values,

Diff for: ‎llvm/include/llvm/CodeGen/LivePhysRegs.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ class LivePhysRegs {
9393
assert(TRI && "LivePhysRegs is not initialized.");
9494
assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
9595
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R)
96-
LiveRegs.erase(*R);
96+
LiveRegs.erase((*R).id());
9797
}
9898

9999
/// Removes physical registers clobbered by the regmask operand \p MO.

Diff for: ‎llvm/include/llvm/CodeGen/MachineOperand.h

+3-2
Original file line numberDiff line numberDiff line change
@@ -645,8 +645,9 @@ class MachineOperand {
645645
/// mask pointers.
646646
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
647647
// See TargetRegisterInfo.h.
648-
assert(PhysReg < (1u << 30) && "Not a physical register");
649-
return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
648+
assert((!PhysReg.isValid() || PhysReg.isPhysical()) &&
649+
"Not a physical register");
650+
return !(RegMask[PhysReg.id() / 32] & (1u << PhysReg.id() % 32));
650651
}
651652

652653
/// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.

Diff for: ‎llvm/include/llvm/CodeGen/MachineRegisterInfo.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -938,7 +938,7 @@ class MachineRegisterInfo {
938938
MCRegAliasIterator R(PhysReg, TRI, true);
939939

940940
for (; R.isValid(); ++R)
941-
ReservedRegs.set(*R);
941+
ReservedRegs.set((*R).id());
942942
}
943943

944944
/// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
@@ -951,7 +951,7 @@ class MachineRegisterInfo {
951951
/// register. Any register can be reserved before freezeReservedRegs() is
952952
/// called.
953953
bool canReserveReg(MCRegister PhysReg) const {
954-
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
954+
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg.id());
955955
}
956956

957957
/// getReservedRegs - Returns a reference to the frozen set of reserved

Diff for: ‎llvm/include/llvm/CodeGen/Register.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ class Register {
2121

2222
public:
2323
constexpr Register(unsigned Val = 0) : Reg(Val) {}
24-
constexpr Register(MCRegister Val) : Reg(Val) {}
24+
constexpr Register(MCRegister Val) : Reg(Val.id()) {}
2525

2626
// Register numbers can represent physical registers, virtual registers, and
2727
// sometimes stack slots. The unsigned values are divided into these ranges:

Diff for: ‎llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
420420
if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
421421
continue;
422422

423-
DefIndices[*AI] = Count;
423+
DefIndices[(*AI).id()] = Count;
424424
}
425425
}
426426
}

Diff for: ‎llvm/lib/CodeGen/CallingConvLower.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -61,12 +61,12 @@ void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
6161
/// Mark a register and all of its aliases as allocated.
6262
void CCState::MarkAllocated(MCPhysReg Reg) {
6363
for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
64-
UsedRegs[*AI / 32] |= 1 << (*AI & 31);
64+
UsedRegs[(*AI).id() / 32] |= 1 << ((*AI).id() & 31);
6565
}
6666

6767
void CCState::MarkUnallocated(MCPhysReg Reg) {
6868
for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
69-
UsedRegs[*AI / 32] &= ~(1 << (*AI & 31));
69+
UsedRegs[(*AI).id() / 32] &= ~(1 << ((*AI).id() & 31));
7070
}
7171

7272
bool CCState::IsShadowAllocatedReg(MCRegister Reg) const {

Diff for: ‎llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
6767
for (const MachineBasicBlock *Succ : BB->successors())
6868
for (const auto &LI : Succ->liveins()) {
6969
for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
70-
unsigned Reg = *AI;
70+
unsigned Reg = (*AI).id();
7171
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
7272
KillIndices[Reg] = BBSize;
7373
DefIndices[Reg] = ~0u;
@@ -85,7 +85,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
8585
if (!IsReturnBlock && !Pristine.test(Reg))
8686
continue;
8787
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
88-
unsigned Reg = *AI;
88+
unsigned Reg = (*AI).id();
8989
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
9090
KillIndices[Reg] = BBSize;
9191
DefIndices[Reg] = ~0u;
@@ -200,7 +200,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
200200
// If an alias of the reg is used during the live range, give up.
201201
// Note that this allows us to skip checking if AntiDepReg
202202
// overlaps with any of the aliases, among other things.
203-
unsigned AliasReg = *AI;
203+
unsigned AliasReg = (*AI).id();
204204
if (Classes[AliasReg]) {
205205
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
206206
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
@@ -327,7 +327,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
327327
// It wasn't previously live but now it is, this is a kill.
328328
// Repeat for all aliases.
329329
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
330-
unsigned AliasReg = *AI;
330+
unsigned AliasReg = (*AI).id();
331331
if (KillIndices[AliasReg] == ~0u) {
332332
KillIndices[AliasReg] = Count;
333333
DefIndices[AliasReg] = ~0u;

Diff for: ‎llvm/lib/CodeGen/ExecutionDomainFix.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -445,7 +445,7 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
445445
for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
446446
for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid();
447447
++AI)
448-
AliasMap[*AI].push_back(i);
448+
AliasMap[(*AI).id()].push_back(i);
449449
}
450450

451451
// Initialize the MBBOutRegsInfos

Diff for: ‎llvm/lib/CodeGen/InterferenceCache.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) {
7878
continue;
7979
}
8080
Entries[E].reset(PhysReg, LIUArray, TRI, MF);
81-
PhysRegEntries[PhysReg] = E;
81+
PhysRegEntries[PhysReg.id()] = E;
8282
return &Entries[E];
8383
}
8484
llvm_unreachable("Ran out of interference cache entries.");

Diff for: ‎llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ class TransferTracker {
283283
if (Reg >= MTracker->NumRegs)
284284
return false;
285285
for (MCRegAliasIterator RAI(Reg, &TRI, true); RAI.isValid(); ++RAI)
286-
if (CalleeSavedRegs.test(*RAI))
286+
if (CalleeSavedRegs.test((*RAI).id()))
287287
return true;
288288
return false;
289289
};
@@ -1345,7 +1345,7 @@ bool InstrRefBasedLDV::isCalleeSaved(LocIdx L) const {
13451345
}
13461346
bool InstrRefBasedLDV::isCalleeSavedReg(Register R) const {
13471347
for (MCRegAliasIterator RAI(R, TRI, true); RAI.isValid(); ++RAI)
1348-
if (CalleeSavedRegs.test(*RAI))
1348+
if (CalleeSavedRegs.test((*RAI).id()))
13491349
return true;
13501350
return false;
13511351
}
@@ -1880,7 +1880,7 @@ void InstrRefBasedLDV::transferRegisterDef(MachineInstr &MI) {
18801880
// Remove ranges of all aliased registers.
18811881
for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
18821882
// FIXME: Can we break out of this loop early if no insertion occurs?
1883-
DeadRegs.insert(*RAI);
1883+
DeadRegs.insert((*RAI).id());
18841884
} else if (MO.isRegMask()) {
18851885
RegMasks.push_back(MO.getRegMask());
18861886
RegMaskPtrs.push_back(&MO);

Diff for: ‎llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1606,7 +1606,7 @@ void VarLocBasedLDV::transferRegisterDef(MachineInstr &MI,
16061606
// Remove ranges of all aliased registers.
16071607
for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
16081608
// FIXME: Can we break out of this loop early if no insertion occurs?
1609-
DeadRegs.insert(*RAI);
1609+
DeadRegs.insert((*RAI).id());
16101610
RegSetInstrs.erase(MO.getReg());
16111611
RegSetInstrs.insert({MO.getReg(), &MI});
16121612
} else if (MO.isRegMask()) {
@@ -1866,7 +1866,7 @@ void VarLocBasedLDV::transferRegisterCopy(MachineInstr &MI,
18661866

18671867
auto isCalleeSavedReg = [&](Register Reg) {
18681868
for (MCRegAliasIterator RAI(Reg, TRI, true); RAI.isValid(); ++RAI)
1869-
if (CalleeSavedRegs.test(*RAI))
1869+
if (CalleeSavedRegs.test((*RAI).id()))
18701870
return true;
18711871
return false;
18721872
};

Diff for: ‎llvm/lib/CodeGen/LiveRegMatrix.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,8 @@ bool LiveRegMatrix::checkRegMaskInterference(const LiveInterval &VirtReg,
165165
// The BitVector is indexed by PhysReg, not register unit.
166166
// Regmask interference is more fine grained than regunits.
167167
// For example, a Win64 call can clobber %ymm8 yet preserve %xmm8.
168-
return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg));
168+
return !RegMaskUsable.empty() &&
169+
(!PhysReg || !RegMaskUsable.test(PhysReg.id()));
169170
}
170171

171172
bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg,

Diff for: ‎llvm/lib/CodeGen/MachineRegisterInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -584,7 +584,7 @@ static bool isNoReturnDef(const MachineOperand &MO) {
584584

585585
bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
586586
bool SkipNoReturnDef) const {
587-
if (UsedPhysRegMask.test(PhysReg))
587+
if (UsedPhysRegMask.test(PhysReg.id()))
588588
return true;
589589
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
590590
for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
@@ -599,7 +599,7 @@ bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
599599

600600
bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
601601
bool SkipRegMaskTest) const {
602-
if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
602+
if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg.id()))
603603
return true;
604604
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
605605
for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();

Diff for: ‎llvm/lib/CodeGen/PrologEpilogInserter.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -1240,9 +1240,9 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
12401240
continue;
12411241

12421242
MCRegister Reg = MO.getReg();
1243-
if (AllocatableSet[Reg] && !MO.isImplicit() &&
1243+
if (AllocatableSet[Reg.id()] && !MO.isImplicit() &&
12441244
(MO.isDef() || MO.isUse()))
1245-
UsedRegs.set(Reg);
1245+
UsedRegs.set(Reg.id());
12461246
}
12471247
}
12481248

@@ -1262,20 +1262,20 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
12621262
continue;
12631263

12641264
// Want only used registers.
1265-
if (OnlyUsed && !UsedRegs[Reg])
1265+
if (OnlyUsed && !UsedRegs[Reg.id()])
12661266
continue;
12671267

12681268
// Want only registers used for arguments.
12691269
if (OnlyArg) {
12701270
if (OnlyUsed) {
1271-
if (!LiveIns[Reg])
1271+
if (!LiveIns[Reg.id()])
12721272
continue;
12731273
} else if (!TRI.isArgumentRegister(MF, Reg)) {
12741274
continue;
12751275
}
12761276
}
12771277

1278-
RegsToZero.set(Reg);
1278+
RegsToZero.set(Reg.id());
12791279
}
12801280

12811281
// Don't clear registers that are live when leaving the function.
@@ -1328,7 +1328,7 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
13281328
for (const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
13291329
MCPhysReg CSReg = *CSRegs; ++CSRegs)
13301330
for (MCRegister Reg : TRI.sub_and_superregs_inclusive(CSReg))
1331-
RegsToZero.reset(Reg);
1331+
RegsToZero.reset(Reg.id());
13321332

13331333
const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
13341334
for (MachineBasicBlock &MBB : MF)

Diff for: ‎llvm/lib/CodeGen/RDFLiveness.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -960,7 +960,7 @@ void Liveness::resetKills(MachineBasicBlock *B) {
960960
continue;
961961
bool IsLive = false;
962962
for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
963-
if (!Live[*AR])
963+
if (!Live[(*AR).id()])
964964
continue;
965965
IsLive = true;
966966
break;

Diff for: ‎llvm/lib/CodeGen/RegAllocGreedy.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -439,7 +439,7 @@ MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg,
439439
}
440440

441441
// Try to evict interference from a cheaper alternative.
442-
uint8_t Cost = RegCosts[PhysReg];
442+
uint8_t Cost = RegCosts[PhysReg.id()];
443443

444444
// Most registers have 0 additional cost.
445445
if (!Cost)
@@ -559,7 +559,7 @@ RegAllocEvictionAdvisor::getOrderLimit(const LiveInterval &VirtReg,
559559

560560
bool RegAllocEvictionAdvisor::canAllocatePhysReg(unsigned CostPerUseLimit,
561561
MCRegister PhysReg) const {
562-
if (RegCosts[PhysReg] >= CostPerUseLimit)
562+
if (RegCosts[PhysReg.id()] >= CostPerUseLimit)
563563
return false;
564564
// The first use of a callee-saved register in a function has cost 1.
565565
// Don't start using a CSR when the CostPerUseLimit is low.

Diff for: ‎llvm/lib/CodeGen/RegUsageInfoCollector.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -162,12 +162,12 @@ bool RegUsageInfoCollector::run(MachineFunction &MF) {
162162
computeCalleeSavedRegs(SavedRegs, MF);
163163

164164
const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
165-
auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
166-
RegMask[Reg / 32] &= ~(1u << Reg % 32);
165+
auto SetRegAsDefined = [&RegMask](MCRegister Reg) {
166+
RegMask[Reg.id() / 32] &= ~(1u << Reg.id() % 32);
167167
};
168168

169169
// Don't include $noreg in any regmasks.
170-
SetRegAsDefined(MCRegister::NoRegister);
170+
SetRegAsDefined(MCRegister());
171171

172172
// Some targets can clobber registers "inside" a call, typically in
173173
// linker-generated code.
@@ -186,7 +186,7 @@ bool RegUsageInfoCollector::run(MachineFunction &MF) {
186186
// with all it's unsaved aliases.
187187
if (!MRI->def_empty(PReg)) {
188188
for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
189-
if (!SavedRegs.test(*AI))
189+
if (!SavedRegs.test((*AI).id()))
190190
SetRegAsDefined(*AI);
191191
continue;
192192
}

Diff for: ‎llvm/lib/CodeGen/RegisterClassInfo.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,8 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
9595
BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
9696
for (const MCPhysReg *I = CSR; *I; ++I)
9797
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
98-
CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
98+
CSRHintsForAllocOrder[(*AI).id()] =
99+
STI.ignoreCSRForAllocationOrder(mf, *AI);
99100
if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
100101
Update = true;
101102
IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;

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