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[SelectionDAG][X86] Add floating point promotion.
When lowering atomic vector types with floats, selection can fail since this pattern is unsupported. To support this, floats can be casted to an integer type of the same size.
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llvm/lib/Target/X86/X86ISelLowering.cpp

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@@ -2589,6 +2589,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(Op, MVT::f32, Promote);
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}
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setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
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setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
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setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
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// We have target-specific dag combine patterns for the following nodes:
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setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
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ISD::SCALAR_TO_VECTOR,
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc %s --mtriple=x86_64 -o - | FileCheck %s
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define <1 x i32> @atomic_scalar_i32(ptr %x) {
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; CHECK-LABEL: atomic_scalar_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: retq
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%ret = load atomic <1 x i32>, ptr %x acquire, align 4
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ret <1 x i32> %ret
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}
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define <1 x float> @atomic_scalar_float(ptr %x) {
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; CHECK-LABEL: atomic_scalar_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: retq
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%ret = load atomic <1 x float>, ptr %x acquire, align 4
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ret <1 x float> %ret
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}
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define <1 x half> @atomic_scalar_half(ptr %x) {
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; CHECK-LABEL: atomic_scalar_half:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK-NEXT: retq
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%ret = load atomic <1 x half>, ptr %x acquire, align 4
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ret <1 x half> %ret
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}
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define <1 x bfloat> @atomic_scalar_bfloat(ptr %x) {
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; CHECK-LABEL: atomic_scalar_bfloat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK-NEXT: retq
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%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
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ret <1 x bfloat> %ret
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}

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