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Stefan Pintiletstellar
Stefan Pintile
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[PowerPC] Implementing overflow version for XO-Form instructions
The Overflow version of XO-Form instruction uses the SO, OV and OV32 special registers. This changes modifies existing multiclasses and instruction definitions to allow for the use of the XER register to record the various types if overflow from possible add, subtract and multiply instructions. It then modifies the existing instructions as to use these multiclasses as needed. Patch By: Kamau Bridgeman Differential Revision: https://reviews.llvm.org/D66902 (cherry picked from commit fdf3d17)
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‎llvm/lib/Target/PowerPC/P9InstrResources.td‎

Lines changed: 28 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -128,14 +128,14 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
128128
(instregex "MTVSRW(A|Z)$"),
129129
(instregex "CMP(WI|LWI|W|LW)(8)?$"),
130130
(instregex "CMP(L)?D(I)?$"),
131-
(instregex "SUBF(I)?C(8)?$"),
131+
(instregex "SUBF(I)?C(8)?(O)?$"),
132132
(instregex "ANDI(S)?o(8)?$"),
133-
(instregex "ADDC(8)?$"),
133+
(instregex "ADDC(8)?(O)?$"),
134134
(instregex "ADDIC(8)?(o)?$"),
135-
(instregex "ADD(8|4)(o)?$"),
136-
(instregex "ADD(E|ME|ZE)(8)?(o)?$"),
137-
(instregex "SUBF(E|ME|ZE)?(8)?(o)?$"),
138-
(instregex "NEG(8)?(o)?$"),
135+
(instregex "ADD(8|4)(O)?(o)?$"),
136+
(instregex "ADD(E|ME|ZE)(8)?(O)?(o)?$"),
137+
(instregex "SUBF(E|ME|ZE)?(8)?(O)?(o)?$"),
138+
(instregex "NEG(8)?(O)?(o)?$"),
139139
(instregex "POPCNTB$"),
140140
(instregex "ADD(I|IS)?(8)?$"),
141141
(instregex "LI(S)?(8)?$"),
@@ -147,7 +147,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
147147
(instregex "EQV(8)?(o)?$"),
148148
(instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
149149
(instregex "ADD(4|8)(TLS)?(_)?$"),
150-
(instregex "NEG(8)?$"),
150+
(instregex "NEG(8)?(O)?$"),
151151
(instregex "ADDI(S)?toc(HA|L)$"),
152152
COPY,
153153
MCRF,
@@ -397,7 +397,7 @@ def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
397397
def : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_3SLOTS_1C],
398398
(instrs
399399
(instregex "MADD(HD|HDU|LD|LD8)$"),
400-
(instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?$")
400+
(instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?(O)?$")
401401
)>;
402402

403403
// 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
@@ -456,7 +456,7 @@ def : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
456456
def : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C,
457457
DISP_3SLOTS_1C, DISP_1C],
458458
(instrs
459-
(instregex "MUL(H|L)(D|W)(U)?o$")
459+
(instregex "MUL(H|L)(D|W)(U)?(O)?o$")
460460
)>;
461461

462462
// 7 cycle Restricted DP operation and one 3 cycle ALU operation.
@@ -944,7 +944,9 @@ def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_EVEN_1C],
944944
def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
945945
(instrs
946946
DIVW,
947+
DIVWO,
947948
DIVWU,
949+
DIVWUO,
948950
MODSW
949951
)>;
950952

@@ -954,9 +956,13 @@ def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
954956
def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
955957
(instrs
956958
DIVWE,
959+
DIVWEO,
957960
DIVD,
961+
DIVDO,
958962
DIVWEU,
963+
DIVWEUO,
959964
DIVDU,
965+
DIVDUO,
960966
MODSD,
961967
MODUD,
962968
MODUW
@@ -968,7 +974,9 @@ def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
968974
def : InstRW<[P9_DIV_40C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
969975
(instrs
970976
DIVDE,
971-
DIVDEU
977+
DIVDEO,
978+
DIVDEU,
979+
DIVDEUO
972980
)>;
973981

974982
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
@@ -987,9 +995,13 @@ def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
987995
DISP_EVEN_1C, DISP_1C],
988996
(instrs
989997
DIVDo,
998+
DIVDOo,
990999
DIVDUo,
1000+
DIVDUOo,
9911001
DIVWEo,
992-
DIVWEUo
1002+
DIVWEOo,
1003+
DIVWEUo,
1004+
DIVWEUOo
9931005
)>;
9941006

9951007
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
@@ -999,7 +1011,9 @@ def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
9991011
DISP_EVEN_1C, DISP_1C],
10001012
(instrs
10011013
DIVDEo,
1002-
DIVDEUo
1014+
DIVDEOo,
1015+
DIVDEUo,
1016+
DIVDEUOo
10031017
)>;
10041018

10051019
// CR access instructions in _BrMCR, IIC_BrMCRX.
@@ -1024,8 +1038,8 @@ def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
10241038
def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
10251039
DISP_1C, DISP_1C],
10261040
(instrs
1027-
(instregex "ADDC(8)?o$"),
1028-
(instregex "SUBFC(8)?o$")
1041+
(instregex "ADDC(8)?(O)?o$"),
1042+
(instregex "SUBFC(8)?(O)?o$")
10291043
)>;
10301044

10311045
// Cracked ALU operations.

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 17 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -497,9 +497,9 @@ def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
497497
[(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
498498

499499
let isCommutable = 1 in
500-
defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
501-
"add", "$rT, $rA, $rB", IIC_IntSimple,
502-
[(set i64:$rT, (add i64:$rA, i64:$rB))]>;
500+
defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
501+
"add", "$rT, $rA, $rB", IIC_IntSimple,
502+
[(set i64:$rT, (add i64:$rA, i64:$rB))]>;
503503
// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
504504
// initial-exec thread-local storage model. We need to forbid r0 here -
505505
// while it works for add just fine, the linker can relax this to local-exec
@@ -576,9 +576,9 @@ defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
576576
"subfc", "$rT, $rA, $rB", IIC_IntGeneral,
577577
[(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
578578
PPC970_DGroup_Cracked;
579-
defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
580-
"subf", "$rT, $rA, $rB", IIC_IntGeneral,
581-
[(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
579+
defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
580+
"subf", "$rT, $rA, $rB", IIC_IntGeneral,
581+
[(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
582582
defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
583583
"neg", "$rT, $rA", IIC_IntSimple,
584584
[(set i64:$rT, (ineg i64:$rA))]>;
@@ -777,10 +777,10 @@ defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
777777
defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
778778
"divdu", "$rT, $rA, $rB", IIC_IntDivD,
779779
[(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64;
780-
def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
781-
"divde $rT, $rA, $rB", IIC_IntDivD,
782-
[(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
783-
isPPC64, Requires<[HasExtDiv]>;
780+
defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
781+
"divde", "$rT, $rA, $rB", IIC_IntDivD,
782+
[(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
783+
isPPC64, Requires<[HasExtDiv]>;
784784

785785
let Predicates = [IsISA3_0] in {
786786
def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
@@ -815,24 +815,14 @@ def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
815815
[(set i64:$rT, (urem i64:$rA, i64:$rB))]>;
816816
}
817817

818-
let Defs = [CR0] in
819-
def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
820-
"divde. $rT, $rA, $rB", IIC_IntDivD,
821-
[]>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
822-
isPPC64, Requires<[HasExtDiv]>;
823-
def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
824-
"divdeu $rT, $rA, $rB", IIC_IntDivD,
825-
[(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
826-
isPPC64, Requires<[HasExtDiv]>;
827-
let Defs = [CR0] in
828-
def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
829-
"divdeu. $rT, $rA, $rB", IIC_IntDivD,
830-
[]>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
831-
isPPC64, Requires<[HasExtDiv]>;
818+
defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
819+
"divdeu", "$rT, $rA, $rB", IIC_IntDivD,
820+
[(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
821+
isPPC64, Requires<[HasExtDiv]>;
832822
let isCommutable = 1 in
833-
defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
834-
"mulld", "$rT, $rA, $rB", IIC_IntMulHD,
835-
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
823+
defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
824+
"mulld", "$rT, $rA, $rB", IIC_IntMulHD,
825+
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
836826
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
837827
def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
838828
"mulli $rD, $rA, $imm", IIC_IntMulLI,

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 83 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1023,6 +1023,32 @@ multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
10231023
}
10241024
}
10251025

1026+
// Multiclass for instructions which have a record overflow form as well
1027+
// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.)
1028+
multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1029+
string asmbase, string asmstr, InstrItinClass itin,
1030+
list<dag> pattern> {
1031+
let BaseName = asmbase in {
1032+
def NAME : XOForm_1<opcode, xo, 0, OOL, IOL,
1033+
!strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1034+
pattern>, RecFormRel;
1035+
let Defs = [CR0] in
1036+
def o : XOForm_1<opcode, xo, 0, OOL, IOL,
1037+
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1038+
[]>, isDOT, RecFormRel;
1039+
}
1040+
let BaseName = !strconcat(asmbase, "O") in {
1041+
let Defs = [XER] in
1042+
def O : XOForm_1<opcode, xo, 1, OOL, IOL,
1043+
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1044+
[]>, RecFormRel;
1045+
let Defs = [XER, CR0] in
1046+
def Oo : XOForm_1<opcode, xo, 1, OOL, IOL,
1047+
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1048+
[]>, isDOT, RecFormRel;
1049+
}
1050+
}
1051+
10261052
// Multiclass for instructions for which the non record form is not cracked
10271053
// and the record form is cracked (i.e. divw, mullw, etc.)
10281054
multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
@@ -1038,6 +1064,16 @@ multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
10381064
[]>, isDOT, RecFormRel, PPC970_DGroup_First,
10391065
PPC970_DGroup_Cracked;
10401066
}
1067+
let BaseName = !strconcat(asmbase, "O") in {
1068+
let Defs = [XER] in
1069+
def O : XOForm_1<opcode, xo, 1, OOL, IOL,
1070+
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1071+
[]>, RecFormRel;
1072+
let Defs = [XER, CR0] in
1073+
def Oo : XOForm_1<opcode, xo, 1, OOL, IOL,
1074+
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1075+
[]>, isDOT, RecFormRel;
1076+
}
10411077
}
10421078

10431079
multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
@@ -1053,6 +1089,16 @@ multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
10531089
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
10541090
[]>, isDOT, RecFormRel;
10551091
}
1092+
let BaseName = !strconcat(asmbase, "O") in {
1093+
let Defs = [CARRY, XER] in
1094+
def O : XOForm_1<opcode, xo, 1, OOL, IOL,
1095+
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1096+
[]>, RecFormRel;
1097+
let Defs = [CARRY, XER, CR0] in
1098+
def Oo : XOForm_1<opcode, xo, 1, OOL, IOL,
1099+
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1100+
[]>, isDOT, RecFormRel;
1101+
}
10561102
}
10571103

10581104
multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
@@ -1067,6 +1113,16 @@ multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
10671113
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
10681114
[]>, isDOT, RecFormRel;
10691115
}
1116+
let BaseName = !strconcat(asmbase, "O") in {
1117+
let Defs = [XER] in
1118+
def O : XOForm_3<opcode, xo, 1, OOL, IOL,
1119+
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1120+
[]>, RecFormRel;
1121+
let Defs = [XER, CR0] in
1122+
def Oo : XOForm_3<opcode, xo, 1, OOL, IOL,
1123+
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1124+
[]>, isDOT, RecFormRel;
1125+
}
10701126
}
10711127

10721128
multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
@@ -1082,6 +1138,16 @@ multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
10821138
!strconcat(asmbase, !strconcat(". ", asmstr)), itin,
10831139
[]>, isDOT, RecFormRel;
10841140
}
1141+
let BaseName = !strconcat(asmbase, "O") in {
1142+
let Defs = [CARRY, XER] in
1143+
def O : XOForm_3<opcode, xo, 1, OOL, IOL,
1144+
!strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1145+
[]>, RecFormRel;
1146+
let Defs = [CARRY, XER, CR0] in
1147+
def Oo : XOForm_3<opcode, xo, 1, OOL, IOL,
1148+
!strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1149+
[]>, isDOT, RecFormRel;
1150+
}
10851151
}
10861152

10871153
multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
@@ -2776,9 +2842,9 @@ def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
27762842
let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
27772843
// XO-Form instructions. Arithmetic instructions that can set overflow bit
27782844
let isCommutable = 1 in
2779-
defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2780-
"add", "$rT, $rA, $rB", IIC_IntSimple,
2781-
[(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2845+
defm ADD4 : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2846+
"add", "$rT, $rA, $rB", IIC_IntSimple,
2847+
[(set i32:$rT, (add i32:$rA, i32:$rB))]>;
27822848
let isCodeGenOnly = 1 in
27832849
def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
27842850
"add $rT, $rA, $rB", IIC_IntSimple,
@@ -2795,38 +2861,28 @@ defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
27952861
defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
27962862
"divwu", "$rT, $rA, $rB", IIC_IntDivW,
27972863
[(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2798-
def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2799-
"divwe $rT, $rA, $rB", IIC_IntDivW,
2800-
[(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2801-
Requires<[HasExtDiv]>;
2802-
let Defs = [CR0] in
2803-
def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2804-
"divwe. $rT, $rA, $rB", IIC_IntDivW,
2805-
[]>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2806-
Requires<[HasExtDiv]>;
2807-
def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2808-
"divweu $rT, $rA, $rB", IIC_IntDivW,
2809-
[(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2810-
Requires<[HasExtDiv]>;
2811-
let Defs = [CR0] in
2812-
def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2813-
"divweu. $rT, $rA, $rB", IIC_IntDivW,
2814-
[]>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2815-
Requires<[HasExtDiv]>;
2864+
defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2865+
"divwe", "$rT, $rA, $rB", IIC_IntDivW,
2866+
[(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2867+
Requires<[HasExtDiv]>;
2868+
defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2869+
"divweu", "$rT, $rA, $rB", IIC_IntDivW,
2870+
[(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2871+
Requires<[HasExtDiv]>;
28162872
let isCommutable = 1 in {
28172873
defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
28182874
"mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
28192875
[(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
28202876
defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
28212877
"mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
28222878
[(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2823-
defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2824-
"mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2825-
[(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2879+
defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2880+
"mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2881+
[(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
28262882
} // isCommutable
2827-
defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2828-
"subf", "$rT, $rA, $rB", IIC_IntGeneral,
2829-
[(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2883+
defm SUBF : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2884+
"subf", "$rT, $rA, $rB", IIC_IntGeneral,
2885+
[(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
28302886
defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
28312887
"subfc", "$rT, $rA, $rB", IIC_IntGeneral,
28322888
[(set i32:$rT, (subc i32:$rB, i32:$rA))]>,

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