RISC-V sanitizers

[efa]

the ISA is become more and more important, please add support for sanitizers at least for Linux

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: efa (efa)

Details

the ISA is become more and more important, please add support for sanitizers at least for Linux

[topperc]

What sanitizer isn't working?

[thurstond]

ASan, HWASan, and TSan already have shadow mappings defined for RISC-V. I assume most minor bits and pieces are already there too.

UBSan isn't platform-specific, so that should work out of the box.

MTE: there is currently no ratified RISC-V memory tagging spec.

The hard case is probably MSan:

• [easy to fix] There are currently no RISC-V-specific shadow mappings (maybe the default Linux 64-bit mapping will work? YOLO)
• [hard to fix] MSan does not explicitly handle any of the @llvm.riscv.* intrinsics. Some will be handled correctly anyway, if the RISC-V intrinsic is auto-upgraded into cross-platform LLVM intrinsics. Some others will be "heuristically" handled (possibly incorrectly). The rest will default to the "strict" handler, which checks that the parameters are fully initialized.

[lenary]

@thurstond Thank you for summarising. Please may you put these docs into RISCVUsage please?