diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index 08e567f2e640a..6bad4ebcff181 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -71,9 +71,13 @@ class LegalizationArtifactCombiner { Register TruncSrc; if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI); - if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) + auto DstType = MRI.getType(DstReg); + auto SrcType = MRI.getType(TruncSrc); + if (DstType == SrcType) replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs, Observer); + else if (DstType.getSizeInBits() == SrcType.getSizeInBits()) + Builder.buildBitcast(DstReg, TruncSrc); else Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); UpdatedDefs.push_back(DstReg); diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp index 2967fc3a602d1..e429db90bb95e 100644 --- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp @@ -71,6 +71,7 @@ bool CSEConfigFull::shouldCSEOpc(unsigned Opc) { case TargetOpcode::G_FMINNUM: case TargetOpcode::G_FMAXNUM_IEEE: case TargetOpcode::G_FMINNUM_IEEE: + case TargetOpcode::G_BITCAST: return true; } return false; diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index c555b67d9198c..c8639ee890539 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -363,6 +363,7 @@ getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, return std::nullopt; break; case TargetOpcode::G_INTTOPTR: + case TargetOpcode::G_BITCAST: VReg = MI->getOperand(1).getReg(); break; default: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir index 9cc747f1f5361..e972e7a2895e5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir @@ -73,3 +73,20 @@ body: | %2:_(<3 x s32>) = G_ANYEXT %1 $vgpr0_vgpr1_vgpr2 = COPY %2 ... + +--- +name: test_anyext_trunc_i32_to_i16_to_f32 +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: test_anyext_trunc_i32_to_i16_to_f32 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[COPY]](i32) + ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + %0:_(i32) = COPY $vgpr0 + %1:_(i16) = G_TRUNC %0(i32) + %2:_(f32) = G_ANYEXT %1(i16) + $vgpr0 = COPY %2(f32) +... \ No newline at end of file diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll index aa389eec4f991..bb9984797d2ae 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll @@ -29,18 +29,16 @@ define <2 x i16> @vop3p_add_v2i16(<2 x i16> %arg0) #0 { ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x i16>) - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[BITCAST1]](i32) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i16) = G_ADD [[TRUNC]], [[TRUNC2]] - ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i16) = G_ADD [[TRUNC1]], [[TRUNC3]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i16) = COPY [[TRUNC]](i16) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i16) = COPY [[TRUNC1]](i16) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i16) = G_ADD [[TRUNC]], [[COPY1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i16) = G_ADD [[TRUNC1]], [[COPY2]] ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[ADD]](i16) ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ADD1]](i16) ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]] - ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32) - ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x i16>) + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32) + ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x i16>) ; CHECK-NEXT: SI_RETURN implicit $vgpr0 %add = add <2 x i16> %arg0, %arg0 ret <2 x i16> %add @@ -69,18 +67,16 @@ define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 { ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[BITCAST]](<2 x i16>) ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) - ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[BITCAST]](<2 x i16>) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) - ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[BITCAST1]], [[BITCAST2]] - ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[LSHR]], [[LSHR1]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[BITCAST1]], [[BITCAST1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[LSHR]], [[LSHR]] ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ADD]], [[C1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ADD1]], [[C1]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C]](i32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]] - ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32) - ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[BITCAST3]](<2 x i16>) - ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST4]](i32) + ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32) + ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[BITCAST2]](<2 x i16>) + ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST3]](i32) ; CHECK-NEXT: SI_RETURN implicit $vgpr0 %add = add <2 x i16> %arg0, %arg0 ret <2 x i16> %add diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir index 6efd646679157..d8def4b8b4c5e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir @@ -831,29 +831,25 @@ body: | ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](i32) ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) - ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>) - ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](i32) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C]](i32) - ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](i32) - ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>) - ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST4]](i32) - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST4]], [[C]](i32) - ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](i32) - ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC4]] - ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC5]] - ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[TRUNC6]] - ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[TRUNC7]] + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16) + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[COPY1]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[COPY2]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[COPY3]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[COPY4]] ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[ADD]](s16) ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ADD1]](s16) ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ZEXT1]], [[C]](i32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[ZEXT]], [[SHL]] - ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[ADD2]](s16) ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[ADD3]](s16) ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[ZEXT3]], [[C]](i32) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[SHL1]] - ; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32) - ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST5]](<2 x s16>), [[BITCAST6]](<2 x s16>) + ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>) ; CHECK-NEXT: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<4 x s16>) = G_BITCAST %0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir index 3272a08aadb75..fbdce424435c3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir @@ -204,14 +204,13 @@ body: | ; GFX6-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00 ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C9]], [[C10]] ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT2]](f64) - ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i64) = G_BITCAST [[COPY]](f64) ; GFX6-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808 ; GFX6-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807 ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[BITCAST2]], [[C12]] - ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST3]], [[C11]] + ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C11]] ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND2]], [[AND3]] - ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64) - ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[BITCAST4]] + ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64) + ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[BITCAST3]] ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[FADD1]](f64) ; ; GFX8-LABEL: name: test_intrinsic_round_f64 @@ -429,40 +428,38 @@ body: | ; GFX6-NEXT: [[C10:%[0-9]+]]:_(f64) = G_FCONSTANT double 0.000000e+00 ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f64) = G_SELECT [[FCMP]](i1), [[C9]], [[C10]] ; GFX6-NEXT: [[BITCAST2:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT2]](f64) - ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(i64) = G_BITCAST [[UV]](f64) ; GFX6-NEXT: [[C11:%[0-9]+]]:_(i64) = G_CONSTANT i64 -9223372036854775808 ; GFX6-NEXT: [[C12:%[0-9]+]]:_(i64) = G_CONSTANT i64 9223372036854775807 ; GFX6-NEXT: [[AND2:%[0-9]+]]:_(i64) = G_AND [[BITCAST2]], [[C12]] - ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST3]], [[C11]] + ; GFX6-NEXT: [[AND3:%[0-9]+]]:_(i64) = G_AND [[BITCAST]], [[C11]] ; GFX6-NEXT: [[OR:%[0-9]+]]:_(i64) = disjoint G_OR [[AND2]], [[AND3]] - ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64) - ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[BITCAST4]] - ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64) - ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST5]](i64) + ; GFX6-NEXT: [[BITCAST3:%[0-9]+]]:_(f64) = G_BITCAST [[OR]](i64) + ; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f64) = G_FADD [[BITCAST1]], [[BITCAST3]] + ; GFX6-NEXT: [[BITCAST4:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64) + ; GFX6-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST4]](i64) ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(i32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](i32), [[C]](i32), [[C1]](i32) ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[INT1]], [[C2]] ; GFX6-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[UV5]], [[C3]] ; GFX6-NEXT: [[MV1:%[0-9]+]]:_(i64) = G_MERGE_VALUES [[C5]](i32), [[AND4]](i32) ; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(i64) = G_ASHR [[C4]], [[SUB1]](i32) ; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(i64) = G_XOR [[ASHR1]], [[C6]] - ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[BITCAST5]], [[XOR1]] + ; GFX6-NEXT: [[AND5:%[0-9]+]]:_(i64) = G_AND [[BITCAST4]], [[XOR1]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](i32), [[C5]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](i32), [[C7]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(i64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND5]] - ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(i64) = G_SELECT [[ICMP3]](s1), [[BITCAST5]], [[SELECT3]] - ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT4]](i64) - ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST6]] + ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(i64) = G_SELECT [[ICMP3]](s1), [[BITCAST4]], [[SELECT3]] + ; GFX6-NEXT: [[BITCAST5:%[0-9]+]]:_(f64) = G_BITCAST [[SELECT4]](i64) + ; GFX6-NEXT: [[FNEG1:%[0-9]+]]:_(f64) = G_FNEG [[BITCAST5]] ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(f64) = G_FADD [[UV1]], [[FNEG1]] ; GFX6-NEXT: [[FABS1:%[0-9]+]]:_(f64) = G_FABS [[FADD2]] ; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(i1) = G_FCMP floatpred(oge), [[FABS1]](f64), [[C8]] ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f64) = G_SELECT [[FCMP1]](i1), [[C9]], [[C10]] - ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT5]](f64) - ; GFX6-NEXT: [[BITCAST8:%[0-9]+]]:_(i64) = G_BITCAST [[UV1]](f64) - ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[BITCAST7]], [[C12]] - ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[BITCAST8]], [[C11]] + ; GFX6-NEXT: [[BITCAST6:%[0-9]+]]:_(i64) = G_BITCAST [[SELECT5]](f64) + ; GFX6-NEXT: [[AND6:%[0-9]+]]:_(i64) = G_AND [[BITCAST6]], [[C12]] + ; GFX6-NEXT: [[AND7:%[0-9]+]]:_(i64) = G_AND [[BITCAST4]], [[C11]] ; GFX6-NEXT: [[OR1:%[0-9]+]]:_(i64) = disjoint G_OR [[AND6]], [[AND7]] - ; GFX6-NEXT: [[BITCAST9:%[0-9]+]]:_(f64) = G_BITCAST [[OR1]](i64) - ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f64) = G_FADD [[BITCAST6]], [[BITCAST9]] + ; GFX6-NEXT: [[BITCAST7:%[0-9]+]]:_(f64) = G_BITCAST [[OR1]](i64) + ; GFX6-NEXT: [[FADD3:%[0-9]+]]:_(f64) = G_FADD [[BITCAST5]], [[BITCAST7]] ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f64>) = G_BUILD_VECTOR [[FADD1]](f64), [[FADD3]](f64) ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x f64>) ; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll index d761f2cd8a97e..58559584c4959 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll @@ -113,9 +113,8 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -144,9 +143,8 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -175,9 +173,8 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -214,12 +211,11 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -252,12 +248,11 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -289,12 +284,11 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -334,12 +328,11 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -372,12 +365,11 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -409,12 +401,11 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -453,9 +444,8 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -484,9 +474,8 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -515,9 +504,8 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -554,12 +542,11 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -592,12 +579,11 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -629,12 +615,11 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -674,12 +659,11 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -712,12 +696,11 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -749,12 +732,11 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -794,15 +776,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -834,15 +814,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -873,15 +851,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -920,9 +896,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -951,9 +926,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -982,9 +956,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) @@ -1021,12 +994,11 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1059,12 +1031,11 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1096,12 +1067,11 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1141,15 +1111,13 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1181,15 +1149,13 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1220,15 +1186,13 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1268,15 +1232,13 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1308,15 +1270,13 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1347,15 +1307,13 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1395,12 +1353,11 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1433,12 +1390,11 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1470,12 +1426,11 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1515,15 +1470,13 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1555,15 +1508,13 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1594,15 +1545,13 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -1736,9 +1685,8 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -1767,9 +1715,8 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -1798,9 +1745,8 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -1837,12 +1783,11 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1875,12 +1820,11 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1912,12 +1856,11 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1957,12 +1900,11 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -1995,12 +1937,11 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2032,12 +1973,11 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2076,9 +2016,8 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -2107,9 +2046,8 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -2138,9 +2076,8 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -2177,12 +2114,11 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2215,12 +2151,11 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2252,12 +2187,11 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2297,12 +2231,11 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2335,12 +2268,11 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2372,12 +2304,11 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2417,15 +2348,13 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2457,15 +2386,13 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2496,15 +2423,13 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2543,9 +2468,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 3 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -2574,9 +2498,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -2605,9 +2528,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) @@ -2644,12 +2566,11 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2682,12 +2603,11 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2719,12 +2639,11 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -2764,15 +2683,13 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2804,15 +2721,13 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2843,15 +2758,13 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2891,15 +2804,13 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2931,15 +2842,13 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -2970,15 +2879,13 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -3018,12 +2925,11 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -3056,12 +2962,11 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -3093,12 +2998,11 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -3138,15 +3042,13 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -3178,15 +3080,13 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -3217,15 +3117,13 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -4994,22 +4892,21 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX9-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX9-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) - ; GFX9-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) - ; GFX9-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) - ; GFX9-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST1]](f32) + ; GFX9-NEXT: $vgpr1 = COPY [[BITCAST2]](f32) + ; GFX9-NEXT: $vgpr2 = COPY [[BITCAST3]](f32) + ; GFX9-NEXT: $vgpr3 = COPY [[BITCAST4]](f32) ; GFX9-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; ; GFX10NSA-LABEL: name: load_2d_tfe @@ -5031,22 +4928,21 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX10NSA-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX10NSA-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX10NSA-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) - ; GFX10NSA-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) - ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) - ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX10NSA-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST1]](f32) + ; GFX10NSA-NEXT: $vgpr1 = COPY [[BITCAST2]](f32) + ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST3]](f32) + ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST4]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; ; GFX12-LABEL: name: load_2d_tfe @@ -5068,22 +4964,21 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX12-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX12-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) - ; GFX12-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) - ; GFX12-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) - ; GFX12-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST1]](f32) + ; GFX12-NEXT: $vgpr1 = COPY [[BITCAST2]](f32) + ; GFX12-NEXT: $vgpr2 = COPY [[BITCAST3]](f32) + ; GFX12-NEXT: $vgpr3 = COPY [[BITCAST4]](f32) ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 main_body: %s = extractelement <2 x i16> %coords, i32 0 @@ -5116,12 +5011,11 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[DEF1:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -5130,14 +5024,14 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x f16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX9-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX9-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST3]](f32) - ; GFX9-NEXT: $vgpr1 = COPY [[BITCAST4]](f32) - ; GFX9-NEXT: $vgpr2 = COPY [[BITCAST5]](f32) - ; GFX9-NEXT: $vgpr3 = COPY [[BITCAST6]](f32) + ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX9-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX9-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX9-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX9-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; ; GFX10NSA-LABEL: name: load_3d_tfe @@ -5160,12 +5054,11 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[DEF1:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -5173,14 +5066,14 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX10NSA-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX10NSA-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX10NSA-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX10NSA-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST3]](f32) - ; GFX10NSA-NEXT: $vgpr1 = COPY [[BITCAST4]](f32) - ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST5]](f32) - ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST6]](f32) + ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX10NSA-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX10NSA-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX10NSA-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; ; GFX12-LABEL: name: load_3d_tfe @@ -5203,12 +5096,11 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[DEF1:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF @@ -5216,14 +5108,14 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX12-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX12-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST3]](f32) - ; GFX12-NEXT: $vgpr1 = COPY [[BITCAST4]](f32) - ; GFX12-NEXT: $vgpr2 = COPY [[BITCAST5]](f32) - ; GFX12-NEXT: $vgpr3 = COPY [[BITCAST6]](f32) + ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX12-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX12-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX12-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 main_body: %s = extractelement <2 x i16> %coords_lo, i32 0 @@ -5257,15 +5149,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX9-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX9-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX9-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX9-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX9-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX9-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) @@ -5273,14 +5163,14 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i ; GFX9-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x f16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 3 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX9-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX9-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX9-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX9-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST4]](f32) - ; GFX9-NEXT: $vgpr1 = COPY [[BITCAST5]](f32) - ; GFX9-NEXT: $vgpr2 = COPY [[BITCAST6]](f32) - ; GFX9-NEXT: $vgpr3 = COPY [[BITCAST7]](f32) + ; GFX9-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX9-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX9-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX9-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX9-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX9-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX9-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX9-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX9-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; ; GFX10NSA-LABEL: name: load_2darraymsaa_tfe @@ -5303,29 +5193,27 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i ; GFX10NSA-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX10NSA-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX10NSA-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX10NSA-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX10NSA-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX10NSA-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX10NSA-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX10NSA-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX10NSA-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX10NSA-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX10NSA-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX10NSA-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX10NSA-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX10NSA-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST4]](f32) - ; GFX10NSA-NEXT: $vgpr1 = COPY [[BITCAST5]](f32) - ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST6]](f32) - ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST7]](f32) + ; GFX10NSA-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX10NSA-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX10NSA-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX10NSA-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX10NSA-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; ; GFX12-LABEL: name: load_2darraymsaa_tfe @@ -5348,29 +5236,27 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i ; GFX12-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) - ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) ; GFX12-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 - ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) - ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX12-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX12-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32) ; GFX12-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) - ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) - ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX12-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) ; GFX12-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) ; GFX12-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) ; GFX12-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) ; GFX12-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) ; GFX12-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) - ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) - ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) - ; GFX12-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) - ; GFX12-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) - ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST4]](f32) - ; GFX12-NEXT: $vgpr1 = COPY [[BITCAST5]](f32) - ; GFX12-NEXT: $vgpr2 = COPY [[BITCAST6]](f32) - ; GFX12-NEXT: $vgpr3 = COPY [[BITCAST7]](f32) + ; GFX12-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX12-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX12-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX12-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX12-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX12-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX12-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX12-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 main_body: %s = extractelement <2 x i16> %coords_lo, i32 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll index 7714c72b04b8d..de7f0563fa1bc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll @@ -428,11 +428,11 @@ define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1100(<8 x i32> inreg %rsrc, ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[DEF]](i32) - ; GCN-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[DEF]](i32) + ; GCN-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY [[BITCAST2]](f32) ; GCN-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GCN-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) ; GCN-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) - ; GCN-NEXT: $vgpr3 = COPY [[BITCAST3]](f32) + ; GCN-NEXT: $vgpr3 = COPY [[COPY10]](f32) ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %tex @@ -643,10 +643,10 @@ define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1000(<8 x i32> inreg %r ; GCN-NEXT: G_STORE [[UV1]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) + ; GCN-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY [[BITCAST1]](f32) ; GCN-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GCN-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) - ; GCN-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) + ; GCN-NEXT: $vgpr2 = COPY [[COPY10]](f32) ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %tex = extractvalue { <3 x float>, i32 } %res, 0 @@ -679,10 +679,10 @@ define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_0000(<8 x i32> inreg %r ; GCN-NEXT: G_STORE [[UV1]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) + ; GCN-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY [[BITCAST1]](f32) ; GCN-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GCN-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) - ; GCN-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) + ; GCN-NEXT: $vgpr2 = COPY [[COPY10]](f32) ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %tex = extractvalue { <3 x float>, i32 } %res, 0 @@ -754,11 +754,11 @@ define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1100(<8 x i32> inreg %r ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) + ; GCN-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY [[BITCAST2]](f32) ; GCN-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GCN-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) ; GCN-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) - ; GCN-NEXT: $vgpr3 = COPY [[BITCAST3]](f32) + ; GCN-NEXT: $vgpr3 = COPY [[COPY10]](f32) ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %tex = extractvalue { <4 x float>, i32 } %res, 0 @@ -791,12 +791,12 @@ define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1000(<8 x i32> inreg %r ; GCN-NEXT: G_STORE [[UV1]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) + ; GCN-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY [[BITCAST1]](f32) + ; GCN-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY [[BITCAST1]](f32) ; GCN-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GCN-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) - ; GCN-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) - ; GCN-NEXT: $vgpr3 = COPY [[BITCAST3]](f32) + ; GCN-NEXT: $vgpr2 = COPY [[COPY10]](f32) + ; GCN-NEXT: $vgpr3 = COPY [[COPY11]](f32) ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %tex = extractvalue { <4 x float>, i32 } %res, 0 @@ -829,12 +829,12 @@ define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_0000(<8 x i32> inreg %r ; GCN-NEXT: G_STORE [[UV1]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) ; GCN-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) ; GCN-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) - ; GCN-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[DEF1]](i32) + ; GCN-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY [[BITCAST1]](f32) + ; GCN-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY [[BITCAST1]](f32) ; GCN-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GCN-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) - ; GCN-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) - ; GCN-NEXT: $vgpr3 = COPY [[BITCAST3]](f32) + ; GCN-NEXT: $vgpr2 = COPY [[COPY10]](f32) + ; GCN-NEXT: $vgpr3 = COPY [[COPY11]](f32) ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %tex = extractvalue { <4 x float>, i32 } %res, 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir index b7a88cdf80833..f4f098c497872 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir @@ -74,20 +74,18 @@ body: | ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) - ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) - ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST1]] - ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ADD]], [[C2]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ADD1]], [[C2]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C1]](i32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]] - ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) ; CHECK-NEXT: G_BR %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x s16>) = G_PHI [[COPY]](<2 x s16>), %bb.0, [[BITCAST2]](<2 x s16>), %bb.1 + ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<2 x s16>) = G_PHI [[COPY]](<2 x s16>), %bb.0, [[BITCAST1]](<2 x s16>), %bb.1 ; CHECK-NEXT: $vgpr0 = COPY [[PHI]](<2 x s16>) ; CHECK-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31 bb.0: @@ -227,26 +225,22 @@ body: | ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](i32) ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>) ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) - ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C1]](i32) - ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>) - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) - ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]] - ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]] - ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]] - ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]] + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST]] + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR]] + ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST1]] + ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR1]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[ADD]], [[C2]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[ADD1]], [[C2]] ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C1]](i32) ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]] - ; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[ADD2]], [[C2]] ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[ADD3]], [[C2]] ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C1]](i32) ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[SHL1]] - ; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32) - ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>) + ; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>) ; CHECK-NEXT: G_BR %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir index 3ea85832af248..de7c5430d0fb4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir @@ -143,16 +143,15 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](s32) + ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) ; GFX8-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C2]] ; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[LSHR1]], [[C3]](i32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_1 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -163,9 +162,8 @@ body: | ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](s32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) @@ -193,15 +191,14 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](s32) + ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX8-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C2]] ; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C3]](i32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[LSHR]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_1_0 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -213,8 +210,7 @@ body: | ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](s32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) @@ -453,16 +449,15 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](s32) + ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) ; GFX8-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C2]] ; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[LSHR1]], [[C3]](i32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_3 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -473,9 +468,8 @@ body: | ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](s32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) @@ -503,15 +497,14 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](s32) + ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX8-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C2]] ; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C3]](i32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[LSHR]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_3_2 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -523,8 +516,7 @@ body: | ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C1]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY1]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](s32) + ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) @@ -1026,17 +1018,15 @@ body: | ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[UV]](i32) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY2]], [[C1]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<4 x s16>) - ; GFX8-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>) - ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV2]](i32) + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV]](i32) ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[COPY3]], [[C]](s32) ; GFX8-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C2]] ; GFX8-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND]], [[C3]](i32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[LSHR]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v4s16_1_0 ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 @@ -1050,9 +1040,7 @@ body: | ; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY2]], [[C1]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<4 x s16>) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>) - ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV2]](i32) + ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV]](i32) ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[COPY3]], [[C]](s32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) @@ -1082,15 +1070,13 @@ body: | ; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[UV]](i32) ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY2]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<4 x s16>) - ; GFX8-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>) - ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV3]](i32) + ; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV1]](i32) ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[COPY3]], [[C]](s32) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[LSHR1]], [[C1]](i32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[LSHR]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v4s16_1_3 ; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 @@ -1103,9 +1089,7 @@ body: | ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[COPY2]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](i32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x i32>) = G_BITCAST [[COPY]](<4 x s16>) - ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[BITCAST1]](<2 x i32>) - ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV3]](i32) + ; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[UV1]](i32) ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[COPY3]], [[C]](s32) ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](i32) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll index ee93f413566e5..c5ed2ef7ff303 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll @@ -875,71 +875,38 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_ ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1013-NEXT: s_endpgm ; -; GFX11-TRUE16-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-TRUE16-NEXT: s_movk_i32 s8, 0x4600 -; GFX11-TRUE16-NEXT: s_movk_i32 s9, 0x4700 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s8, 0x4200 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s9, 0x4400 -; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, 2.0 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-TRUE16-NEXT: s_movk_i32 s3, 0x4800 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, 1.0 -; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s3, 0x4500 -; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo -; GFX11-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo -; GFX11-TRUE16-NEXT: flat_load_b32 v6, v[0:1] -; GFX11-TRUE16-NEXT: flat_load_b32 v7, v[2:3] -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v5, s10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-TRUE16-NEXT: s_endpgm -; -; GFX11-FAKE16-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, 0x42004600 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, 0x44004700 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, 0x45004800 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, s10 -; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, 2.0 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, 1.0 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 -; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo -; GFX11-FAKE16-NEXT: flat_load_b32 v6, v[0:1] -; GFX11-FAKE16-NEXT: flat_load_b32 v7, v[2:3] -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s9 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-FAKE16-NEXT: s_endpgm +; GFX11-LABEL: image_bvh_intersect_ray_a16_nsa_reassign: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_mov_b32 s8, 0x42004600 +; GFX11-NEXT: s_mov_b32 s9, 0x44004700 +; GFX11-NEXT: s_mov_b32 s10, 0x45004800 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v5, s10 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_lshlrev_b32 v4, 2, v0 +; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2 +; GFX11-NEXT: s_mov_b32 s2, 2.0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: s_mov_b32 s1, 1.0 +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo +; GFX11-NEXT: flat_load_b32 v6, v[0:1] +; GFX11-NEXT: flat_load_b32 v7, v[2:3] +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s8 +; GFX11-NEXT: v_mov_b32_e32 v4, s9 +; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[4:7] a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-NEXT: s_endpgm %lid = tail call i32 @llvm.amdgcn.workitem.id.x() %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid %node_ptr = load i32, ptr %gep_node_ptr, align 4 @@ -1123,70 +1090,36 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3] ; GFX1013-NEXT: s_endpgm ; -; GFX11-TRUE16-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_clause 0x1 -; GFX11-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 -; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-TRUE16-NEXT: s_movk_i32 s8, 0x4600 -; GFX11-TRUE16-NEXT: s_movk_i32 s9, 0x4700 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, 1.0 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s8, 0x4200 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s9, 0x4400 -; GFX11-TRUE16-NEXT: v_bfrev_b32_e32 v7, 4.0 -; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s6 -; GFX11-TRUE16-NEXT: s_movk_i32 s7, 0x4800 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, 2.0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s7, 0x4500 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s8 -; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v5, s10 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s6 -; GFX11-TRUE16-NEXT: flat_load_b32 v8, v[0:1] -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s9 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-TRUE16-NEXT: s_endpgm -; -; GFX11-FAKE16-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_clause 0x1 -; GFX11-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 -; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, 1.0 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, 0 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, 0x42004600 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, 0x44004700 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, 0x45004800 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v5, s10 -; GFX11-FAKE16-NEXT: v_bfrev_b32_e32 v7, 4.0 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v3, s8 -; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, 2.0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 -; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s6 -; GFX11-FAKE16-NEXT: flat_load_b32 v8, v[0:1] -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: flat_store_b128 v[0:1], v[0:3] -; GFX11-FAKE16-NEXT: s_endpgm +; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 +; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_mov_b32 s5, 1.0 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s8, 0x42004600 +; GFX11-NEXT: s_mov_b32 s9, 0x44004700 +; GFX11-NEXT: s_mov_b32 s10, 0x45004800 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v6, 0xb36211c6 :: v_dual_mov_b32 v5, s10 +; GFX11-NEXT: v_bfrev_b32_e32 v7, 4.0 +; GFX11-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v3, s8 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_lshlrev_b32 v2, 2, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, s6 +; GFX11-NEXT: s_mov_b32 s6, 2.0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo +; GFX11-NEXT: v_mov_b32_e32 v2, s6 +; GFX11-NEXT: flat_load_b32 v8, v[0:1] +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3] +; GFX11-NEXT: s_endpgm %lid = tail call i32 @llvm.amdgcn.workitem.id.x() %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid %ray_extent = load float, ptr %gep_ray, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll index ec149479868b5..1721f94d5d84c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll @@ -45,21 +45,20 @@ define <4 x half> @test_v4s16(<4 x half> %a) #0 { ; GCN-LABEL: test_v4s16: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0 -; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v0, v4 src0_sel:WORD_1 src1_sel:DWORD +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc +; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 -; GCN-NEXT: v_cndmask_b32_e64 v5, v0, 0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc ; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1 -; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v4 src0_sel:WORD_1 src1_sel:DWORD -; GCN-NEXT: v_cndmask_b32_e64 v2, v1, 0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[4:5] -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GCN-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc +; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; GCN-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GCN-NEXT: s_setpc_b64 s[30:31] entry: %fcmp = fcmp olt <4 x half> %a, zeroinitializer @@ -71,35 +70,34 @@ define <8 x half> @test_v8s16(<8 x half> %a) #0 { ; GCN-LABEL: test_v8s16: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v0 ; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0 -; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v0, v8 src0_sel:WORD_1 src1_sel:DWORD +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc +; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, v0, 0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc ; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1 -; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v8 src0_sel:WORD_1 src1_sel:DWORD +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc +; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v5 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2 -; GCN-NEXT: v_cndmask_b32_e64 v4, v1, 0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, 0, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc ; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2 -; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v2, v8 src0_sel:WORD_1 src1_sel:DWORD +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc +; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v6 ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3 -; GCN-NEXT: v_cndmask_b32_e64 v5, v2, 0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc ; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v3 -; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v3, v8 src0_sel:WORD_1 src1_sel:DWORD -; GCN-NEXT: v_cndmask_b32_e64 v6, v3, 0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v3, v7, 0, s[4:5] -; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GCN-NEXT: v_or_b32_sdwa v0, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GCN-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GCN-NEXT: v_or_b32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 -; GCN-NEXT: v_or_b32_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GCN-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc +; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v7 +; GCN-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v5 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc +; GCN-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v6 +; GCN-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v7 +; GCN-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GCN-NEXT: s_setpc_b64 s[30:31] entry: %fcmp = fcmp olt <8 x half> %a, zeroinitializer diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll index 0a3874e6f70c0..818a8b3de7674 100644 --- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll +++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll @@ -1010,14 +1010,14 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX9-SDAG: ; %bb.0: ; %entry ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX9-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX9-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX9-SDAG-NEXT: v_pk_mad_u16 v4, v1, v3, v1 ; GFX9-SDAG-NEXT: v_pk_mad_u16 v5, v0, v2, v0 ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v6, v5, v2 ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v7, v4, v3 ; GFX9-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX9-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 -; GFX9-SDAG-NEXT: v_pk_mad_u16 v3, v4, v3, 1 +; GFX9-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] +; GFX9-SDAG-NEXT: v_pk_mad_u16 v3, v4, v3, 1 op_sel_hi:[1,1,0] ; GFX9-SDAG-NEXT: v_pk_mad_u16 v2, v5, v2, 1 op_sel_hi:[1,1,0] ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1 ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -1048,14 +1048,14 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX10-SDAG: ; %bb.0: ; %entry ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX10-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX10-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX10-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX10-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX10-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX10-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX10-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX10-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX10-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX10-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1 @@ -1086,16 +1086,16 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX11-SDAG: ; %bb.0: ; %entry ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX11-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX11-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX11-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX11-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX11-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX11-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX11-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX11-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX11-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX11-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -1136,16 +1136,16 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0 ; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX1200-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -1187,16 +1187,16 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX1250-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX1250-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX1250-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX1250-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX1250-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX1250-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX1250-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX1250-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -2534,14 +2534,14 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX9-SDAG: ; %bb.0: ; %entry ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX9-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX9-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX9-SDAG-NEXT: v_pk_mad_u16 v4, v1, v3, v1 ; GFX9-SDAG-NEXT: v_pk_mad_u16 v5, v0, v2, v0 ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v6, v5, v2 ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v7, v4, v3 ; GFX9-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX9-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 -; GFX9-SDAG-NEXT: v_pk_mad_u16 v3, v4, v3, 1 +; GFX9-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] +; GFX9-SDAG-NEXT: v_pk_mad_u16 v3, v4, v3, 1 op_sel_hi:[1,1,0] ; GFX9-SDAG-NEXT: v_pk_mad_u16 v2, v5, v2, 1 op_sel_hi:[1,1,0] ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1 ; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -2572,14 +2572,14 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX10-SDAG: ; %bb.0: ; %entry ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX10-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX10-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX10-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX10-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX10-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX10-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX10-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX10-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX10-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX10-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 ; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v1, v7, v1 @@ -2610,16 +2610,16 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX11-SDAG: ; %bb.0: ; %entry ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX11-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX11-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX11-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX11-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX11-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX11-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX11-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX11-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX11-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX11-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -2660,16 +2660,16 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0 ; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX1200-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX1200-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX1200-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX1200-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX1200-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1200-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -2711,16 +2711,16 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) { ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX1250-SDAG-NEXT: v_pk_add_u16 v0, v0, 1 op_sel_hi:[1,0] -; GFX1250-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 +; GFX1250-SDAG-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v4, v0, v2, v0 ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v5, v1, v3, v1 ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v0, v0, v2, 1 op_sel_hi:[1,1,0] -; GFX1250-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 +; GFX1250-SDAG-NEXT: v_pk_mad_u16 v1, v1, v3, 1 op_sel_hi:[1,1,0] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-SDAG-NEXT: v_pk_mul_lo_u16 v6, v4, v2 ; GFX1250-SDAG-NEXT: v_pk_mul_lo_u16 v7, v5, v3 -; GFX1250-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 +; GFX1250-SDAG-NEXT: v_pk_mad_u16 v3, v5, v3, 1 op_sel_hi:[1,1,0] ; GFX1250-SDAG-NEXT: v_pk_mad_u16 v2, v4, v2, 1 op_sel_hi:[1,1,0] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX1250-SDAG-NEXT: v_pk_mul_lo_u16 v0, v6, v0 @@ -11021,7 +11021,7 @@ define <2 x i16> @clpeak_imad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) { ; GFX8-GISEL-NEXT: v_mad_u16 v4, v2, v1, v2 ; GFX8-GISEL-NEXT: v_mad_u16 v5, v0, v3, v0 ; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v4, v4, v1 -; GFX8-GISEL-NEXT: v_mul_lo_u16_sdwa v5, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v5, v5, v3 ; GFX8-GISEL-NEXT: v_mad_u16 v1, v2, v1, 1 ; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v3, 1 ; GFX8-GISEL-NEXT: v_mad_u16 v2, v4, v1, v1 @@ -11370,7 +11370,7 @@ define <2 x i16> @clpeak_umad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) { ; GFX8-GISEL-NEXT: v_mad_u16 v4, v2, v1, v2 ; GFX8-GISEL-NEXT: v_mad_u16 v5, v0, v3, v0 ; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v4, v4, v1 -; GFX8-GISEL-NEXT: v_mul_lo_u16_sdwa v5, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v5, v5, v3 ; GFX8-GISEL-NEXT: v_mad_u16 v1, v2, v1, 1 ; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v3, 1 ; GFX8-GISEL-NEXT: v_mad_u16 v2, v4, v1, v1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll index 99240b29d2a9e..b4b880ea39e69 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll @@ -261,14 +261,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_f64(ptr addrspace(1) %out, doubl ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s6, s7 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s6, s7 +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s6, s7 +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s6, s7 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -291,13 +289,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_f64(ptr addrspace(1) %out, doubl ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -320,13 +317,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_f64(ptr addrspace(1) %out, doubl ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -350,12 +346,11 @@ define amdgpu_kernel void @v_permlane16_b32_vss_f64(ptr addrspace(1) %out, doubl ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 false, i1 false) @@ -578,14 +573,12 @@ define amdgpu_kernel void @v_permlane16_b32_vii_f64(ptr addrspace(1) %out, doubl ; GFX10-GISEL-LABEL: v_permlane16_b32_vii_f64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, 1, 2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, 1, 2 +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, 1, 2 +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, 1, 2 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -604,13 +597,12 @@ define amdgpu_kernel void @v_permlane16_b32_vii_f64(ptr addrspace(1) %out, doubl ; GFX11-GISEL-LABEL: v_permlane16_b32_vii_f64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, 1, 2 -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, 1, 2 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, 1, 2 +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, 1, 2 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -629,13 +621,12 @@ define amdgpu_kernel void @v_permlane16_b32_vii_f64(ptr addrspace(1) %out, doubl ; GFX12-GISEL-LABEL: v_permlane16_b32_vii_f64: ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, 1, 2 -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, 1, 2 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, 1, 2 +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, 1, 2 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -655,12 +646,11 @@ define amdgpu_kernel void @v_permlane16_b32_vii_f64(ptr addrspace(1) %out, doubl ; GFX13-GISEL: ; %bb.0: ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, 1, 2 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, 1, 2 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, 1, 2 +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, 1, 2 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 1, i32 2, i1 false, i1 false) @@ -909,15 +899,13 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f64(ptr addrspace(1) %out, doubl ; GFX10-GISEL-LABEL: v_permlane16_b32_vll_f64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-GISEL-NEXT: s_movk_i32 s2, 0x1234 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s2, 0xc1d1 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s2, 0xc1d1 +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1 +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -938,15 +926,14 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f64(ptr addrspace(1) %out, doubl ; GFX11-GISEL-LABEL: v_permlane16_b32_vll_f64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_movk_i32 s2, 0x1234 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s2, 0xc1d1 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s2, 0xc1d1 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -967,15 +954,14 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f64(ptr addrspace(1) %out, doubl ; GFX12-GISEL-LABEL: v_permlane16_b32_vll_f64: ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x1234 ; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s2, 0xc1d1 -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s2, 0xc1d1 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1 +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -997,14 +983,13 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f64(ptr addrspace(1) %out, doubl ; GFX13-GISEL: ; %bb.0: ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 ; GFX13-GISEL-NEXT: s_movk_i32 s2, 0x1234 ; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s2, 0xc1d1 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s2, 0xc1d1 +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 4660, i32 49617, i1 false, i1 false) @@ -1413,90 +1398,50 @@ define amdgpu_kernel void @v_permlane16_b32_vvv_f64(ptr addrspace(1) %out, doubl ; GFX10-GISEL-NEXT: s_mov_b32 null, 0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; -; GFX11-SDAG-LABEL: v_permlane16_b32_vvv_f64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX11-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s4, v1 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-SDAG-NEXT: v_permlane16_b32 v0, v0, s4, s5 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_permlane16_b32 v1, v1, s4, s5 -; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-SDAG-NEXT: s_endpgm -; -; GFX11-GISEL-LABEL: v_permlane16_b32_vvv_f64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v1 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-GISEL-NEXT: s_endpgm -; -; GFX12-SDAG-LABEL: v_permlane16_b32_vvv_f64: -; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX12-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s4, v1 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, s3 -; GFX12-SDAG-NEXT: v_permlane16_b32 v0, v0, s4, s5 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s4, s5 -; GFX12-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-SDAG-NEXT: s_endpgm +; GFX11-LABEL: v_permlane16_b32_vvv_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX11-NEXT: v_bfe_u32 v0, v0, 10, 10 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readfirstlane_b32 s5, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_permlane16_b32 v1, v1, s4, s5 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm ; -; GFX12-GISEL-LABEL: v_permlane16_b32_vvv_f64: -; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v1 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-GISEL-NEXT: s_endpgm +; GFX12-LABEL: v_permlane16_b32_vvv_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX12-NEXT: v_bfe_u32 v0, v0, 10, 10 +; GFX12-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_readfirstlane_b32 s5, v0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 +; GFX12-NEXT: v_readfirstlane_b32 s4, v1 +; GFX12-NEXT: v_mov_b32_e32 v1, s3 +; GFX12-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_permlane16_b32 v1, v1, s4, s5 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_endpgm ; ; GFX13-SDAG-LABEL: v_permlane16_b32_vvv_f64: ; GFX13-SDAG: ; %bb.0: @@ -1520,16 +1465,15 @@ define amdgpu_kernel void @v_permlane16_b32_vvv_f64(ptr addrspace(1) %out, doubl ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0 ; GFX13-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s4, v1 ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %tidx = call i32 @llvm.amdgcn.workitem.id.x() @@ -1877,86 +1821,48 @@ define amdgpu_kernel void @v_permlane16_b32_vvs_f64(ptr addrspace(1) %out, doubl ; GFX10-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34 ; GFX10-GISEL-NEXT: s_mov_b32 null, 0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s6 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s6 +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s6 +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s6 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; -; GFX11-SDAG-LABEL: v_permlane16_b32_vvs_f64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_clause 0x1 -; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-SDAG-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-SDAG-NEXT: v_permlane16_b32 v1, v1, s5, s4 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_permlane16_b32 v0, v0, s5, s4 -; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-SDAG-NEXT: s_endpgm -; -; GFX11-GISEL-LABEL: v_permlane16_b32_vvs_f64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_clause 0x1 -; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v0, 0x3ff, v0 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s5, s4 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s5, s4 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-GISEL-NEXT: s_endpgm -; -; GFX12-SDAG-LABEL: v_permlane16_b32_vvs_f64: -; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_clause 0x1 -; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-SDAG-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s5, s4 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_permlane16_b32 v0, v0, s5, s4 -; GFX12-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-SDAG-NEXT: s_endpgm +; GFX11-LABEL: v_permlane16_b32_vvs_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_load_b32 s4, s[4:5], 0x34 +; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readfirstlane_b32 s5, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_permlane16_b32 v1, v1, s5, s4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_permlane16_b32 v0, v0, s5, s4 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm ; -; GFX12-GISEL-LABEL: v_permlane16_b32_vvs_f64: -; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_clause 0x1 -; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v0, 0x3ff, v0 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s3 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s5, s4 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s5, s4 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-GISEL-NEXT: s_endpgm +; GFX12-LABEL: v_permlane16_b32_vvs_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_load_b32 s4, s[4:5], 0x34 +; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_readfirstlane_b32 s5, v0 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 +; GFX12-NEXT: v_permlane16_b32 v1, v1, s5, s4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_permlane16_b32 v0, v0, s5, s4 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_endpgm ; ; GFX13-SDAG-LABEL: v_permlane16_b32_vvs_f64: ; GFX13-SDAG: ; %bb.0: @@ -1981,15 +1887,14 @@ define amdgpu_kernel void @v_permlane16_b32_vvs_f64(ptr addrspace(1) %out, doubl ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s5, s4 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s5, s4 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s5, s4 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s5, s4 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %tidx = call i32 @llvm.amdgcn.workitem.id.x() @@ -2378,14 +2283,12 @@ define amdgpu_kernel void @v_permlane16_b32_vsv_f64(ptr addrspace(1) %out, doubl ; GFX10-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34 ; GFX10-GISEL-NEXT: s_mov_b32 null, 0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s6, s4 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s6, s4 +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s6, s4 +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s6, s4 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -2412,15 +2315,14 @@ define amdgpu_kernel void @v_permlane16_b32_vsv_f64(ptr addrspace(1) %out, doubl ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 ; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -2447,15 +2349,14 @@ define amdgpu_kernel void @v_permlane16_b32_vsv_f64(ptr addrspace(1) %out, doubl ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 ; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -2482,18 +2383,17 @@ define amdgpu_kernel void @v_permlane16_b32_vsv_f64(ptr addrspace(1) %out, doubl ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 -; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX13-GISEL-NEXT: s_endpgm - %tidy = call i32 @llvm.amdgcn.workitem.id.y() +; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 +; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX13-GISEL-NEXT: s_endpgm + %tidy = call i32 @llvm.amdgcn.workitem.id.y() %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 %src1, i32 %tidy, i1 false, i1 false) store double %v, ptr addrspace(1) %out ret void @@ -2742,14 +2642,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_f64(ptr addrspace(1) %out, do ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s6, s7 op_sel:[1,0] -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s6, s7 op_sel:[1,0] +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s6, s7 op_sel:[1,0] +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s6, s7 op_sel:[1,0] ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -2772,13 +2670,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_f64(ptr addrspace(1) %out, do ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[1,0] -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[1,0] -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[1,0] +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[1,0] ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -2801,13 +2698,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_f64(ptr addrspace(1) %out, do ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[1,0] -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[1,0] -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[1,0] +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[1,0] ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -2831,12 +2727,11 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_f64(ptr addrspace(1) %out, do ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[1,0] -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[1,0] +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[1,0] +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[1,0] ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 true, i1 false) @@ -3087,14 +2982,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_bc_f64(ptr addrspace(1) %out, do ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s6, s7 op_sel:[0,1] -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s6, s7 op_sel:[0,1] +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s6, s7 op_sel:[0,1] +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s6, s7 op_sel:[0,1] ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -3117,13 +3010,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_bc_f64(ptr addrspace(1) %out, do ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[0,1] -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[0,1] -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[0,1] +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[0,1] ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -3146,13 +3038,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_bc_f64(ptr addrspace(1) %out, do ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[0,1] -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[0,1] -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[0,1] +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[0,1] ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -3176,12 +3067,11 @@ define amdgpu_kernel void @v_permlane16_b32_vss_bc_f64(ptr addrspace(1) %out, do ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[0,1] -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[0,1] +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[0,1] +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[0,1] ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 false, i1 true) @@ -3432,14 +3322,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_bc_f64(ptr addrspace(1) %out, ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v2, s6, s7 op_sel:[1,1] -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v3, s6, s7 op_sel:[1,1] +; GFX10-GISEL-NEXT: v_permlane16_b32 v0, v0, s6, s7 op_sel:[1,1] +; GFX10-GISEL-NEXT: v_permlane16_b32 v1, v1, s6, s7 op_sel:[1,1] ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -3462,13 +3350,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_bc_f64(ptr addrspace(1) %out, ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[1,1] -; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[1,1] -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[1,1] +; GFX11-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[1,1] ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -3491,13 +3378,12 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_bc_f64(ptr addrspace(1) %out, ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[1,1] -; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[1,1] -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[1,1] +; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[1,1] ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -3521,12 +3407,11 @@ define amdgpu_kernel void @v_permlane16_b32_vss_fi_bc_f64(ptr addrspace(1) %out, ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v2, s4, s5 op_sel:[1,1] -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v3, s4, s5 op_sel:[1,1] +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlane16_b32 v0, v0, s4, s5 op_sel:[1,1] +; GFX13-GISEL-NEXT: v_permlane16_b32 v1, v1, s4, s5 op_sel:[1,1] ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlane16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 true, i1 true) @@ -3777,14 +3662,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_f64(ptr addrspace(1) %out, doub ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s6, s7 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s6, s7 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s6, s7 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s6, s7 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -3807,13 +3690,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_f64(ptr addrspace(1) %out, doub ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -3836,13 +3718,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_f64(ptr addrspace(1) %out, doub ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -3866,12 +3747,11 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_f64(ptr addrspace(1) %out, doub ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlanex16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 false, i1 false) @@ -4094,14 +3974,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vii_f64(ptr addrspace(1) %out, doub ; GFX10-GISEL-LABEL: v_permlanex16_b32_vii_f64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, 1, 2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, 1, 2 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, 1, 2 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, 1, 2 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -4120,13 +3998,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vii_f64(ptr addrspace(1) %out, doub ; GFX11-GISEL-LABEL: v_permlanex16_b32_vii_f64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, 1, 2 -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, 1, 2 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, 1, 2 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, 1, 2 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -4145,13 +4022,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vii_f64(ptr addrspace(1) %out, doub ; GFX12-GISEL-LABEL: v_permlanex16_b32_vii_f64: ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, 1, 2 -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, 1, 2 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, 1, 2 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, 1, 2 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -4171,12 +4047,11 @@ define amdgpu_kernel void @v_permlanex16_b32_vii_f64(ptr addrspace(1) %out, doub ; GFX13-GISEL: ; %bb.0: ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, 1, 2 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, 1, 2 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, 1, 2 +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, 1, 2 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlanex16.f64(double %src0, double %src0, i32 1, i32 2, i1 false, i1 false) @@ -4425,15 +4300,13 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f64(ptr addrspace(1) %out, doub ; GFX10-GISEL-LABEL: v_permlanex16_b32_vll_f64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-GISEL-NEXT: s_movk_i32 s2, 0x1234 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s2, 0xc1d1 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s2, 0xc1d1 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -4454,15 +4327,14 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f64(ptr addrspace(1) %out, doub ; GFX11-GISEL-LABEL: v_permlanex16_b32_vll_f64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_movk_i32 s2, 0x1234 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s2, 0xc1d1 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s2, 0xc1d1 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -4483,15 +4355,14 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f64(ptr addrspace(1) %out, doub ; GFX12-GISEL-LABEL: v_permlanex16_b32_vll_f64: ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x1234 ; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s2, 0xc1d1 -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s2, 0xc1d1 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -4513,14 +4384,13 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f64(ptr addrspace(1) %out, doub ; GFX13-GISEL: ; %bb.0: ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 ; GFX13-GISEL-NEXT: s_movk_i32 s2, 0x1234 ; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s2, 0xc1d1 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s2, 0xc1d1 +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlanex16.f64(double %src0, double %src0, i32 4660, i32 49617, i1 false, i1 false) @@ -4929,90 +4799,50 @@ define amdgpu_kernel void @v_permlanex16_b32_vvv_f64(ptr addrspace(1) %out, doub ; GFX10-GISEL-NEXT: s_mov_b32 null, 0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; -; GFX11-SDAG-LABEL: v_permlanex16_b32_vvv_f64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX11-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s4, v1 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-SDAG-NEXT: v_permlanex16_b32 v0, v0, s4, s5 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_permlanex16_b32 v1, v1, s4, s5 -; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-SDAG-NEXT: s_endpgm -; -; GFX11-GISEL-LABEL: v_permlanex16_b32_vvv_f64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v1 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 -; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-GISEL-NEXT: s_endpgm -; -; GFX12-SDAG-LABEL: v_permlanex16_b32_vvv_f64: -; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX12-SDAG-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s4, v1 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, s3 -; GFX12-SDAG-NEXT: v_permlanex16_b32 v0, v0, s4, s5 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s4, s5 -; GFX12-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-SDAG-NEXT: s_endpgm +; GFX11-LABEL: v_permlanex16_b32_vvv_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX11-NEXT: v_bfe_u32 v0, v0, 10, 10 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readfirstlane_b32 s5, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_permlanex16_b32 v1, v1, s4, s5 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm ; -; GFX12-GISEL-LABEL: v_permlanex16_b32_vvv_f64: -; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0 -; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v1 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 -; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-GISEL-NEXT: s_endpgm +; GFX12-LABEL: v_permlanex16_b32_vvv_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX12-NEXT: v_bfe_u32 v0, v0, 10, 10 +; GFX12-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_readfirstlane_b32 s5, v0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 +; GFX12-NEXT: v_readfirstlane_b32 s4, v1 +; GFX12-NEXT: v_mov_b32_e32 v1, s3 +; GFX12-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_permlanex16_b32 v1, v1, s4, s5 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_endpgm ; ; GFX13-SDAG-LABEL: v_permlanex16_b32_vvv_f64: ; GFX13-SDAG: ; %bb.0: @@ -5036,16 +4866,15 @@ define amdgpu_kernel void @v_permlanex16_b32_vvv_f64(ptr addrspace(1) %out, doub ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v0 ; GFX13-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s4, v1 ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %tidx = call i32 @llvm.amdgcn.workitem.id.x() @@ -5393,86 +5222,48 @@ define amdgpu_kernel void @v_permlanex16_b32_vvs_f64(ptr addrspace(1) %out, doub ; GFX10-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34 ; GFX10-GISEL-NEXT: s_mov_b32 null, 0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s6 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s6 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s6 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s6 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; -; GFX11-SDAG-LABEL: v_permlanex16_b32_vvs_f64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_clause 0x1 -; GFX11-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-SDAG-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-SDAG-NEXT: v_permlanex16_b32 v1, v1, s5, s4 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-SDAG-NEXT: v_permlanex16_b32 v0, v0, s5, s4 -; GFX11-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-SDAG-NEXT: s_endpgm -; -; GFX11-GISEL-LABEL: v_permlanex16_b32_vvs_f64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_clause 0x1 -; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v0, 0x3ff, v0 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s5, s4 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s5, s4 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-GISEL-NEXT: s_endpgm -; -; GFX12-SDAG-LABEL: v_permlanex16_b32_vvs_f64: -; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_clause 0x1 -; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-SDAG-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2 -; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s5, s4 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-SDAG-NEXT: v_permlanex16_b32 v0, v0, s5, s4 -; GFX12-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-SDAG-NEXT: s_endpgm +; GFX11-LABEL: v_permlanex16_b32_vvs_f64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_load_b32 s4, s[4:5], 0x34 +; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readfirstlane_b32 s5, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_permlanex16_b32 v1, v1, s5, s4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_permlanex16_b32 v0, v0, s5, s4 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_endpgm ; -; GFX12-GISEL-LABEL: v_permlanex16_b32_vvs_f64: -; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_clause 0x1 -; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX12-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 -; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v0, 0x3ff, v0 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v0 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s3 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s5, s4 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s5, s4 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX12-GISEL-NEXT: s_endpgm +; GFX12-LABEL: v_permlanex16_b32_vvs_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_load_b32 s4, s[4:5], 0x34 +; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_readfirstlane_b32 s5, v0 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 +; GFX12-NEXT: v_permlanex16_b32 v1, v1, s5, s4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_permlanex16_b32 v0, v0, s5, s4 +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_endpgm ; ; GFX13-SDAG-LABEL: v_permlanex16_b32_vvs_f64: ; GFX13-SDAG: ; %bb.0: @@ -5497,15 +5288,14 @@ define amdgpu_kernel void @v_permlanex16_b32_vvs_f64(ptr addrspace(1) %out, doub ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s5, s4 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s5, s4 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s5, s4 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s5, s4 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %tidx = call i32 @llvm.amdgcn.workitem.id.x() @@ -5894,14 +5684,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vsv_f64(ptr addrspace(1) %out, doub ; GFX10-GISEL-NEXT: s_load_dword s6, s[4:5], 0x34 ; GFX10-GISEL-NEXT: s_mov_b32 null, 0 ; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s6, s4 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s6, s4 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s6, s4 +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s6, s4 ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -5928,15 +5716,14 @@ define amdgpu_kernel void @v_permlanex16_b32_vsv_f64(ptr addrspace(1) %out, doub ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 ; GFX11-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -5963,15 +5750,14 @@ define amdgpu_kernel void @v_permlanex16_b32_vsv_f64(ptr addrspace(1) %out, doub ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 ; GFX12-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -5998,15 +5784,14 @@ define amdgpu_kernel void @v_permlanex16_b32_vsv_f64(ptr addrspace(1) %out, doub ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: v_bfe_u32 v0, v0, 10, 10 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX13-GISEL-NEXT: v_readfirstlane_b32 s5, v0 ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 +; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %tidy = call i32 @llvm.amdgcn.workitem.id.y() @@ -6258,14 +6043,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_f64(ptr addrspace(1) %out, d ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s6, s7 op_sel:[1,0] -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s6, s7 op_sel:[1,0] +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s6, s7 op_sel:[1,0] +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s6, s7 op_sel:[1,0] ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -6288,13 +6071,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_f64(ptr addrspace(1) %out, d ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[1,0] -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[1,0] -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[1,0] +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[1,0] ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -6317,13 +6099,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_f64(ptr addrspace(1) %out, d ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[1,0] -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[1,0] -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[1,0] +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[1,0] ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -6347,12 +6128,11 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_f64(ptr addrspace(1) %out, d ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[1,0] -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[1,0] +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[1,0] +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[1,0] ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlanex16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 true, i1 false) @@ -6603,14 +6383,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_bc_f64(ptr addrspace(1) %out, d ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s6, s7 op_sel:[0,1] -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s6, s7 op_sel:[0,1] +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s6, s7 op_sel:[0,1] +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s6, s7 op_sel:[0,1] ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -6633,13 +6411,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_bc_f64(ptr addrspace(1) %out, d ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[0,1] -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[0,1] -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[0,1] +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[0,1] ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -6662,13 +6439,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_bc_f64(ptr addrspace(1) %out, d ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[0,1] -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[0,1] -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[0,1] +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[0,1] ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -6692,12 +6468,11 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_bc_f64(ptr addrspace(1) %out, d ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[0,1] -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[0,1] +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[0,1] +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[0,1] ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlanex16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 false, i1 true) @@ -6948,14 +6723,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_bc_f64(ptr addrspace(1) %out ; GFX10-GISEL-NEXT: s_clause 0x1 ; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GFX10-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v2, s6, s7 op_sel:[1,1] -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v3, s6, s7 op_sel:[1,1] +; GFX10-GISEL-NEXT: v_permlanex16_b32 v0, v0, s6, s7 op_sel:[1,1] +; GFX10-GISEL-NEXT: v_permlanex16_b32 v1, v1, s6, s7 op_sel:[1,1] ; GFX10-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-GISEL-NEXT: s_endpgm ; @@ -6978,13 +6751,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_bc_f64(ptr addrspace(1) %out ; GFX11-GISEL-NEXT: s_clause 0x1 ; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[1,1] -; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[1,1] -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[1,1] +; GFX11-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[1,1] ; GFX11-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-GISEL-NEXT: s_endpgm ; @@ -7007,13 +6779,12 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_bc_f64(ptr addrspace(1) %out ; GFX12-GISEL-NEXT: s_clause 0x1 ; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX12-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[1,1] -; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[1,1] -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[1,1] +; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[1,1] ; GFX12-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; @@ -7037,12 +6808,11 @@ define amdgpu_kernel void @v_permlanex16_b32_vss_fi_bc_f64(ptr addrspace(1) %out ; GFX13-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv ; GFX13-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv ; GFX13-GISEL-NEXT: s_wait_kmcnt 0x0 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s2 -; GFX13-GISEL-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v3, s3 -; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v2, s4, s5 op_sel:[1,1] -; GFX13-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v3, s4, s5 op_sel:[1,1] +; GFX13-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s2 +; GFX13-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX13-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX13-GISEL-NEXT: v_permlanex16_b32 v0, v0, s4, s5 op_sel:[1,1] +; GFX13-GISEL-NEXT: v_permlanex16_b32 v1, v1, s4, s5 op_sel:[1,1] ; GFX13-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX13-GISEL-NEXT: s_endpgm %v = call double @llvm.amdgcn.permlanex16.f64(double %src0, double %src0, i32 %src1, i32 %src2, i1 true, i1 true) diff --git a/llvm/test/CodeGen/AMDGPU/ucmp.ll b/llvm/test/CodeGen/AMDGPU/ucmp.ll index 2eef0cd806efb..398f25ac5d119 100644 --- a/llvm/test/CodeGen/AMDGPU/ucmp.ll +++ b/llvm/test/CodeGen/AMDGPU/ucmp.ll @@ -1118,19 +1118,22 @@ define <2 x i32> @ucmp_v2i16_uniform(<2 x i16> inreg %a, <2 x i16> inreg %b) { ; GFX12-GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GFX12-GISEL-NEXT: s_cmp_lt_u32 s0, s3 ; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0 +; GFX12-GISEL-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX12-GISEL-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_cmp_lt_u32 s2, s1 ; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0 -; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GFX12-GISEL-NEXT: s_cselect_b32 s2, 1, 0 ; GFX12-GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GFX12-GISEL-NEXT: s_cselect_b32 s3, 1, 0 ; GFX12-GISEL-NEXT: s_cmp_lg_u32 s0, 0 ; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0 +; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0 ; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0 -; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_sub_co_i32 s0, s2, s0 +; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: s_sub_co_i32 s1, s3, s1 ; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1