wip: yosys-synlig

Author: jwnrt

nix/sv2v.nix

@@ -10,13 +10,9 @@
   ...
 }: let
 
-  sv2v_local = import ./sv2v.nix {inherit inputs pkgs;};
-
-  ibex_syn_deps = [
-    sv2v_local.default
-  ] ++ (with pkgs; [
-    # haskellPackages.sv2v # broken
+  ibex_syn_deps = (with pkgs; [
     yosys
+    yosys-synlig
     openroad
   ]);
 
@@ -42,6 +38,7 @@
   ibex_syn_profile = ''
     export LR_SYNTH_CELL_LIBRARY_NAME=nangate
     export LR_SYNTH_CELL_LIBRARY_PATH=${nangate45}/lib/NangateOpenCellLibrary_typical.lib
+    export LR_SYNTH_SYNLIG_PLUGIN_PATH=${pkgs.yosys-synlig}/share/yosys/plugins/systemverilog.so
   '';
 
 in {

nix/syn.nix

@@ -24,7 +24,7 @@ module ibex_top import ibex_pkg::*; #(
   parameter bit                     RV32E                        = 1'b0,
   parameter rv32m_e                 RV32M                        = RV32MFast,
   parameter rv32b_e                 RV32B                        = RV32BNone,
-  parameter regfile_e               RegFile                      = RegFileFF,
+  parameter regfile_e               RegFile                      = RegFileLatch,
   parameter bit                     BranchTargetALU              = 1'b0,
   parameter bit                     WritebackStage               = 1'b0,
   parameter bit                     ICache                       = 1'b0,

rtl/ibex_top.sv

@@ -0,0 +1,16 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module prim_buf #(
+  parameter int Width = 1
+) (
+  input        [Width-1:0] in_i,
+  output logic [Width-1:0] out_o
+);
+
+  logic [Width-1:0] inv;
+  assign inv = ~in_i;
+  assign out_o = ~inv;
+
+endmodule

syn/rtl/prim_buf.sv

@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module prim_flop #(
+  parameter int               Width      = 1,
+  parameter logic [Width-1:0] ResetValue = 0
+) (
+  input                    clk_i,
+  input                    rst_ni,
+  input        [Width-1:0] d_i,
+  output logic [Width-1:0] q_o
+);
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      q_o <= ResetValue;
+    end else begin
+      q_o <= d_i;
+    end
+  end
+
+endmodule

syn/rtl/prim_flop.sv

@@ -28,10 +28,6 @@ fi
 #-------------------------------------------------------------------------
 source syn_setup.sh
 
-#-------------------------------------------------------------------------
-# use sv2v to convert all SystemVerilog files to Verilog
-#-------------------------------------------------------------------------
-
 LR_DEP_SOURCES=(
     "../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv"
     "../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv"
@@ -41,42 +37,6 @@ mkdir -p "$LR_SYNTH_OUT_DIR/generated"
 mkdir -p "$LR_SYNTH_OUT_DIR/log"
 mkdir -p "$LR_SYNTH_OUT_DIR/reports/timing"
 
-# Convert dependency sources
-for file in "${LR_DEP_SOURCES[@]}"; do
-    module=$(basename -s .sv "$file")
-
-    sv2v \
-        --define=SYNTHESIS --define=YOSYS \
-        -I../vendor/lowrisc_ip/ip/prim/rtl \
-        "$file" \
-        > "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
-done
-
-# Convert core sources
-for file in ../rtl/*.sv; do
-  module=$(basename -s .sv "$file")
-
-  # Skip packages
-  if echo "$module" | grep -q '_pkg$'; then
-      continue
-  fi
-
-  sv2v \
-    --define=SYNTHESIS --define=YOSYS \
-    ../rtl/*_pkg.sv \
-    ../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv \
-    ../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv \
-    -I../vendor/lowrisc_ip/ip/prim/rtl \
-    -I../vendor/lowrisc_ip/dv/sv/dv_utils \
-    "$file" \
-    > "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
-
-# Make sure auto-generated primitives are resolved to generic primitives
-# where available.
-  sed -i 's/prim_buf/prim_generic_buf/g'  "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
-  sed -i 's/prim_flop/prim_generic_flop/g' "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
-done
-
 # remove tracer (not needed for synthesis)
 rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_tracer.v
 
@@ -85,7 +45,7 @@ rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_tracer.v
 rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_register_file_ff.v
 rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_register_file_fpga.v
 
-yosys -c ./tcl/yosys_run_synth.tcl |& teelog syn || {
+yosys -m "$LR_SYNTH_SYNLIG_PLUGIN_PATH" -c ./tcl/yosys_run_synth.tcl |& teelog syn || {
     error "Failed to synthesize RTL with Yosys"
 }
 

syn/syn_yosys.sh

@@ -14,7 +14,44 @@ if { $lr_synth_timing_run } {
   write_sdc_out $lr_synth_sdc_file_in $lr_synth_sdc_file_out
 }
 
-yosys "read_verilog -defer -sv ./rtl/prim_clock_gating.v $lr_synth_out_dir/generated/*.v"
+yosys "read_systemverilog -defer \
+  -PSYNTHESIS=true \
+  -PYOSYS=true \
+  -I../vendor/lowrisc_ip/ip/prim/rtl/ \
+  -I../vendor/lowrisc_ip/dv/sv/dv_utils \
+  rtl/prim_clock_gating.v \
+  rtl/prim_buf.sv \
+  rtl/prim_flop.sv \
+  ../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv \
+  ../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv \
+  ../rtl/ibex_pkg.sv \
+  ../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv \
+  ../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv \
+  ../rtl/ibex_alu.sv \
+  ../rtl/ibex_branch_predict.sv \
+  ../rtl/ibex_compressed_decoder.sv \
+  ../rtl/ibex_controller.sv \
+  ../rtl/ibex_core.sv \
+  ../rtl/ibex_counter.sv \
+  ../rtl/ibex_cs_registers.sv \
+  ../rtl/ibex_csr.sv \
+  ../rtl/ibex_decoder.sv \
+  ../rtl/ibex_dummy_instr.sv \
+  ../rtl/ibex_ex_block.sv \
+  ../rtl/ibex_fetch_fifo.sv \
+  ../rtl/ibex_icache.sv \
+  ../rtl/ibex_id_stage.sv \
+  ../rtl/ibex_if_stage.sv \
+  ../rtl/ibex_load_store_unit.sv \
+  ../rtl/ibex_lockstep.sv \
+  ../rtl/ibex_multdiv_fast.sv \
+  ../rtl/ibex_multdiv_slow.sv \
+  ../rtl/ibex_pmp.sv \
+  ../rtl/ibex_prefetch_buffer.sv \
+  ../rtl/ibex_register_file_latch.sv \
+  ../rtl/ibex_top.sv \
+  ../rtl/ibex_wb_stage.sv"
+yosys "read_systemverilog -link"
 
 if { $lr_synth_ibex_branch_target_alu } {
   yosys "chparam -set BranchTargetALU 1 $lr_synth_top_module"