docs(notes): add 2025-03-24 CPU architecture overview

Author: lzwjava

notes/2025-03-24-cpu-en.md

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+---
+title: Central Processing Unit 
+lang: en
+layout: post
+audio: false
+translated: false
+generated: true
+---
+
+Here's a structured tutorial on the **Central Processing Unit (CPU)** based on **Computer Organization and Architecture (02318)**.  
+
+---
+
+# **Tutorial: Central Processing Unit (CPU)**
+## **1. Introduction to the CPU**
+The **Central Processing Unit (CPU)** is the brain of a computer, responsible for executing instructions through an organized set of components and operations. The main functions of the CPU include:  
+- Fetching instructions from memory  
+- Decoding instructions  
+- Executing operations through the **Arithmetic Logic Unit (ALU)**  
+- Managing data flow using **registers**  
+
+To understand the CPU, we need to break it down into its core components and execution cycle.
+
+---
+
+## **2. CPU Internal Structure**
+The CPU consists of several key components that work together to process instructions:  
+
+### **2.1 Registers**  
+Registers are **small, fast storage locations** inside the CPU used for temporary data storage and instruction execution. Key types of registers include:  
+1. **Program Counter (PC):** Holds the address of the next instruction.  
+2. **Instruction Register (IR):** Stores the current instruction being executed.  
+3. **Accumulator (ACC):** Stores results of arithmetic and logic operations.  
+4. **General-Purpose Registers:** Store intermediate data for quick access.  
+5. **Memory Address Register (MAR):** Holds memory addresses for data retrieval.  
+6. **Memory Data Register (MDR):** Stores data fetched from or sent to memory.  
+7. **Status Register (FLAGS):** Stores condition codes like zero flag, carry flag, etc.  
+
+### **2.2 Arithmetic Logic Unit (ALU)**  
+The ALU performs **arithmetic (addition, subtraction, multiplication, division)** and **logical (AND, OR, NOT, XOR) operations**. The ALU interacts with registers to process data.  
+
+### **2.3 Control Unit (CU)**  
+The Control Unit (CU) manages data flow inside the CPU. It **decodes** instructions, controls signal flow, and synchronizes execution using a system clock.  
+
+### **2.4 System Bus**  
+The CPU communicates with memory and input/output devices through the **system bus**, which consists of:  
+- **Data Bus:** Transfers actual data.  
+- **Address Bus:** Carries memory addresses.  
+- **Control Bus:** Sends control signals.  
+
+---
+
+## **3. The Instruction Cycle (Fetch-Decode-Execute)**
+The **Instruction Cycle** is the process by which the CPU executes instructions. It consists of three main stages:
+
+### **3.1 Fetch Stage**
+- The **Program Counter (PC)** contains the address of the next instruction.  
+- The CPU fetches the instruction from memory using the **MAR** and **MDR**.  
+- The fetched instruction is stored in the **Instruction Register (IR)**.  
+
+### **3.2 Decode Stage**
+- The **Control Unit (CU)** interprets the instruction in the **IR**.  
+- The CU identifies the required **operation (opcode)** and **operands**.  
+- If needed, additional data is fetched from memory.  
+
+### **3.3 Execute Stage**
+- The **ALU** performs the required arithmetic/logical operations.  
+- The result is stored in a register or memory.  
+- The **Program Counter (PC)** is updated to point to the next instruction.  
+
+**Example: Execution of an ADD instruction**  
+1. **Fetch:** CPU fetches the instruction `ADD R1, R2`.  
+2. **Decode:** CU identifies `ADD` as an arithmetic operation and operands as `R1` and `R2`.  
+3. **Execute:** ALU performs `R1 = R1 + R2`, storing the result in `R1`.  
+
+---
+
+## **4. Execution Mechanisms**
+CPU execution depends on several factors, including:  
+
+### **4.1 Pipelining**
+To improve performance, modern CPUs use **pipelining**, where multiple instructions are processed simultaneously in different stages (fetch, decode, execute).  
+
+Example of a 3-stage pipeline:  
+| Cycle | Fetch  | Decode  | Execute |
+|--------|--------|---------|---------|
+| 1      | I1    |         |         |
+| 2      | I2    | I1      |         |
+| 3      | I3    | I2      | I1      |
+| 4      | I4    | I3      | I2      |
+| 5      | I5    | I4      | I3      |
+
+This reduces instruction processing time and increases throughput.  
+
+### **4.2 Parallel Processing**
+- **Superscalar Execution:** Multiple execution units process different instructions simultaneously.  
+- **Multicore CPUs:** Modern processors have multiple cores that execute instructions in parallel.  
+
+### **4.3 Interrupt Handling**
+- CPUs use **interrupts** to respond to external events (e.g., I/O requests).  
+- The CPU saves its current state, executes the interrupt service routine (ISR), and resumes normal execution.  
+
+---
+
+## **5. Summary**
+- The CPU consists of **registers, ALU, control unit, and buses**.  
+- The **Fetch-Decode-Execute** cycle governs instruction execution.  
+- Performance enhancements include **pipelining, parallelism, and interrupts**.  
+
+By mastering these concepts, you gain a solid understanding of how the CPU operates in a **computer organization and architecture** course. 🚀  
+
+Would you like to see specific examples or practice problems? 😊