Pipeline PhasedAccu for n>8 and allow non-log(2) values of n when n>8

Author: fevi

misoc/cores/duc.py

@@ -205,29 +205,21 @@ def __init__(self, width, constants):
 
         ###
 
+        self.latency = 2 if n > 8 else 0
+
         # TODO: improve MCM
-        assert n <= 9
+        assert n <= 16
         assert range(n) == constants
 
-        ctx = self.comb
-        if n > 0:
-            ctx += o[0].eq(0)
-        if n > 1:
-            ctx += o[1].eq(i)
-        if n > 2:
-            ctx += o[2].eq(i << 1)
-        if n > 3:
-            ctx += o[3].eq(i + (i << 1))
-        if n > 4:
-            ctx += o[4].eq(i << 2)
-        if n > 5:
-            ctx += o[5].eq(i + (i << 2))
-        if n > 6:
-            ctx += o[6].eq(o[3] << 1)
-        if n > 7:
-            ctx += o[7].eq((i << 3) - i)
-        if n > 8:
-            ctx += o[8].eq(i << 3)
+        ctx = self.sync if n > 8 else self.comb
+
+        # manually generated multiplication for small numbers,
+        # if you use "x*y" Vivado will use a DSP48E1 instead
+        for x in range(n):
+            ctx += o[x].eq((x & 0x1) * i + 
+                           ((x & 0x2) >> 1) * (i << 1) +
+                           ((x & 0x4) >> 2) * (i << 2) +
+                           ((x & 0x8) >> 3) * (i << 3))
 
 
 class PhasedAccu(Module):
@@ -247,26 +239,53 @@ def __init__(self, n, fwidth, pwidth):
         self.z = [Signal(pwidth, reset_less=True)
                   for _ in range(n)]
 
-        self.submodules.mcm = MCM(fwidth, range(n))
+        self.submodules.mcm = MCM(fwidth, range(n+1))
         # reset by clr
         qa = Signal(fwidth, reset_less=True)
         qb = Signal(fwidth, reset_less=True)
         clr_d = Signal(reset_less=True)
-        self.sync += [
-            clr_d.eq(self.clr),
-            qa.eq(qa + (self.f << log2_int(n))),
-            self.mcm.i.eq(self.f),
-            If(self.clr | clr_d,
-                qa.eq(0),
-            ),
-            If(clr_d,
-                self.mcm.i.eq(0),
-            ),
-            qb.eq(qa + (self.p << fwidth - pwidth)),
-            [z.eq((qb + oi)[fwidth - pwidth:])
-                for oi, z in zip(self.mcm.o, self.z)]
-        ]
 
+        if n > 8:
+            # additional pipelining for n > 8
+            clr_d2 = Signal(reset_less=True)
+            mcm_o_d = [Signal(fwidth, reset_less=True) for _ in range(n)]
+            self.sync += [
+                # Delay signals to match now increased mcm latency
+                clr_d.eq(self.clr),
+                clr_d2.eq(clr_d),
+                [mcm_o_d[i].eq(self.mcm.o[i]) for i in range(n)],
+
+                qa.eq(qa + self.mcm.o[n]),
+                self.mcm.i.eq(self.f),
+                If(clr_d | clr_d2,
+                    qa.eq(0),
+                ),
+                If(clr_d2,
+                    self.mcm.i.eq(0),
+                ),
+                qb.eq(qa + (self.p << (fwidth - pwidth))),
+
+                # Use delayed signals in the final phase calculation
+                [z.eq((qb + mcm_o_d[i])[fwidth - pwidth:])
+            for i, z in enumerate(self.z)]
+            ]
+        else:
+            self.sync += [
+                clr_d.eq(self.clr),
+                qa.eq(qa + (self.f << log2_int(n))),
+                self.mcm.i.eq(self.f),
+                If(self.clr | clr_d,
+                    qa.eq(0),
+                ),
+                If(clr_d,
+                    self.mcm.i.eq(0),
+                ),
+                qb.eq(qa + (self.p << (fwidth - pwidth))),
+
+                # Use non-delayed signals in the final phase calculation
+                [z.eq((qb + oi)[fwidth - pwidth:])
+                    for oi, z in zip(self.mcm.o, self.z)]
+            ]
 
 class PhaseModulator(Module):
     """Complex phase modulator/shifter.

misoc/test/test_duc.py

@@ -50,6 +50,7 @@ def test_init(self):
 
     def test_seq(self):
         def gen():
+            # latency = 2
             yield self.dut.clr.eq(0)
             yield self.dut.p.eq(0x01)
             yield
@@ -104,6 +105,97 @@ def gen():
             self.assertEqual((yield self.dut.z[1]), 0xa1)
         run_simulation(self.dut, gen())
 
+class TestPhasedAccuNonLog(unittest.TestCase):
+    def setUp(self):
+        self.dut = duc.PhasedAccu(n=12, fwidth=32, pwidth=16)
+
+    def test_init(self):
+        self.assertEqual(len(self.dut.f), 32)
+        self.assertEqual(len(self.dut.p), 16)
+        self.assertEqual(len(self.dut.z), 12)
+        self.assertEqual(len(self.dut.z[0]), 16)
+
+    def test_seq(self):
+        def gen():
+            # latency = 4
+            n=12
+            yield self.dut.clr.eq(0)
+            yield self.dut.p.eq(0x01)
+            yield
+            yield
+            yield
+            yield
+            # check phase offset with f=0
+            self.assertEqual((yield self.dut.z[0]), 0x01)
+            self.assertEqual((yield self.dut.z[1]), 0x01)
+            yield self.dut.f.eq(0x10 << 16)
+            yield
+            yield
+            yield
+            yield
+            yield
+            # check first cycle f increments
+            for i in range(n):
+                expected_value = (i << 4) | 0x01
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield
+            # second cycle f increments
+            for i in range(n):
+                expected_value += 0x10
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield self.dut.clr.eq(1)
+            yield
+            for i in range(n):
+                expected_value += 0x10
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield
+            for i in range(n):
+                expected_value += 0x10
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield self.dut.clr.eq(0)
+            yield
+            for i in range(n):
+                expected_value += 0x10
+            yield
+            for i in range(n):
+                expected_value += 0x10
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield
+            # first clr cycle
+            for i in range(n):
+                expected_value = (i << 4) | 0x01
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield
+            # second clr cycle
+            for i in range(n):
+                expected_value = (i << 4) | 0x01
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield self.dut.f.eq(0x20 << 16)
+            yield
+            yield
+            yield
+            # first cycle after clr with old f
+            for i in range(n):
+                expected_value = (i << 4) | 0x01
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield
+            # second cycle with old f
+            for i in range(n):
+                expected_value += 0x10
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+            yield
+            # cycle with one old and one new
+            expected_value += 0x10
+            for i in range(n):
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+                expected_value += 0x20
+            yield
+            # cycle with only new increments
+            expected_value -= 0x20
+            for i in range(n):
+                expected_value += 0x20
+                self.assertEqual((yield self.dut.z[i]), expected_value)
+        run_simulation(self.dut, gen())
 
 class TestMul(unittest.TestCase):
     def setUp(self):