From 97c95cbf20fb050dc286bb9b02496fa98af5b73c Mon Sep 17 00:00:00 2001 From: Vladimir Radosavljevic Date: Fri, 3 Oct 2025 16:53:44 +0200 Subject: [PATCH] [EVM][CVP] Disable narrowing of div and rem instructions This is not profitable for us, since it will introduce more instructions. Signed-off-by: Vladimir Radosavljevic --- .../Transforms/Scalar/CorrelatedValuePropagation.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp index b3d439a6f113..794e279501b8 100644 --- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp +++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp @@ -752,6 +752,12 @@ static bool narrowSDivOrSRem(BinaryOperator *Instr, const ConstantRange &LCR, assert(Instr->getOpcode() == Instruction::SDiv || Instr->getOpcode() == Instruction::SRem); + // EVM local begin + Triple TT(Instr->getFunction()->getParent()->getTargetTriple()); + if (TT.isEVM()) + return false; + // EVM local end + // Find the smallest power of two bitwidth that's sufficient to hold Instr's // operands. unsigned OrigWidth = Instr->getType()->getScalarSizeInBits(); @@ -885,6 +891,12 @@ static bool narrowUDivOrURem(BinaryOperator *Instr, const ConstantRange &XCR, assert(Instr->getOpcode() == Instruction::UDiv || Instr->getOpcode() == Instruction::URem); + // EVM local begin + Triple TT(Instr->getFunction()->getParent()->getTargetTriple()); + if (TT.isEVM()) + return false; + // EVM local end + // Find the smallest power of two bitwidth that's sufficient to hold Instr's // operands.