@@ -54,6 +54,15 @@ def childImage(self, ci):
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self .image .child .image_file = ci
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class MemBus (SystemXBar ):
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+ # pass
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+ badaddr_responder = BadAddr ()
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+ default = Self .badaddr_responder .pio
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+
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+ class CoherentSystemBus (SystemXBar ):
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+ badaddr_responder = BadAddr ()
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+ default = Self .badaddr_responder .pio
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+
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+ class NonCoherentSystemBus (IOXBar ):
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badaddr_responder = BadAddr ()
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default = Self .badaddr_responder .pio
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@@ -64,7 +73,7 @@ def fillInCmdline(mdesc, template, **kwargs):
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kwargs .setdefault ('script' , mdesc .script ())
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return template % kwargs
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- def makeLinuxAlphaSystem (mem_mode , mdesc = None , ruby = False , cmdline = None ):
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+ def makeLinuxAlphaSystem (mem_mode , options , mdesc = None , cmdline = None ):
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class BaseTsunami (Tsunami ):
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ethernet = NSGigE (pci_bus = 0 , pci_dev = 1 , pci_func = 0 )
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ide = IdeController (disks = [Parent .disk0 , Parent .disk2 ],
@@ -88,7 +97,13 @@ class BaseTsunami(Tsunami):
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self .tsunami .ethernet .pio = self .iobus .master
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self .tsunami .ethernet .config = self .iobus .master
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- self .systembus = IOXBar ()
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+ self .systembus = MemBus ()
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+ # self.systembus = IOXBar()
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+
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+ # if options.caches or options.l2cache:
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+ # self.systembus = CoherentSystemBus()
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+ # else:
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+ # self.systembus = NonCoherentSystemBus()
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# By default the bridge responds to all addresses above the I/O
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# base address (including the PCI config space)
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