elevator.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Web Edition
# Date created = 23:52:19  October 14, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		elevator_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7064SLC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY elevator
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:52:19  OCTOBER 14, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VHDL_FILE regist.vhd
set_global_assignment -name VHDL_FILE counter.vhd
set_global_assignment -name VHDL_FILE edge_det.vhd
set_global_assignment -name VHDL_FILE elevator.vhd
set_global_assignment -name VHDL_FILE encoder.vhd
set_global_assignment -name VHDL_FILE timer.vhd
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_WAVEFORM_FILE elevator_test.vwf
set_global_assignment -name END_TIME "1000 ns"
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE elevator_test.vwf
set_global_assignment -name MISC_FILE "E:/ALTERA_PROJECTS/VHDL-LAB2/elevator.dpf"