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Working Glib with Stack Counter
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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/.DS_Store

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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/_xmsgs/cg.xmsgs

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="sim" num="172" delta="old" >Generating IP...
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</msg>
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<msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">structural</arg>&gt;.
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</msg>
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<msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">structural</arg>&gt;.
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</msg>
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<msg type="warning" file="sim" num="89" delta="new" >A core named &lt;<arg fmt="%s" index="1">chipscope_ila</arg>&gt; already exists in the output directory. Output products for this core may be overwritten.
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</msg>
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<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
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</msg>
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<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
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</msg>
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</messages>
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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/_xmsgs/pn_parser.xmsgs

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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated -->
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<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- changes made to this file may result in unpredictable -->
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<!-- behavior or data corruption. It is strongly advised that -->
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<!-- users do not edit the contents of this file. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<messages>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/pix_emul_glib3/prj_iphc_strasbourg/glib_v3/GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_ila.vhd&quot; into library work</arg>
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</msg>
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</messages>
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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/_xmsgs/xst.xmsgs

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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.asy

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Version 4
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SymbolType BLOCK
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TEXT 32 32 LEFT 4 chipscope_icon
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RECTANGLE Normal 32 32 544 864
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LINE Wide 576 112 544 112
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PIN 576 112 RIGHT 36
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PINATTR PinName control0[35:0]
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PINATTR Polarity BOTH
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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.constraints/chipscope_icon.ucf

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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
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TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
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#Update Constraints
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NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
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NET "U0/iSHIFT_OUT" TIG ;
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TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
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TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
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TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
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TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.constraints/chipscope_icon.xdc

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# icon XDC
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create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
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create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
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set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
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set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.gise

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chipscope_icon.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_ASY" xil_pn:name="chipscope_icon.asy" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_VHO" xil_pn:name="chipscope_icon.vho" xil_pn:origination="imported"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
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</generated_project>

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.ncf

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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.ngc

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‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.sym

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<?xml version="1.0" encoding="UTF-8"?>
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<symbol version="7" name="chipscope_icon">
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<symboltype>BLOCK</symboltype>
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<timestamp>2015-10-2T16:30:10</timestamp>
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<pin polarity="Output" x="576" y="112" name="control0[35:0]" />
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<graph>
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<text style="fontsize:40;fontname:Arial" x="32" y="32">chipscope_icon</text>
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<rect width="512" x="32" y="32" height="832" />
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<line x2="544" y1="112" y2="112" style="linewidth:W" x1="576" />
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<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="112" type="pin control0[35:0]" />
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</graph>
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</symbol>

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.ucf

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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
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TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
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#Update Constraints
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NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
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NET "U0/iSHIFT_OUT" TIG ;
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TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
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TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
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TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
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TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.vhd

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-------------------------------------------------------------------------------
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-- Copyright (c) 2015 Xilinx, Inc.
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-- All Rights Reserved
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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 14.7
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-- \ \ Application: XILINX CORE Generator
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-- / / Filename : chipscope_icon.vhd
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-- /___/ /\ Timestamp : Fri Oct 02 11:30:10 Central Daylight Time 2015
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-- \ \ / \
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-- \___\/\___\
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--
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-- Design Name: VHDL Synthesis Wrapper
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-------------------------------------------------------------------------------
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-- This wrapper is used to integrate with Project Navigator and PlanAhead
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY chipscope_icon IS
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port (
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CONTROL0: inout std_logic_vector(35 downto 0));
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END chipscope_icon;
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ARCHITECTURE chipscope_icon_a OF chipscope_icon IS
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BEGIN
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END chipscope_icon_a;

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.vho

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-------------------------------------------------------------------------------
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-- Copyright (c) 2015 Xilinx, Inc.
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-- All Rights Reserved
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-------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 14.7
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-- \ \ Application: Xilinx CORE Generator
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-- / / Filename : chipscope_icon.vho
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-- /___/ /\ Timestamp : Fri Oct 02 11:30:10 Central Daylight Time 2015
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-- \ \ / \
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-- \___\/\___\
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--
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-- Design Name: ISE Instantiation template
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-- Component Identifier: xilinx.com:ip:chipscope_icon:1.06.a
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-------------------------------------------------------------------------------
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-- The following code must appear in the VHDL architecture header:
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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component chipscope_icon
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PORT (
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CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
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end component;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : chipscope_icon
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port map (
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CONTROL0 => CONTROL0);
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-- INST_TAG_END ------ End INSTANTIATION Template ------------

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.xco

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##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Fri Oct 02 16:29:18 2015
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6vlx130t
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SET devicefamily = virtex6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
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# END Select
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# BEGIN Parameters
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CSET component_name=chipscope_icon
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CSET constraint_type=external
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CSET enable_jtag_bufg=true
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CSET example_design=false
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CSET number_control_ports=1
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CSET use_ext_bscan=false
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CSET use_softbscan=false
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CSET use_unused_bscan=false
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CSET user_scan_chain=USER1
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2013-10-13T14:12:40Z
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# END Extra information
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GENERATE
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# CRC: ba28dc8f

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.xdc

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# icon XDC
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create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
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create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
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set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
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set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
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set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon.xise

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="chipscope_icon.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|chipscope_icon|chipscope_icon_a" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="chipscope_icon.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chipscope_icon" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-10-02T11:30:22" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="78E3AD2F47E34B6EA826ABCBA2DA73E9" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings/>
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<libraries/>
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<autoManagedFiles>
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<!-- The following files are identified by `include statements in verilog -->
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<!-- source files and are automatically managed by Project Navigator. -->
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<!-- -->
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<!-- Do not hand-edit this section, as it will be overwritten when the -->
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<!-- project is analyzed based on files automatically identified as -->
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<!-- include files. -->
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</autoManagedFiles>
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</project>

‎GLIB-master/amc_glib/trunk/glib_v3/fw/fpga/prj/glib_fw/ipcore_dir/chipscope_icon_flist.txt

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# Output products list for <chipscope_icon>
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_xmsgs\pn_parser.xmsgs
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chipscope_icon.asy
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chipscope_icon.constraints\chipscope_icon.ucf
5+
chipscope_icon.constraints\chipscope_icon.xdc
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chipscope_icon.gise
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chipscope_icon.ngc
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chipscope_icon.sym
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chipscope_icon.ucf
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chipscope_icon.vhd
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chipscope_icon.vho
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chipscope_icon.xco
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chipscope_icon.xdc
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chipscope_icon.xise
15+
chipscope_icon_flist.txt
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chipscope_icon_readme.txt
17+
chipscope_icon_xmdf.tcl

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