diff --git a/gecko/CMakeLists.txt b/gecko/CMakeLists.txt
index 57b384a40..d04c27d2d 100644
--- a/gecko/CMakeLists.txt
+++ b/gecko/CMakeLists.txt
@@ -46,6 +46,7 @@ zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32WG Device/SiliconLabs/EFM32WG/So
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32BG13P Device/SiliconLabs/EFR32BG13P/Source/system_efr32bg13p.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG1P Device/SiliconLabs/EFR32FG1P/Source/system_efr32fg1p.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32HG Device/SiliconLabs/EFM32HG/Source/system_efm32hg.c)
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32MG1P Device/SiliconLabs/EFR32MG1P/Source/system_efr32mg1p.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32MG12P Device/SiliconLabs/EFR32MG12P/Source/system_efr32mg12p.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32PG12B Device/SiliconLabs/EFM32PG12B/Source/system_efm32pg12b.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32GG11B Device/SiliconLabs/EFM32GG11B/Source/system_efm32gg11b.c)
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p131f256gm48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p131f256gm48.h
new file mode 100644
index 000000000..551491f44
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p131f256gm48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P131F256GM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P131F256GM48_H
+#define EFR32MG1P131F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48 EFR32MG1P131F256GM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P131F256GM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P131F256GM48)
+#define EFR32MG1P131F256GM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P131F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P131F256GM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P131F256GM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P131F256GM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P131F256GM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P131F256GM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P131F256GM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P131F256GM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P131F256GM48_UNLOCK */
+
+/** @} End of group EFR32MG1P131F256GM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P131F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P131F256GM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gj43.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gj43.h
new file mode 100644
index 000000000..1358c33f1
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gj43.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P132F256GJ43
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P132F256GJ43_H
+#define EFR32MG1P132F256GJ43_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43 EFR32MG1P132F256GJ43
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P132F256GJ43_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P132F256GJ43)
+#define EFR32MG1P132F256GJ43 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P132F256GJ43" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P132F256GJ43 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P132F256GJ43_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P132F256GJ43_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P132F256GJ43_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P132F256GJ43_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P132F256GJ43_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GJ43_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P132F256GJ43_UNLOCK */
+
+/** @} End of group EFR32MG1P132F256GJ43_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P132F256GJ43 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P132F256GJ43_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gm32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gm32.h
new file mode 100644
index 000000000..43d6a666f
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gm32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P132F256GM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P132F256GM32_H
+#define EFR32MG1P132F256GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32 EFR32MG1P132F256GM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P132F256GM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P132F256GM32)
+#define EFR32MG1P132F256GM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P132F256GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P132F256GM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P132F256GM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P132F256GM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P132F256GM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P132F256GM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P132F256GM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P132F256GM32_UNLOCK */
+
+/** @} End of group EFR32MG1P132F256GM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P132F256GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P132F256GM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gm48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gm48.h
new file mode 100644
index 000000000..4271a8eea
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256gm48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P132F256GM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P132F256GM48_H
+#define EFR32MG1P132F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48 EFR32MG1P132F256GM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P132F256GM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P132F256GM48)
+#define EFR32MG1P132F256GM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P132F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P132F256GM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P132F256GM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P132F256GM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P132F256GM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P132F256GM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P132F256GM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256GM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P132F256GM48_UNLOCK */
+
+/** @} End of group EFR32MG1P132F256GM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P132F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P132F256GM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256im32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256im32.h
new file mode 100644
index 000000000..72fb6426c
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256im32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P132F256IM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P132F256IM32_H
+#define EFR32MG1P132F256IM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32 EFR32MG1P132F256IM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P132F256IM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P132F256IM32)
+#define EFR32MG1P132F256IM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P132F256IM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P132F256IM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P132F256IM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P132F256IM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P132F256IM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P132F256IM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P132F256IM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P132F256IM32_UNLOCK */
+
+/** @} End of group EFR32MG1P132F256IM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P132F256IM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P132F256IM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256im48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256im48.h
new file mode 100644
index 000000000..b77e8db6a
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p132f256im48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P132F256IM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P132F256IM48_H
+#define EFR32MG1P132F256IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48 EFR32MG1P132F256IM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P132F256IM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P132F256IM48)
+#define EFR32MG1P132F256IM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P132F256IM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P132F256IM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P132F256IM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P132F256IM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P132F256IM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P132F256IM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P132F256IM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P132F256IM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P132F256IM48_UNLOCK */
+
+/** @} End of group EFR32MG1P132F256IM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P132F256IM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P132F256IM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p133f256gm48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p133f256gm48.h
new file mode 100644
index 000000000..f825c45bd
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p133f256gm48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P133F256GM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P133F256GM48_H
+#define EFR32MG1P133F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48 EFR32MG1P133F256GM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P133F256GM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P133F256GM48)
+#define EFR32MG1P133F256GM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P133F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P133F256GM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P133F256GM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P133F256GM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P133F256GM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P133F256GM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P133F256GM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P133F256GM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P133F256GM48_UNLOCK */
+
+/** @} End of group EFR32MG1P133F256GM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P133F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P133F256GM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p231f256gm48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p231f256gm48.h
new file mode 100644
index 000000000..3915983ac
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p231f256gm48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P231F256GM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P231F256GM48_H
+#define EFR32MG1P231F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48 EFR32MG1P231F256GM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P231F256GM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P231F256GM48)
+#define EFR32MG1P231F256GM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P231F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P231F256GM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P231F256GM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P231F256GM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P231F256GM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P231F256GM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P231F256GM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P231F256GM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P231F256GM48_UNLOCK */
+
+/** @} End of group EFR32MG1P231F256GM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P231F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P231F256GM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gj43.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gj43.h
new file mode 100644
index 000000000..62d38db07
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gj43.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P232F256GJ43
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P232F256GJ43_H
+#define EFR32MG1P232F256GJ43_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43 EFR32MG1P232F256GJ43
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P232F256GJ43_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P232F256GJ43)
+#define EFR32MG1P232F256GJ43 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P232F256GJ43" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P232F256GJ43 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P232F256GJ43_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P232F256GJ43_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P232F256GJ43_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P232F256GJ43_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P232F256GJ43_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GJ43_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P232F256GJ43_UNLOCK */
+
+/** @} End of group EFR32MG1P232F256GJ43_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P232F256GJ43 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P232F256GJ43_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gm32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gm32.h
new file mode 100644
index 000000000..fc49873cb
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gm32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P232F256GM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P232F256GM32_H
+#define EFR32MG1P232F256GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32 EFR32MG1P232F256GM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P232F256GM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P232F256GM32)
+#define EFR32MG1P232F256GM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P232F256GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P232F256GM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P232F256GM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P232F256GM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P232F256GM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P232F256GM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P232F256GM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P232F256GM32_UNLOCK */
+
+/** @} End of group EFR32MG1P232F256GM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P232F256GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P232F256GM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gm48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gm48.h
new file mode 100644
index 000000000..979aa819b
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256gm48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P232F256GM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P232F256GM48_H
+#define EFR32MG1P232F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48 EFR32MG1P232F256GM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P232F256GM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P232F256GM48)
+#define EFR32MG1P232F256GM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P232F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P232F256GM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P232F256GM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P232F256GM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P232F256GM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P232F256GM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P232F256GM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256GM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P232F256GM48_UNLOCK */
+
+/** @} End of group EFR32MG1P232F256GM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P232F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P232F256GM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256im32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256im32.h
new file mode 100644
index 000000000..f28403f70
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256im32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P232F256IM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P232F256IM32_H
+#define EFR32MG1P232F256IM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32 EFR32MG1P232F256IM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P232F256IM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P232F256IM32)
+#define EFR32MG1P232F256IM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P232F256IM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P232F256IM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P232F256IM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P232F256IM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P232F256IM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P232F256IM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P232F256IM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P232F256IM32_UNLOCK */
+
+/** @} End of group EFR32MG1P232F256IM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P232F256IM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P232F256IM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256im48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256im48.h
new file mode 100644
index 000000000..df51818d4
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p232f256im48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P232F256IM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P232F256IM48_H
+#define EFR32MG1P232F256IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48 EFR32MG1P232F256IM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P232F256IM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P232F256IM48)
+#define EFR32MG1P232F256IM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P232F256IM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P232F256IM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P232F256IM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P232F256IM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P232F256IM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P232F256IM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P232F256IM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P232F256IM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P232F256IM48_UNLOCK */
+
+/** @} End of group EFR32MG1P232F256IM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P232F256IM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P232F256IM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p233f256gm48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p233f256gm48.h
new file mode 100644
index 000000000..dd26da3b6
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p233f256gm48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P233F256GM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P233F256GM48_H
+#define EFR32MG1P233F256GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48 EFR32MG1P233F256GM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P233F256GM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P233F256GM48)
+#define EFR32MG1P233F256GM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P233F256GM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P233F256GM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P233F256GM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P233F256GM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P233F256GM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P233F256GM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P233F256GM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256GM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P233F256GM48_UNLOCK */
+
+/** @} End of group EFR32MG1P233F256GM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P233F256GM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P233F256GM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p233f256im48.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p233f256im48.h
new file mode 100644
index 000000000..4d7b2e9b7
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p233f256im48.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P233F256IM48
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P233F256IM48_H
+#define EFR32MG1P233F256IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48 EFR32MG1P233F256IM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P233F256IM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P233F256IM48)
+#define EFR32MG1P233F256IM48 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P233F256IM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P233F256IM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P233F256IM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P233F256IM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P233F256IM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P233F256IM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P233F256IM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P233F256IM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P233F256IM48_UNLOCK */
+
+/** @} End of group EFR32MG1P233F256IM48_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P233F256IM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P233F256IM48_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p632f256gm32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p632f256gm32.h
new file mode 100644
index 000000000..bb2875b68
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p632f256gm32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P632F256GM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P632F256GM32_H
+#define EFR32MG1P632F256GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32 EFR32MG1P632F256GM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P632F256GM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P632F256GM32)
+#define EFR32MG1P632F256GM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P632F256GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P632F256GM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P632F256GM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P632F256GM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P632F256GM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P632F256GM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P632F256GM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256GM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P632F256GM32_UNLOCK */
+
+/** @} End of group EFR32MG1P632F256GM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P632F256GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P632F256GM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p632f256im32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p632f256im32.h
new file mode 100644
index 000000000..726742120
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p632f256im32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P632F256IM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P632F256IM32_H
+#define EFR32MG1P632F256IM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32 EFR32MG1P632F256IM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P632F256IM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P632F256IM32)
+#define EFR32MG1P632F256IM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P632F256IM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P632F256IM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P632F256IM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P632F256IM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P632F256IM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P632F256IM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P632F256IM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P632F256IM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P632F256IM32_UNLOCK */
+
+/** @} End of group EFR32MG1P632F256IM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P632F256IM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P632F256IM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p732f256gm32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p732f256gm32.h
new file mode 100644
index 000000000..dd470699e
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p732f256gm32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P732F256GM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P732F256GM32_H
+#define EFR32MG1P732F256GM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32 EFR32MG1P732F256GM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P732F256GM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P732F256GM32)
+#define EFR32MG1P732F256GM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P732F256GM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P732F256GM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P732F256GM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P732F256GM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P732F256GM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P732F256GM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P732F256GM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256GM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P732F256GM32_UNLOCK */
+
+/** @} End of group EFR32MG1P732F256GM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P732F256GM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P732F256GM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p732f256im32.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p732f256im32.h
new file mode 100644
index 000000000..74bcb6777
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p732f256im32.h
@@ -0,0 +1,447 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG1P732F256IM32
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32MG1P732F256IM32_H
+#define EFR32MG1P732F256IM32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32 EFR32MG1P732F256IM32
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */
+ MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */
+ MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */
+ CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */
+ LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */
+} IRQn_Type;
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG1P732F256IM32_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG1P732F256IM32)
+#define EFR32MG1P732F256IM32 1 /**< MIGHTY Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG1P732F256IM32" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */
+#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */
+#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */
+#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */
+#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */
+#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */
+#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */
+#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */
+#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */
+#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */
+#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */
+#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */
+#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */
+#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */
+#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32MG1P732F256IM32 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 72U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 61U
+
+/* Part number capabilities */
+
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 2 /**< 2 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 1 /**< 1 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 1 /**< 1 WDOGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 1 /**< 1 CRYPTO available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32mg1p.h" /* System Header File */
+
+/** @} End of group EFR32MG1P732F256IM32_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32mg1p_msc.h"
+#include "efr32mg1p_emu.h"
+#include "efr32mg1p_rmu.h"
+#include "efr32mg1p_cmu.h"
+#include "efr32mg1p_crypto.h"
+#include "efr32mg1p_gpio_p.h"
+#include "efr32mg1p_gpio.h"
+#include "efr32mg1p_prs_ch.h"
+#include "efr32mg1p_prs.h"
+#include "efr32mg1p_ldma_ch.h"
+#include "efr32mg1p_ldma.h"
+#include "efr32mg1p_fpueh.h"
+#include "efr32mg1p_gpcrc.h"
+#include "efr32mg1p_timer_cc.h"
+#include "efr32mg1p_timer.h"
+#include "efr32mg1p_usart.h"
+#include "efr32mg1p_leuart.h"
+#include "efr32mg1p_letimer.h"
+#include "efr32mg1p_cryotimer.h"
+#include "efr32mg1p_pcnt.h"
+#include "efr32mg1p_i2c.h"
+#include "efr32mg1p_adc.h"
+#include "efr32mg1p_acmp.h"
+#include "efr32mg1p_idac.h"
+#include "efr32mg1p_rtcc_cc.h"
+#include "efr32mg1p_rtcc_ret.h"
+#include "efr32mg1p_rtcc.h"
+#include "efr32mg1p_wdog_pch.h"
+#include "efr32mg1p_wdog.h"
+#include "efr32mg1p_dma_descriptor.h"
+#include "efr32mg1p_devinfo.h"
+#include "efr32mg1p_romtable.h"
+
+/** @} End of group EFR32MG1P732F256IM32_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32MG1P732F256IM32_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32MG1P732F256IM32_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+
+/** @} End of group EFR32MG1P732F256IM32_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32mg1p_prs_signals.h"
+#include "efr32mg1p_dmareq.h"
+
+/***************************************************************************//**
+ * @defgroup EFR32MG1P732F256IM32_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32MG1P732F256IM32_UNLOCK */
+
+/** @} End of group EFR32MG1P732F256IM32_BitFields */
+
+#include "efr32mg1p_af_ports.h"
+#include "efr32mg1p_af_pins.h"
+
+/***************************************************************************//**
+ * @brief Set the value of a bit field within a register.
+ *
+ * @param REG
+ * The register to update
+ * @param MASK
+ * The mask for the bit field to update
+ * @param VALUE
+ * The value to write to the bit field
+ * @param OFFSET
+ * The number of bits that the field is offset within the register.
+ * 0 (zero) means LSB.
+ ******************************************************************************/
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
+
+/** @} End of group EFR32MG1P732F256IM32 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* EFR32MG1P732F256IM32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_acmp.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_acmp.h
new file mode 100644
index 000000000..301328976
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_acmp.h
@@ -0,0 +1,1372 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_ACMP register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_ACMP ACMP
+ * @{
+ * @brief EFR32MG1P_ACMP Register Declaration
+ ******************************************************************************/
+/** ACMP Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t INPUTSEL; /**< Input Selection Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IM uint32_t APORTREQ; /**< APORT Request Status Register */
+ __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
+ __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */
+ __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */
+
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+} ACMP_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_ACMP
+ * @{
+ * @defgroup EFR32MG1P_ACMP_BitFields ACMP Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for ACMP CTRL */
+#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */
+#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */
+#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */
+#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
+#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
+#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
+#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */
+#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */
+#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
+#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */
+#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */
+#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */
+#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */
+#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */
+#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */
+#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */
+#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */
+#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */
+#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus Selected By VASEL */
+#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */
+#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */
+#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */
+#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */
+#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_DVDD 0x00000001UL /**< Mode DVDD for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_DVDD (_ACMP_CTRL_PWRSEL_DVDD << 12) /**< Shifted mode DVDD for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP Accuracy Mode */
+#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */
+#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */
+#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
+#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */
+#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */
+#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */
+#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */
+#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */
+#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */
+#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */
+#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */
+#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */
+#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
+#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */
+#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */
+#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */
+#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */
+#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
+#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */
+#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */
+#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */
+#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */
+#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */
+#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */
+#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */
+#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */
+
+/* Bit fields for ACMP INPUTSEL */
+#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
+#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */
+#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */
+#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */
+#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */
+#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */
+#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */
+#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */
+#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */
+#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */
+#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */
+#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */
+#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */
+#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */
+#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */
+#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */
+
+/* Bit fields for ACMP STATUS */
+#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
+#define _ACMP_STATUS_MASK 0x00000007UL /**< Mask for ACMP_STATUS */
+#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */
+#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */
+#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */
+#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */
+#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */
+#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */
+
+/* Bit fields for ACMP IF */
+#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
+#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */
+#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
+#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
+#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
+#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */
+#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */
+
+/* Bit fields for ACMP IFS */
+#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */
+#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */
+#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */
+#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
+#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */
+#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */
+#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
+#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */
+
+/* Bit fields for ACMP IFC */
+#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */
+#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */
+#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */
+#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
+#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */
+#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */
+#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
+#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */
+
+/* Bit fields for ACMP IEN */
+#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
+#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */
+#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */
+#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
+#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
+#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */
+#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
+#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
+#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */
+#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
+#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
+#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */
+
+/* Bit fields for ACMP APORTREQ */
+#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */
+#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
+#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */
+#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */
+#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
+#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */
+#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */
+#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */
+#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */
+#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
+#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */
+#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */
+#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */
+#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */
+#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
+#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */
+#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */
+#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
+#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */
+#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */
+#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
+#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */
+#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */
+#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
+#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */
+#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */
+#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
+#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */
+#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */
+#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
+#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
+
+/* Bit fields for ACMP APORTCONFLICT */
+#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */
+#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */
+#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
+
+/* Bit fields for ACMP HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */
+#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */
+#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
+#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
+#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
+
+/* Bit fields for ACMP HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */
+#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */
+#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */
+#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
+#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */
+#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
+#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
+
+/* Bit fields for ACMP ROUTEPEN */
+#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */
+#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */
+#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */
+#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */
+#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */
+#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */
+#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */
+
+/* Bit fields for ACMP ROUTELOC0 */
+#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */
+#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */
+#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */
+#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */
+
+/** @} */
+/** @} End of group EFR32MG1P_ACMP */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_adc.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_adc.h
new file mode 100644
index 000000000..291e59fd9
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_adc.h
@@ -0,0 +1,2238 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_ADC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_ADC ADC
+ * @{
+ * @brief EFR32MG1P_ADC Register Declaration
+ ******************************************************************************/
+/** ADC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */
+ __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register Continued */
+ __IOM uint32_t SCANCTRL; /**< Scan Control Register */
+ __IOM uint32_t SCANCTRLX; /**< Scan Control Register Continued */
+ __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */
+ __IOM uint32_t SCANINPUTSEL; /**< Input Selection Register for Scan Mode */
+ __IOM uint32_t SCANNEGSEL; /**< Negative Input Select Register for Scan */
+ __IOM uint32_t CMPTHR; /**< Compare Threshold Register */
+ __IOM uint32_t BIASPROG; /**< Bias Programming Register for Various Analog Blocks Used in ADC Operation */
+ __IOM uint32_t CAL; /**< Calibration Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */
+ __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
+ __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
+ __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */
+ __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */
+
+ uint32_t RESERVED2[3U]; /**< Reserved for future use **/
+ __IM uint32_t APORTREQ; /**< APORT Request Status Register */
+ __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
+ __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */
+ __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */
+ __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */
+ __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */
+ __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */
+} ADC_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_ADC
+ * @{
+ * @defgroup EFR32MG1P_ADC_BitFields ADC Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for ADC CTRL */
+#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
+#define _ADC_CTRL_MASK 0x2F7F7FDFUL /**< Mask for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
+#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
+#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */
+#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */
+#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
+#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */
+#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */
+#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */
+#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */
+#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */
+#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */
+#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */
+#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */
+#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */
+#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 */
+#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */
+#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */
+#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */
+#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */
+#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */
+#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */
+#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */
+#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */
+#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */
+#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */
+#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
+#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
+#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
+#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
+#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
+#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */
+#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
+#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
+#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
+#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
+#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */
+#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */
+#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */
+#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
+#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */
+#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */
+#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */
+
+/* Bit fields for ADC CMD */
+#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
+#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
+#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */
+#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
+#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
+#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */
+#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
+#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
+#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
+#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
+#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
+#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
+#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
+#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
+#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
+#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
+
+/* Bit fields for ADC STATUS */
+#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
+#define _ADC_STATUS_MASK 0x00031F03UL /**< Mask for ADC_STATUS */
+#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */
+#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
+#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
+#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
+#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
+#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
+#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */
+#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
+#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
+#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
+#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
+#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
+#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */
+#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */
+#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */
+#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */
+#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */
+#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */
+#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
+#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
+#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
+#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */
+#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
+#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
+#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
+#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
+#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
+#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
+#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
+
+/* Bit fields for ADC SINGLECTRL */
+#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */
+#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
+#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
+#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */
+#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
+#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
+#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */
+#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
+#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
+#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */
+#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */
+#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */
+#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */
+#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */
+#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_BUVDD 0x000000E1UL /**< Mode BUVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DVDD 0x000000E2UL /**< Mode DVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_PAVDD 0x000000E3UL /**< Mode PAVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DECOUPLE 0x000000E4UL /**< Mode DECOUPLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_IOVDD 0x000000E5UL /**< Mode IOVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_IOVDD1 0x000000E6UL /**< Mode IOVDD1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_R5VOUT 0x000000F5UL /**< Mode R5VOUT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_BUVDD (_ADC_SINGLECTRL_POSSEL_BUVDD << 8) /**< Shifted mode BUVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DVDD (_ADC_SINGLECTRL_POSSEL_DVDD << 8) /**< Shifted mode DVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_PAVDD (_ADC_SINGLECTRL_POSSEL_PAVDD << 8) /**< Shifted mode PAVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DECOUPLE (_ADC_SINGLECTRL_POSSEL_DECOUPLE << 8) /**< Shifted mode DECOUPLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_IOVDD (_ADC_SINGLECTRL_POSSEL_IOVDD << 8) /**< Shifted mode IOVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_IOVDD1 (_ADC_SINGLECTRL_POSSEL_IOVDD1 << 8) /**< Shifted mode IOVDD1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_R5VOUT (_ADC_SINGLECTRL_POSSEL_R5VOUT << 8) /**< Shifted mode R5VOUT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */
+#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */
+#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */
+#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */
+#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */
+#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */
+#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */
+#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */
+#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */
+#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
+
+/* Bit fields for ADC SINGLECTRLX */
+#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_MASK 0x0F1F7FFFUL /**< Mask for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */
+#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */
+#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
+#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
+#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
+#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */
+#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */
+#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */
+#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */
+#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */
+#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */
+#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */
+#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */
+#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */
+#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */
+#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */
+#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */
+#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */
+#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */
+#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 24 /**< Shift value for ADC_CONVSTARTDELAY */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
+#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
+
+/* Bit fields for ADC SCANCTRL */
+#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
+#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
+#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
+#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
+#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
+#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
+#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
+#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
+#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
+#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */
+#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */
+#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */
+#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */
+#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
+#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */
+#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */
+#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */
+#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */
+#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */
+#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */
+#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */
+#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */
+#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */
+#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
+#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
+
+/* Bit fields for ADC SCANCTRLX */
+#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_MASK 0x0F1F7FFFUL /**< Mask for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */
+#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */
+#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
+#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
+#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
+#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */
+#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */
+#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */
+#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */
+#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */
+#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */
+#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */
+#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */
+#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */
+#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */
+#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */
+#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */
+#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */
+#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */
+#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 24 /**< Shift value for ADC_CONVSTARTDELAY */
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */
+#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
+#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
+
+/* Bit fields for ADC SCANMASK */
+#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */
+#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
+#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
+#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
+
+/* Bit fields for ADC SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
+#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
+
+/* Bit fields for ADC SCANNEGSEL */
+#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
+#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
+#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
+
+/* Bit fields for ADC CMPTHR */
+#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */
+#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */
+#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */
+#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */
+#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */
+#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */
+#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */
+#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */
+#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */
+#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */
+
+/* Bit fields for ADC BIASPROG */
+#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */
+#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */
+#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */
+#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */
+#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF Flag */
+#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */
+#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */
+#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy Setting for the System Bias During ADC Operation */
+#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */
+#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */
+#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
+#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */
+#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */
+#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */
+#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */
+#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */
+
+/* Bit fields for ADC CAL */
+#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */
+#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */
+#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
+#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */
+#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */
+#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */
+#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
+#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
+#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
+#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative Single-ended Offset Calibration is Enabled */
+#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */
+#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */
+#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
+#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */
+#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */
+#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */
+#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */
+#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
+#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
+#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
+#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration Mode is Enabled */
+#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */
+#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */
+#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
+#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */
+
+/* Bit fields for ADC IF */
+#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
+#define _ADC_IF_MASK 0x03030F03UL /**< Mask for ADC_IF */
+#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
+#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
+#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
+#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
+#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
+#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
+#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */
+#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */
+#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
+#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
+#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */
+#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */
+#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
+#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
+#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */
+#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */
+#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */
+#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
+#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
+#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */
+#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */
+#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
+#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
+#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
+#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */
+
+/* Bit fields for ADC IFS */
+#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
+#define _ADC_IFS_MASK 0x03030F00UL /**< Mask for ADC_IFS */
+#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */
+#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */
+#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
+#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
+#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */
+#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */
+#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
+#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
+#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */
+#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */
+#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */
+#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
+#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
+#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */
+#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */
+#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
+#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
+#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
+#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */
+
+/* Bit fields for ADC IFC */
+#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
+#define _ADC_IFC_MASK 0x03030F00UL /**< Mask for ADC_IFC */
+#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */
+#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */
+#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
+#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
+#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */
+#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */
+#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
+#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
+#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */
+#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */
+#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */
+#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
+#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
+#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */
+#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */
+#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
+#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
+#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
+#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */
+
+/* Bit fields for ADC IEN */
+#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
+#define _ADC_IEN_MASK 0x03030F03UL /**< Mask for ADC_IEN */
+#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */
+#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
+#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
+#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */
+#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
+#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
+#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */
+#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
+#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
+#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */
+#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
+#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
+#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */
+#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
+#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
+#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */
+#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
+#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
+#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */
+#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
+#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
+#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */
+#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
+#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
+#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */
+#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
+#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
+#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */
+#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */
+#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
+#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
+#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
+#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */
+
+/* Bit fields for ADC SINGLEDATA */
+#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
+#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
+#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
+#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
+#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
+#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
+
+/* Bit fields for ADC SCANDATA */
+#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
+#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
+#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
+#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
+#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
+#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
+
+/* Bit fields for ADC SINGLEDATAP */
+#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
+#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
+#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
+#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
+#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
+#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
+
+/* Bit fields for ADC SCANDATAP */
+#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
+#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
+#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
+#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
+#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
+#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
+
+/* Bit fields for ADC SCANDATAX */
+#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */
+#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */
+#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
+#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */
+#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */
+#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
+#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */
+#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */
+#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */
+#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
+
+/* Bit fields for ADC SCANDATAXP */
+#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */
+#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */
+#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
+#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */
+#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */
+#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */
+#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */
+#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
+
+/* Bit fields for ADC APORTREQ */
+#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */
+#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
+#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */
+#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */
+#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
+#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */
+#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */
+#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is Requested */
+#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */
+#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */
+#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
+#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */
+#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */
+#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
+#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */
+#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */
+#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
+#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */
+#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */
+#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
+#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */
+#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */
+#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
+#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */
+#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */
+#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
+#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */
+#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */
+#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
+#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */
+#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */
+#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
+#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */
+
+/* Bit fields for ADC APORTCONFLICT */
+#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */
+#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */
+#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
+#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
+
+/* Bit fields for ADC SINGLEFIFOCOUNT */
+#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */
+#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */
+#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */
+#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */
+
+/* Bit fields for ADC SCANFIFOCOUNT */
+#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */
+#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */
+#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */
+#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */
+#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */
+#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */
+
+/* Bit fields for ADC SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO Content */
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */
+#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */
+
+/* Bit fields for ADC SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO Content */
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */
+#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */
+
+/* Bit fields for ADC APORTMASTERDIS */
+#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */
+#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */
+#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
+#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+
+/** @} */
+/** @} End of group EFR32MG1P_ADC */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_af_pins.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_af_pins.h
new file mode 100644
index 000000000..61932082e
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_af_pins.h
@@ -0,0 +1,108 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_AF_PINS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_Alternate_Function Alternate Function
+ * @{
+ * @defgroup EFR32MG1P_AF_Pins Alternate Function Pins
+ * @{
+ ******************************************************************************/
+
+#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
+#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) /**< Pin number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) /**< Pin number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Pin number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) /**< Pin number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) /**< Pin number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) /**< Pin number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) /**< Pin number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) /**< Pin number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) /**< Pin number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) /**< Pin number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) /**< Pin number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) /**< Pin number for AF_PRS_CH11 location number i */
+#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART1_RTS location number i */
+#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LEUART0_RX location number i */
+#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
+#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */
+#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_I2C0_SCL location number i */
+#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP1_OUT location number i */
+#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) /**< Pin number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */
+
+/** @} */
+/** @} End of group EFR32MG1P_AF_Pins */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_af_ports.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_af_ports.h
new file mode 100644
index 000000000..3cbd450d4
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_af_ports.h
@@ -0,0 +1,108 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_AF_PORTS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_Alternate_Function Alternate Function
+ * @{
+ * @defgroup EFR32MG1P_AF_Ports Alternate Function Ports
+ * @{
+ ******************************************************************************/
+
+#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK1 location number i */
+#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) /**< Port number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) /**< Port number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) /**< Port number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) /**< Port number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH11 location number i */
+#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RTS location number i */
+#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LEUART0_RX location number i */
+#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */
+#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT0_S1IN location number i */
+#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C0_SCL location number i */
+#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP1_OUT location number i */
+#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) /**< Port number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */
+
+/** @} */
+/** @} End of group EFR32MG1P_AF_Ports */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_cmu.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_cmu.h
new file mode 100644
index 000000000..b75b2df10
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_cmu.h
@@ -0,0 +1,1783 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_CMU register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_CMU CMU
+ * @{
+ * @brief EFR32MG1P_CMU Register Declaration
+ ******************************************************************************/
+/** CMU Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< CMU Control Register */
+
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
+
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
+
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
+ __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */
+ __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */
+ __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */
+ __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */
+ __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */
+ __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */
+ __IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */
+
+ uint32_t RESERVED3[4U]; /**< Reserved for future use **/
+ __IOM uint32_t CALCTRL; /**< Calibration Control Register */
+ __IOM uint32_t CALCNT; /**< Calibration Counter Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use **/
+ __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED5[2U]; /**< Reserved for future use **/
+ __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */
+ __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use **/
+ __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */
+ __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */
+ __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */
+
+ uint32_t RESERVED7[1U]; /**< Reserved for future use **/
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use **/
+ __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */
+
+ uint32_t RESERVED9[3U]; /**< Reserved for future use **/
+ __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
+
+ uint32_t RESERVED10[7U]; /**< Reserved for future use **/
+ __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
+
+ uint32_t RESERVED12[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */
+ uint32_t RESERVED13[3U]; /**< Reserved for future use **/
+ __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */
+
+ uint32_t RESERVED14[1U]; /**< Reserved for future use **/
+ __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */
+ __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */
+
+ uint32_t RESERVED15[1U]; /**< Reserved for future use **/
+ __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */
+
+ uint32_t RESERVED16[2U]; /**< Reserved for future use **/
+ __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */
+ uint32_t RESERVED17[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */
+
+ uint32_t RESERVED19[3U]; /**< Reserved for future use **/
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ uint32_t RESERVED20[2U]; /**< Reserved for future use **/
+ __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
+
+ uint32_t RESERVED21[2U]; /**< Reserved for future use **/
+ __IOM uint32_t ADCCTRL; /**< ADC Control Register */
+
+ uint32_t RESERVED22[4U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+
+ uint32_t RESERVED23[2U]; /**< Reserved for future use **/
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+} CMU_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_CMU
+ * @{
+ * @defgroup EFR32MG1P_CMU_BitFields CMU Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CMU CTRL */
+#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */
+#define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */
+#define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */
+#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */
+#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */
+#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */
+#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */
+#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */
+#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */
+#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */
+#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */
+#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */
+#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
+#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
+
+/* Bit fields for CMU HFRCOCTRL */
+#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F3CUL /**< Default value for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
+#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
+#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000003CUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */
+#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */
+#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */
+#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */
+#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */
+#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */
+#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */
+#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */
+#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */
+#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */
+#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */
+#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
+#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
+#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
+#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */
+#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */
+#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
+#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
+
+/* Bit fields for CMU AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F3CUL /**< Default value for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
+#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
+#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000003CUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */
+#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */
+#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */
+#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */
+#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */
+#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */
+#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */
+#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
+#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */
+#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */
+#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
+#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
+
+/* Bit fields for CMU LFRCOCTRL */
+#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_MASK 0xF30701FFUL /**< Mask for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
+#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */
+#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */
+#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */
+#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */
+#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */
+#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */
+#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */
+#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */
+#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */
+#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */
+#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */
+#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */
+#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
+#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */
+#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */
+#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
+#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
+
+/* Bit fields for CMU HFXOCTRL */
+#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */
+#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */
+#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */
+#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */
+#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */
+#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */
+#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */
+#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */
+#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */
+#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */
+#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */
+#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */
+#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */
+#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */
+#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */
+#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
+#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
+
+/* Bit fields for CMU HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_RESETVALUE 0x00000240UL /**< Default value for CMU_HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_MASK 0x00000277UL /**< Mask for CMU_HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 0 /**< Shift value for CMU_PEAKDETTHR */
+#define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7UL /**< Bit mask for CMU_PEAKDETTHR */
+#define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
+#define _CMU_HFXOCTRL1_REGLVL_SHIFT 4 /**< Shift value for CMU_REGLVL */
+#define _CMU_HFXOCTRL1_REGLVL_MASK 0x70UL /**< Bit mask for CMU_REGLVL */
+#define _CMU_HFXOCTRL1_REGLVL_DEFAULT 0x00000004UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_REGLVL_DEFAULT (_CMU_HFXOCTRL1_REGLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_XTIBIASEN (0x1UL << 9) /**< Reserved for internal use. Do not change. */
+#define _CMU_HFXOCTRL1_XTIBIASEN_SHIFT 9 /**< Shift value for CMU_XTIBIASEN */
+#define _CMU_HFXOCTRL1_XTIBIASEN_MASK 0x200UL /**< Bit mask for CMU_XTIBIASEN */
+#define _CMU_HFXOCTRL1_XTIBIASEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */
+#define CMU_HFXOCTRL1_XTIBIASEN_DEFAULT (_CMU_HFXOCTRL1_XTIBIASEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
+
+/* Bit fields for CMU HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0xA1250060UL /**< Default value for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_MASK 0xFFEFF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000060UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */
+#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_RESERVED0_SHIFT 21 /**< Shift value for CMU_RESERVED0 */
+#define _CMU_HFXOSTARTUPCTRL_RESERVED0_MASK 0xFE00000UL /**< Bit mask for CMU_RESERVED0 */
+#define _CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT (_CMU_HFXOSTARTUPCTRL_RESERVED0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define _CMU_HFXOSTARTUPCTRL_RESERVED1_SHIFT 28 /**< Shift value for CMU_RESERVED1 */
+#define _CMU_HFXOSTARTUPCTRL_RESERVED1_MASK 0xF0000000UL /**< Bit mask for CMU_RESERVED1 */
+#define _CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+#define CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT (_CMU_HFXOSTARTUPCTRL_RESERVED1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
+
+/* Bit fields for CMU HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30AAD09UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */
+#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000155UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */
+#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */
+#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */
+#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
+
+/* Bit fields for CMU HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x00026667UL /**< Default value for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_SHIFT 8 /**< Shift value for CMU_RESERVED2 */
+#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_MASK 0xF00UL /**< Bit mask for CMU_RESERVED2 */
+#define _CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT (_CMU_HFXOTIMEOUTCTRL_RESERVED2_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
+#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
+
+/* Bit fields for CMU LFXOCTRL */
+#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
+#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
+#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */
+#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */
+#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */
+#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */
+#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */
+#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */
+#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */
+#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */
+#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */
+#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */
+#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */
+#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */
+#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */
+#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */
+#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */
+#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */
+#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */
+#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */
+#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
+#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */
+
+/* Bit fields for CMU ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL /**< Default value for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL /**< Mask for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
+#define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL /**< Bit mask for CMU_TUNING */
+#define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_MODE_SHIFT 10 /**< Shift value for CMU_MODE */
+#define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL /**< Bit mask for CMU_MODE */
+#define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL /**< Mode 1KHZ for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL /**< Mode 2KHZ for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL /**< Mode 4KHZ for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL /**< Mode 32KHZ for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10) /**< Shifted mode 1KHZ for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10) /**< Shifted mode 2KHZ for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10) /**< Shifted mode 4KHZ for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10) /**< Shifted mode 32KHZ for CMU_ULFRCOCTRL */
+#define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16 /**< Shift value for CMU_RESTRIM */
+#define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL /**< Bit mask for CMU_RESTRIM */
+#define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */
+#define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */
+
+/* Bit fields for CMU CALCTRL */
+#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
+#define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
+#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
+#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */
+#define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */
+#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */
+#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */
+#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */
+#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */
+#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */
+#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */
+#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */
+#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */
+#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
+#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
+
+/* Bit fields for CMU CALCNT */
+#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
+#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
+#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
+
+/* Bit fields for CMU OSCENCMD */
+#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
+#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
+#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
+#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
+#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
+#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
+#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
+#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
+#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
+#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
+#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
+#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
+#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
+#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
+#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
+#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
+#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
+#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
+#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
+#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
+#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
+#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
+#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
+#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
+#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
+#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
+#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
+#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
+#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
+#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
+#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
+#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
+
+/* Bit fields for CMU CMD */
+#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
+#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */
+#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */
+#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */
+#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */
+#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
+#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */
+#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */
+#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */
+#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */
+#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */
+#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */
+#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */
+#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */
+#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */
+#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
+#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
+
+/* Bit fields for CMU DBGCLKSEL */
+#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */
+#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */
+#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */
+#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */
+#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */
+#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */
+#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */
+
+/* Bit fields for CMU HFCLKSEL */
+#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */
+#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */
+#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */
+#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */
+#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */
+
+/* Bit fields for CMU LFACLKSEL */
+#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
+#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */
+#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */
+#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */
+#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */
+
+/* Bit fields for CMU LFBCLKSEL */
+#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */
+#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */
+#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */
+#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */
+#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */
+
+/* Bit fields for CMU LFECLKSEL */
+#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */
+#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */
+#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */
+#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */
+#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */
+
+/* Bit fields for CMU STATUS */
+#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */
+#define _CMU_STATUS_MASK 0x07E103FFUL /**< Mask for CMU_STATUS */
+#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
+#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
+#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
+#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
+#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
+#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
+#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
+#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
+#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
+#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
+#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
+#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
+#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
+#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
+#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
+#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
+#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
+#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
+#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
+#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
+#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
+#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
+#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
+#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
+#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
+#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
+#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */
+#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */
+#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */
+#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */
+#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */
+#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */
+#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */
+#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */
+#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */
+#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */
+#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */
+#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */
+#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */
+#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */
+#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */
+#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */
+
+/* Bit fields for CMU HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */
+#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */
+#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */
+#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */
+#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */
+
+/* Bit fields for CMU HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
+#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
+#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
+#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */
+#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */
+#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
+#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
+
+/* Bit fields for CMU IF */
+#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
+#define _CMU_IF_MASK 0x80007F7FUL /**< Mask for CMU_IF */
+#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
+#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
+#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
+#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
+#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
+#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
+#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
+#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
+#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
+#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
+#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
+#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
+#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */
+#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */
+#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */
+#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */
+#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */
+#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */
+#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */
+#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */
+#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
+#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
+#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */
+
+/* Bit fields for CMU IFS */
+#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
+#define _CMU_IFS_MASK 0x80007F7FUL /**< Mask for CMU_IFS */
+#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */
+#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */
+#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
+#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */
+#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */
+#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
+#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */
+#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */
+#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
+#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */
+#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
+#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
+#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */
+#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */
+#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */
+#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */
+#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */
+#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */
+#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */
+#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */
+#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
+#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
+#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
+#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */
+
+/* Bit fields for CMU IFC */
+#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
+#define _CMU_IFC_MASK 0x80007F7FUL /**< Mask for CMU_IFC */
+#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */
+#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */
+#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
+#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */
+#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */
+#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
+#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */
+#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */
+#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
+#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */
+#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
+#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
+#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */
+#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */
+#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */
+#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */
+#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */
+#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */
+#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */
+#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */
+#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
+#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
+#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
+#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */
+
+/* Bit fields for CMU IEN */
+#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
+#define _CMU_IEN_MASK 0x80007F7FUL /**< Mask for CMU_IEN */
+#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */
+#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
+#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
+#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */
+#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
+#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
+#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */
+#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
+#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
+#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */
+#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
+#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
+#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */
+#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
+#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
+#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */
+#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
+#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */
+#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
+#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
+#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */
+#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
+#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
+#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */
+#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
+#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
+#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */
+#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
+#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
+#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */
+#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
+#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
+#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */
+#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
+#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */
+#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
+#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
+#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */
+#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
+#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
+#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */
+#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
+#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
+#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */
+
+/* Bit fields for CMU HFBUSCLKEN0 */
+#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */
+#define _CMU_HFBUSCLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */
+#define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */
+#define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */
+#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_CRYPTO (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
+#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT 1 /**< Shift value for CMU_CRYPTO */
+#define _CMU_HFBUSCLKEN0_CRYPTO_MASK 0x2UL /**< Bit mask for CMU_CRYPTO */
+#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 2) /**< General purpose Input/Output Clock Enable */
+#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 2 /**< Shift value for CMU_GPIO */
+#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x4UL /**< Bit mask for CMU_GPIO */
+#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_PRS (0x1UL << 3) /**< Peripheral Reflex System Clock Enable */
+#define _CMU_HFBUSCLKEN0_PRS_SHIFT 3 /**< Shift value for CMU_PRS */
+#define _CMU_HFBUSCLKEN0_PRS_MASK 0x8UL /**< Bit mask for CMU_PRS */
+#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 4) /**< Linked Direct Memory Access Controller Clock Enable */
+#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 4 /**< Shift value for CMU_LDMA */
+#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x10UL /**< Bit mask for CMU_LDMA */
+#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 5) /**< General Purpose CRC Clock Enable */
+#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 5 /**< Shift value for CMU_GPCRC */
+#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x20UL /**< Bit mask for CMU_GPCRC */
+#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
+#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
+
+/* Bit fields for CMU HFPERCLKEN0 */
+#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
+#define _CMU_HFPERCLKEN0_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */
+#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */
+#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */
+#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */
+#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */
+#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART0 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_USART0_SHIFT 2 /**< Shift value for CMU_USART0 */
+#define _CMU_HFPERCLKEN0_USART0_MASK 0x4UL /**< Bit mask for CMU_USART0 */
+#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART1 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
+#define _CMU_HFPERCLKEN0_USART1_SHIFT 3 /**< Shift value for CMU_USART1 */
+#define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL /**< Bit mask for CMU_USART1 */
+#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 4) /**< Analog Comparator 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 4 /**< Shift value for CMU_ACMP0 */
+#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x10UL /**< Bit mask for CMU_ACMP0 */
+#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 5) /**< Analog Comparator 1 Clock Enable */
+#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 5 /**< Shift value for CMU_ACMP1 */
+#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL /**< Bit mask for CMU_ACMP1 */
+#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CRYOTIMER Clock Enable */
+#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6 /**< Shift value for CMU_CRYOTIMER */
+#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL /**< Bit mask for CMU_CRYOTIMER */
+#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 7) /**< I2C 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_I2C0_SHIFT 7 /**< Shift value for CMU_I2C0 */
+#define _CMU_HFPERCLKEN0_I2C0_MASK 0x80UL /**< Bit mask for CMU_I2C0 */
+#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 8) /**< Analog to Digital Converter 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_ADC0_SHIFT 8 /**< Shift value for CMU_ADC0 */
+#define _CMU_HFPERCLKEN0_ADC0_MASK 0x100UL /**< Bit mask for CMU_ADC0 */
+#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 9) /**< Current Digital to Analog Converter 0 Clock Enable */
+#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 9 /**< Shift value for CMU_IDAC0 */
+#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x200UL /**< Bit mask for CMU_IDAC0 */
+#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
+#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
+
+/* Bit fields for CMU LFACLKEN0 */
+#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
+#define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */
+#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */
+#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */
+#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */
+#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
+#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
+
+/* Bit fields for CMU LFBCLKEN0 */
+#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
+#define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */
+#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
+#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
+#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
+#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
+#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
+
+/* Bit fields for CMU LFECLKEN0 */
+#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */
+#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */
+#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */
+#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */
+#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */
+#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */
+#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */
+
+/* Bit fields for CMU HFPRESC */
+#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */
+#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */
+#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
+#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */
+#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */
+#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */
+#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */
+#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */
+#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */
+#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */
+#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */
+#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */
+
+/* Bit fields for CMU HFCOREPRESC */
+#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */
+#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */
+#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
+#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */
+#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */
+#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */
+#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */
+#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */
+
+/* Bit fields for CMU HFPERPRESC */
+#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */
+#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */
+#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
+#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */
+#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */
+#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */
+#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */
+#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */
+
+/* Bit fields for CMU HFEXPPRESC */
+#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */
+#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */
+#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
+#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */
+#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */
+#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */
+#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */
+#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */
+
+/* Bit fields for CMU LFAPRESC0 */
+#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */
+#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
+#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
+#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
+
+/* Bit fields for CMU LFBPRESC0 */
+#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
+#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
+#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
+#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
+
+/* Bit fields for CMU LFEPRESC0 */
+#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */
+#define _CMU_LFEPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFEPRESC0 */
+#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */
+#define _CMU_LFEPRESC0_RTCC_MASK 0xFUL /**< Bit mask for CMU_RTCC */
+#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */
+#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */
+
+/* Bit fields for CMU SYNCBUSY */
+#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
+#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */
+#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
+#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
+#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */
+#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
+#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
+#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
+#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
+#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
+#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
+#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
+#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
+#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */
+#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */
+#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */
+#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */
+#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */
+#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */
+#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */
+#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */
+#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */
+#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */
+#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */
+#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */
+#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */
+#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */
+#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */
+#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */
+#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */
+#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */
+#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */
+#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */
+#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
+#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
+
+/* Bit fields for CMU FREEZE */
+#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
+#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
+#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
+#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
+#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
+#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
+#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
+#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
+
+/* Bit fields for CMU PCNTCTRL */
+#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
+#define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
+#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
+#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
+#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
+#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
+
+/* Bit fields for CMU ADCCTRL */
+#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */
+#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */
+#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */
+#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */
+#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
+#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */
+
+/* Bit fields for CMU ROUTEPEN */
+#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */
+#define _CMU_ROUTEPEN_MASK 0x00000003UL /**< Mask for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
+#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
+#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
+#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
+#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
+#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
+#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
+#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
+
+/* Bit fields for CMU ROUTELOC0 */
+#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */
+#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
+#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
+
+/* Bit fields for CMU LOCK */
+#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
+#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
+#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
+#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
+
+/** @} */
+/** @} End of group EFR32MG1P_CMU */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_cryotimer.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_cryotimer.h
new file mode 100644
index 000000000..5e245e348
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_cryotimer.h
@@ -0,0 +1,172 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_CRYOTIMER register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_CRYOTIMER CRYOTIMER
+ * @{
+ * @brief EFR32MG1P_CRYOTIMER Register Declaration
+ ******************************************************************************/
+/** CRYOTIMER Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t PERIODSEL; /**< Interrupt Duration */
+ __IM uint32_t CNT; /**< Counter Value */
+ __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+} CRYOTIMER_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_CRYOTIMER
+ * @{
+ * @defgroup EFR32MG1P_CRYOTIMER_BitFields CRYOTIMER Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CRYOTIMER CTRL */
+#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */
+#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */
+#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
+#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */
+#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */
+#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000000UL /**< Mode LFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000001UL /**< Mode LFXO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000002UL /**< Mode ULFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */
+#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */
+#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
+#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
+
+/* Bit fields for CRYOTIMER PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */
+#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
+#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
+
+/* Bit fields for CRYOTIMER CNT */
+#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */
+#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */
+#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
+
+/* Bit fields for CRYOTIMER EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
+#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
+#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
+#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
+#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
+
+/* Bit fields for CRYOTIMER IF */
+#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
+#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */
+#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
+#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
+
+/* Bit fields for CRYOTIMER IFS */
+#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */
+#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */
+#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
+
+/* Bit fields for CRYOTIMER IFC */
+#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */
+#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */
+#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */
+#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
+
+/* Bit fields for CRYOTIMER IEN */
+#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */
+#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */
+#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
+#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
+#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
+
+/** @} */
+/** @} End of group EFR32MG1P_CRYOTIMER */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_crypto.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_crypto.h
new file mode 100644
index 000000000..6446de945
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_crypto.h
@@ -0,0 +1,1203 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_CRYPTO register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_CRYPTO CRYPTO
+ * @{
+ * @brief EFR32MG1P_CRYPTO Register Declaration
+ ******************************************************************************/
+/** CRYPTO Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t DSTATUS; /**< Data Status Register */
+ __IM uint32_t CSTATUS; /**< Control Status Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t KEY; /**< KEY Register Access */
+ __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
+ __IOM uint32_t SEQCTRL; /**< Sequence Control */
+ __IOM uint32_t SEQCTRLB; /**< Sequence Control B */
+ uint32_t RESERVED3[2U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< AES Interrupt Flags */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t SEQ0; /**< Sequence Register 0 */
+ __IOM uint32_t SEQ1; /**< Sequence Register 1 */
+ __IOM uint32_t SEQ2; /**< Sequence Register 2 */
+ __IOM uint32_t SEQ3; /**< Sequence Register 3 */
+ __IOM uint32_t SEQ4; /**< Sequence Register 4 */
+ uint32_t RESERVED4[7U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0; /**< DATA0 Register Access */
+ __IOM uint32_t DATA1; /**< DATA1 Register Access */
+ __IOM uint32_t DATA2; /**< DATA2 Register Access */
+ __IOM uint32_t DATA3; /**< DATA3 Register Access */
+ uint32_t RESERVED5[4U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */
+ uint32_t RESERVED6[3U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */
+ __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */
+ __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */
+ __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */
+ __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */
+ __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */
+ uint32_t RESERVED8[12U]; /**< Reserved for future use **/
+ __IOM uint32_t DDATA0; /**< DDATA0 Register Access */
+ __IOM uint32_t DDATA1; /**< DDATA1 Register Access */
+ __IOM uint32_t DDATA2; /**< DDATA2 Register Access */
+ __IOM uint32_t DDATA3; /**< DDATA3 Register Access */
+ __IOM uint32_t DDATA4; /**< DDATA4 Register Access */
+ uint32_t RESERVED9[7U]; /**< Reserved for future use **/
+ __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */
+ uint32_t RESERVED10[3U]; /**< Reserved for future use **/
+ __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */
+ __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */
+ __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 Access */
+ uint32_t RESERVED11[13U]; /**< Reserved for future use **/
+ __IOM uint32_t QDATA0; /**< QDATA0 Register Access */
+ __IOM uint32_t QDATA1; /**< QDATA1 Register Access */
+ uint32_t RESERVED12[7U]; /**< Reserved for future use **/
+ __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */
+ uint32_t RESERVED13[6U]; /**< Reserved for future use **/
+ __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */
+ __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */
+} CRYPTO_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_CRYPTO
+ * @{
+ * @defgroup EFR32MG1P_CRYPTO_BitFields CRYPTO Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for CRYPTO CTRL */
+#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */
+#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */
+#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */
+#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */
+#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */
+#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */
+#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */
+#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */
+#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */
+#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */
+#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */
+#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */
+#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */
+#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */
+#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */
+#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */
+#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */
+#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */
+#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */
+#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */
+#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */
+#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */
+#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */
+#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */
+#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */
+#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */
+#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
+#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
+
+/* Bit fields for CRYPTO WAC */
+#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */
+#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */
+#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */
+#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */
+#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */
+#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */
+#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */
+#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */
+#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */
+#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */
+#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */
+#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */
+#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */
+#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */
+#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */
+#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */
+#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */
+
+/* Bit fields for CRYPTO CMD */
+#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */
+#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */
+#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */
+#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */
+#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */
+#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */
+#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */
+#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */
+#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */
+#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */
+#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */
+#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */
+#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */
+#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */
+#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
+#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */
+
+/* Bit fields for CRYPTO STATUS */
+#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */
+#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */
+#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */
+#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */
+#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */
+#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is Active */
+#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */
+#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */
+#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is Active */
+#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */
+#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */
+#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
+#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
+
+/* Bit fields for CRYPTO DSTATUS */
+#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */
+#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */
+#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */
+#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */
+#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */
+#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */
+#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */
+#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */
+#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */
+#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */
+#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */
+#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */
+#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
+#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
+
+/* Bit fields for CRYPTO CSTATUS */
+#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */
+#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */
+#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */
+#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */
+#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */
+#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */
+#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */
+#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */
+#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */
+#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */
+#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */
+#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */
+#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
+#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
+
+/* Bit fields for CRYPTO KEY */
+#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */
+#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */
+#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */
+#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */
+#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */
+#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */
+
+/* Bit fields for CRYPTO KEYBUF */
+#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */
+#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */
+#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */
+
+/* Bit fields for CRYPTO SEQCTRL */
+#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */
+#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */
+#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */
+#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */
+#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */
+#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */
+#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve a */
+#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */
+#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */
+#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve a */
+#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */
+#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */
+#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */
+#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */
+#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */
+#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
+#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
+
+/* Bit fields for CRYPTO SEQCTRLB */
+#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */
+#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */
+#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */
+#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */
+#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */
+#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */
+#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
+#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
+
+/* Bit fields for CRYPTO IF */
+#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */
+#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */
+#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction Done */
+#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */
+#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */
+#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */
+#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */
+#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */
+
+/* Bit fields for CRYPTO IFS */
+#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */
+#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */
+#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */
+#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */
+#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */
+#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */
+
+/* Bit fields for CRYPTO IFC */
+#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */
+#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */
+#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */
+#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */
+#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */
+#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */
+
+/* Bit fields for CRYPTO IEN */
+#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */
+#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */
+#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */
+#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
+#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
+#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */
+#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
+#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
+#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */
+#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */
+
+/* Bit fields for CRYPTO SEQ0 */
+#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */
+#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */
+#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */
+#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */
+#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */
+#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */
+#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */
+#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */
+#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
+#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
+
+/* Bit fields for CRYPTO SEQ1 */
+#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */
+#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */
+#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */
+#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */
+#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */
+#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */
+#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */
+#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */
+#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
+#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
+
+/* Bit fields for CRYPTO SEQ2 */
+#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */
+#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */
+#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */
+#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */
+#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */
+#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */
+#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */
+#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */
+#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
+#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
+
+/* Bit fields for CRYPTO SEQ3 */
+#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */
+#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */
+#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */
+#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */
+#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */
+#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */
+#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */
+#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */
+#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
+#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
+
+/* Bit fields for CRYPTO SEQ4 */
+#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */
+#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */
+#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */
+#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */
+#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */
+#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */
+#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */
+#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */
+#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
+#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
+
+/* Bit fields for CRYPTO DATA0 */
+#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */
+#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */
+#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */
+
+/* Bit fields for CRYPTO DATA1 */
+#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */
+#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */
+#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */
+
+/* Bit fields for CRYPTO DATA2 */
+#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */
+#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */
+#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */
+
+/* Bit fields for CRYPTO DATA3 */
+#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */
+#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */
+#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */
+
+/* Bit fields for CRYPTO DATA0XOR */
+#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */
+#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */
+#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */
+
+/* Bit fields for CRYPTO DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */
+#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */
+#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */
+
+/* Bit fields for CRYPTO DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */
+#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */
+#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */
+
+/* Bit fields for CRYPTO DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */
+#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */
+#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */
+
+/* Bit fields for CRYPTO DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */
+#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */
+#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */
+
+/* Bit fields for CRYPTO DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */
+#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */
+#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */
+
+/* Bit fields for CRYPTO DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */
+#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */
+#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */
+
+/* Bit fields for CRYPTO DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */
+#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */
+#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */
+
+/* Bit fields for CRYPTO DDATA0 */
+#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */
+#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */
+#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */
+
+/* Bit fields for CRYPTO DDATA1 */
+#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */
+#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */
+#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */
+
+/* Bit fields for CRYPTO DDATA2 */
+#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */
+#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */
+#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */
+
+/* Bit fields for CRYPTO DDATA3 */
+#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */
+#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */
+#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */
+
+/* Bit fields for CRYPTO DDATA4 */
+#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */
+#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */
+#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */
+
+/* Bit fields for CRYPTO DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */
+#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */
+#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */
+
+/* Bit fields for CRYPTO DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */
+#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */
+#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */
+
+/* Bit fields for CRYPTO DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */
+#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */
+#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */
+
+/* Bit fields for CRYPTO DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */
+#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */
+#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */
+
+/* Bit fields for CRYPTO QDATA0 */
+#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */
+#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */
+#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */
+
+/* Bit fields for CRYPTO QDATA1 */
+#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */
+#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */
+#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */
+
+/* Bit fields for CRYPTO QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */
+#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */
+#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */
+
+/* Bit fields for CRYPTO QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */
+#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */
+#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */
+
+/* Bit fields for CRYPTO QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */
+#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */
+#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */
+
+/** @} */
+/** @} End of group EFR32MG1P_CRYPTO */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_devinfo.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_devinfo.h
new file mode 100644
index 000000000..3c356c929
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_devinfo.h
@@ -0,0 +1,910 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_DEVINFO register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_DEVINFO Device Information and Calibration
+ * @{
+ ******************************************************************************/
+
+/** DEVINFO Register Declaration */
+typedef struct {
+ __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
+ __IM uint32_t MODULEINFO; /**< Module trace information */
+ __IM uint32_t MODXOCAL; /**< Module Crystal Oscillator Calibration */
+ uint32_t RESERVED0[5U]; /**< Reserved for future use **/
+ __IM uint32_t EXTINFO; /**< External Component description */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
+ __IM uint32_t EUI48H; /**< OUI */
+ __IM uint32_t CUSTOMINFO; /**< Custom information */
+ __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
+ __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
+ __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
+ __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
+ __IM uint32_t PART; /**< Part description */
+ __IM uint32_t DEVINFOREV; /**< Device information page revision */
+ __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
+ uint32_t RESERVED3[2U]; /**< Reserved for future use **/
+ __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
+ __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
+ __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
+ __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
+ uint32_t RESERVED4[4U]; /**< Reserved for future use **/
+ __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
+ uint32_t RESERVED5[2U]; /**< Reserved for future use **/
+ __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use **/
+ __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
+ __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
+ __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use **/
+ __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
+ __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
+ __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
+ uint32_t RESERVED8[11U]; /**< Reserved for future use **/
+ __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
+ uint32_t RESERVED9[2U]; /**< Reserved for future use **/
+ __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
+ uint32_t RESERVED10[2U]; /**< Reserved for future use **/
+ __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
+ __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
+ __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use **/
+ __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
+ __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
+ __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
+ uint32_t RESERVED12[11U]; /**< Reserved for future use **/
+ __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
+ __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
+ __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
+ uint32_t RESERVED13[3U]; /**< Reserved for future use **/
+ __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
+ __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
+ uint32_t RESERVED14[2U]; /**< Reserved for future use **/
+ __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
+ __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
+ __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
+ __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */
+ __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */
+ __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */
+ __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
+} DEVINFO_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_DEVINFO
+ * @{
+ * @defgroup EFR32MG1P_DEVINFO_BitFields DEVINFO Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for DEVINFO CAL */
+#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
+#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */
+#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */
+#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
+#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
+
+/* Bit fields for DEVINFO MODULEINFO */
+#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for HWREV */
+#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for HWREV */
+#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for ANTENNA */
+#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for ANTENNA */
+#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for MODNUMBER */
+#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for MODNUMBER */
+#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for TYPE */
+#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for TYPE */
+#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for LFXO */
+#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for LFXO */
+#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for EXPRESS */
+#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for EXPRESS */
+#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for LFXOCALVAL */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for LFXOCALVAL */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for HFXOCALVAL */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for HFXOCALVAL */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_RESERVED1_SHIFT 20 /**< Shift value for RESERVED1 */
+#define _DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFF00000UL /**< Bit mask for RESERVED1 */
+
+/* Bit fields for DEVINFO MODXOCAL */
+#define _DEVINFO_MODXOCAL_MASK 0x0000FFFFUL /**< Mask for DEVINFO_MODXOCAL */
+#define _DEVINFO_MODXOCAL_HFXOCTUNE_SHIFT 0 /**< Shift value for HFXOCTUNE */
+#define _DEVINFO_MODXOCAL_HFXOCTUNE_MASK 0x1FFUL /**< Bit mask for HFXOCTUNE */
+#define _DEVINFO_MODXOCAL_LFXOTUNING_SHIFT 9 /**< Shift value for LFXOTUNING */
+#define _DEVINFO_MODXOCAL_LFXOTUNING_MASK 0xFE00UL /**< Bit mask for LFXOTUNING */
+
+/* Bit fields for DEVINFO EXTINFO */
+#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */
+#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */
+#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */
+#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */
+#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */
+#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */
+#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */
+
+/* Bit fields for DEVINFO EUI48L */
+#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
+#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */
+#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */
+#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */
+#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */
+
+/* Bit fields for DEVINFO EUI48H */
+#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
+#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */
+#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */
+
+/* Bit fields for DEVINFO CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */
+
+/* Bit fields for DEVINFO MEMINFO */
+#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */
+#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */
+#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */
+#define _DEVINFO_MEMINFO_PKGTYPE_KGD 0x00000044UL /**< Mode KGD for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_KGD (_DEVINFO_MEMINFO_PKGTYPE_KGD << 8) /**< Shifted mode KGD for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */
+#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */
+#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */
+
+/* Bit fields for DEVINFO UNIQUEL */
+#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
+#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */
+#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
+
+/* Bit fields for DEVINFO UNIQUEH */
+#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
+#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */
+#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
+
+/* Bit fields for DEVINFO MSIZE */
+#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
+#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */
+#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */
+#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */
+#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */
+
+/* Bit fields for DEVINFO PART */
+#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */
+#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */
+#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */
+#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL /**< Mode EFR32ZG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL /**< Mode EFM32GG12B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16) /**< Shifted mode EFR32ZG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16) /**< Shifted mode EFM32GG12B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
+#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */
+#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */
+
+/* Bit fields for DEVINFO DEVINFOREV */
+#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
+#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */
+#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */
+
+/* Bit fields for DEVINFO EMUTEMP */
+#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */
+
+/* Bit fields for DEVINFO ADC0CAL0 */
+#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
+#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */
+#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */
+#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */
+#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */
+#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */
+#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */
+
+/* Bit fields for DEVINFO ADC0CAL1 */
+#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
+#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */
+#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */
+#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */
+#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */
+#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */
+#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */
+#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */
+
+/* Bit fields for DEVINFO ADC0CAL2 */
+#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
+#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */
+#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */
+#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */
+#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */
+
+/* Bit fields for DEVINFO ADC0CAL3 */
+#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
+#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */
+#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */
+
+/* Bit fields for DEVINFO HFRCOCAL0 */
+#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
+#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL3 */
+#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
+#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL6 */
+#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
+#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL7 */
+#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
+#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL8 */
+#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
+#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL10 */
+#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
+#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL11 */
+#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
+#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO HFRCOCAL12 */
+#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
+#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL0 */
+#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
+#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL3 */
+#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
+#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL6 */
+#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
+#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL7 */
+#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
+#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL8 */
+#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
+#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL10 */
+#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
+#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL11 */
+#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
+#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO AUXHFRCOCAL12 */
+#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
+#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
+#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
+#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
+#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
+#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
+#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
+#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
+#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
+
+/* Bit fields for DEVINFO VMONCAL0 */
+#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
+
+/* Bit fields for DEVINFO VMONCAL1 */
+#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */
+#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
+
+/* Bit fields for DEVINFO VMONCAL2 */
+#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */
+#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
+
+/* Bit fields for DEVINFO IDAC0CAL0 */
+#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */
+#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
+
+/* Bit fields for DEVINFO IDAC0CAL1 */
+#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */
+#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
+
+/* Bit fields for DEVINFO DCDCLNVCTRL0 */
+#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */
+#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */
+#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */
+#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL0 */
+#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL1 */
+#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL2 */
+#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
+#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
+
+/* Bit fields for DEVINFO DCDCLPVCTRL3 */
+#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
+#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
+
+/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */
+
+/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
+#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
+
+/** @} */
+/** @} End of group EFR32MG1P_DEVINFO */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_dma_descriptor.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_dma_descriptor.h
new file mode 100644
index 000000000..e8c4ee1d0
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_dma_descriptor.h
@@ -0,0 +1,55 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_DMA_DESCRIPTOR register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_DMA_DESCRIPTOR DMA Descriptor
+ * @{
+ ******************************************************************************/
+/** DMA_DESCRIPTOR Register Declaration */
+typedef struct {
+ /* Note! Use of double __IOM (volatile) qualifier to ensure that both */
+ /* pointer and referenced memory are declared volatile. */
+ __IOM uint32_t CTRL; /**< DMA control register */
+ __IOM void * __IOM SRC; /**< DMA source address */
+ __IOM void * __IOM DST; /**< DMA destination address */
+ __IOM void * __IOM LINK; /**< DMA link address */
+} DMA_DESCRIPTOR_TypeDef; /**< @} */
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_dmareq.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_dmareq.h
new file mode 100644
index 000000000..4c255d695
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_dmareq.h
@@ -0,0 +1,83 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_DMAREQ register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_DMAREQ DMAREQ
+ * @{
+ * @defgroup EFR32MG1P_DMAREQ_BitFields DMAREQ Bit Fields
+ * @{
+ ******************************************************************************/
+#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
+#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
+#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
+#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
+#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
+#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
+#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
+#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
+#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
+#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
+#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
+#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
+#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
+#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
+#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
+#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
+#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
+#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
+#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
+#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
+#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
+#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
+#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
+#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
+#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
+#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
+#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
+#define DMAREQ_CRYPTO_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO_DATA0WR */
+#define DMAREQ_CRYPTO_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO_DATA0XWR */
+#define DMAREQ_CRYPTO_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO_DATA0RD */
+#define DMAREQ_CRYPTO_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO_DATA1WR */
+#define DMAREQ_CRYPTO_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO_DATA1RD */
+
+/** @} */
+/** @} End of group EFR32MG1P_DMAREQ */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_emu.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_emu.h
new file mode 100644
index 000000000..d479b3fa8
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_emu.h
@@ -0,0 +1,1112 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_EMU register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_EMU EMU
+ * @{
+ * @brief EFR32MG1P_EMU Register Declaration
+ ******************************************************************************/
+/** EMU Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t RAM0CTRL; /**< Memory Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t EM4CTRL; /**< EM4 Control Register */
+ __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */
+ __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
+ __IOM uint32_t PWRCFG; /**< Power Configuration Register */
+ __IOM uint32_t PWRCTRL; /**< Power Control Register */
+ __IOM uint32_t DCDCCTRL; /**< DCDC Control */
+
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
+ __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
+ __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
+ __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */
+ __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
+ __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */
+ __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
+
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
+ __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
+
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
+ __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
+
+ uint32_t RESERVED4[5U]; /**< Reserved for future use **/
+ __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
+ __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
+ __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
+ __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
+
+ uint32_t RESERVED5[49U]; /**< Reserved for future use **/
+ __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */
+
+ uint32_t RESERVED6[10U]; /**< Reserved for future use **/
+ __IOM uint32_t TESTLOCK; /**< Test Lock Register */
+
+ uint32_t RESERVED7[2U]; /**< Reserved for future use **/
+ __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for Regulator and BIAS */
+} EMU_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_EMU
+ * @{
+ * @defgroup EFR32MG1P_EMU_BitFields EMU Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for EMU CTRL */
+#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
+#define _EMU_CTRL_MASK 0x00000002UL /**< Mask for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
+#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
+#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
+
+/* Bit fields for EMU STATUS */
+#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
+#define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */
+#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */
+#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
+#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
+#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */
+#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
+#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
+#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */
+#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
+#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
+#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */
+#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
+#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
+#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */
+#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
+#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
+#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel */
+#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
+#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
+#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */
+#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */
+#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */
+#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */
+#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */
+
+/* Bit fields for EMU LOCK */
+#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
+#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
+
+/* Bit fields for EMU RAM0CTRL */
+#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */
+#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */
+#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */
+
+/* Bit fields for EMU CMD */
+#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
+#define _EMU_CMD_MASK 0x00000001UL /**< Mask for EMU_CMD */
+#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */
+#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */
+#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
+#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
+
+/* Bit fields for EMU EM4CTRL */
+#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */
+#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */
+#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */
+#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */
+#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
+#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
+#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */
+#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
+#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
+#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */
+#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
+#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
+#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
+#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
+#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */
+#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */
+#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+
+/* Bit fields for EMU TEMPLIMITS */
+#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */
+#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
+#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
+#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+
+/* Bit fields for EMU TEMP */
+#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
+#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */
+#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */
+#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */
+#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
+#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
+
+/* Bit fields for EMU IF */
+#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
+#define _EMU_IF_MASK 0xE11FC0FFUL /**< Mask for EMU_IF */
+#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */
+#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */
+#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */
+#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */
+#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */
+#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */
+#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */
+#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */
+#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */
+#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */
+#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */
+#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */
+#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */
+#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */
+#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */
+#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */
+#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */
+#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */
+#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */
+#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
+
+/* Bit fields for EMU IFS */
+#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
+#define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */
+#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */
+#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */
+#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */
+#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */
+#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */
+#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */
+#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */
+#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */
+#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */
+#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */
+#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */
+#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
+#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */
+
+/* Bit fields for EMU IFC */
+#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
+#define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */
+#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */
+#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */
+#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */
+#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */
+#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */
+#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */
+#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */
+#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */
+#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */
+#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */
+#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */
+#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
+#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */
+
+/* Bit fields for EMU IEN */
+#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
+#define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */
+#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
+#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
+#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
+#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
+#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
+#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
+#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
+#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
+#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
+#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
+#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
+#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
+#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */
+#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
+#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
+#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */
+#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
+#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
+#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */
+#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
+#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
+#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */
+#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
+#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
+#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
+#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
+#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */
+#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
+#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
+#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */
+#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
+#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
+#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */
+#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
+#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
+#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */
+#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */
+#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */
+#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */
+#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
+
+/* Bit fields for EMU PWRLOCK */
+#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
+
+/* Bit fields for EMU PWRCFG */
+#define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */
+#define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL /**< Mode STARTUP for EMU_PWRCFG */
+#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0) /**< Shifted mode STARTUP for EMU_PWRCFG */
+#define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */
+
+/* Bit fields for EMU PWRCTRL */
+#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */
+#define _EMU_PWRCTRL_MASK 0x00000020UL /**< Mask for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */
+#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */
+#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */
+#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
+#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
+#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
+#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
+
+/* Bit fields for EMU DCDCCTRL */
+#define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL /**< Default value for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */
+#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */
+#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
+#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
+#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */
+
+/* Bit fields for EMU DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
+#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */
+#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */
+#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */
+#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */
+#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */
+#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */
+#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28 /**< Shift value for EMU_LPCMPBIAS */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIAS */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
+#define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
+#define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
+
+/* Bit fields for EMU DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL /**< Default value for EMU_DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */
+#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
+#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */
+#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
+#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
+
+/* Bit fields for EMU DCDCCLIMCTRL */
+#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL /**< Default value for EMU_DCDCCLIMCTRL */
+#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */
+#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
+#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
+#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */
+#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
+#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
+
+/* Bit fields for EMU DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */
+#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
+
+/* Bit fields for EMU DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */
+#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */
+#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */
+#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
+#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */
+#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */
+#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
+#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
+
+/* Bit fields for EMU DCDCTIMING */
+#define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL /**< Default value for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL /**< Mask for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0 /**< Shift value for EMU_LPINITWAIT */
+#define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */
+#define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN Mode Precharge Enable */
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */
+#define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_LNWAIT_SHIFT 12 /**< Shift value for EMU_LNWAIT */
+#define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL /**< Bit mask for EMU_LNWAIT */
+#define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20 /**< Shift value for EMU_BYPWAIT */
+#define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL /**< Bit mask for EMU_BYPWAIT */
+#define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+#define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29 /**< Shift value for EMU_DUTYSCALE */
+#define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL /**< Bit mask for EMU_DUTYSCALE */
+#define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCTIMING */
+#define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
+
+/* Bit fields for EMU DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */
+#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
+#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
+#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
+#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */
+#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */
+#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
+#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
+
+/* Bit fields for EMU DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL /**< Default value for EMU_DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSEL */
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */
+#define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
+#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
+#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */
+#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */
+#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
+#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
+
+/* Bit fields for EMU DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */
+#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
+#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */
+#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
+#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
+
+/* Bit fields for EMU DCDCSYNC */
+#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
+#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
+#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
+#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
+#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
+
+/* Bit fields for EMU VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */
+#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
+#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
+#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
+#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
+#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */
+#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */
+#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
+#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
+
+/* Bit fields for EMU VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */
+#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
+#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
+#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
+#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
+#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
+#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
+#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
+#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
+
+/* Bit fields for EMU VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */
+#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
+#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
+#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
+#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
+#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
+#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
+#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
+#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
+#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
+
+/* Bit fields for EMU VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */
+#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
+#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
+#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
+#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
+#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
+#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
+#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
+#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
+#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */
+#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
+#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
+#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
+#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
+#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
+#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
+#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
+#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
+
+/* Bit fields for EMU BIASCONF */
+#define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */
+#define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */
+#define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */
+#define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */
+#define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */
+#define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */
+#define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */
+#define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */
+#define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */
+#define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */
+#define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */
+#define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */
+#define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */
+#define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */
+#define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */
+#define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */
+#define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */
+#define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */
+#define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */
+#define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */
+#define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
+#define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */
+
+/* Bit fields for EMU TESTLOCK */
+#define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */
+#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */
+#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */
+
+/* Bit fields for EMU BIASTESTCTRL */
+#define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */
+#define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */
+#define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */
+#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */
+#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */
+#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */
+#define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */
+
+/** @} */
+/** @} End of group EFR32MG1P_EMU */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_fpueh.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_fpueh.h
new file mode 100644
index 000000000..d505999b5
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_fpueh.h
@@ -0,0 +1,199 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_FPUEH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_FPUEH FPUEH
+ * @{
+ * @brief EFR32MG1P_FPUEH Register Declaration
+ ******************************************************************************/
+/** FPUEH Register Declaration */
+typedef struct {
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+} FPUEH_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_FPUEH
+ * @{
+ * @defgroup EFR32MG1P_FPUEH_BitFields FPUEH Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for FPUEH IF */
+#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
+#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
+#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
+#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
+#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
+#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
+#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
+#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
+#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
+#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
+
+/* Bit fields for FPUEH IFS */
+#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
+#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
+#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
+#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
+#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
+#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
+#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
+#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
+#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
+#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
+
+/* Bit fields for FPUEH IFC */
+#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
+#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
+#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
+#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
+#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
+#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
+#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
+#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
+#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
+#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
+
+/* Bit fields for FPUEH IEN */
+#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
+#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
+#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
+#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
+#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
+#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
+#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
+#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
+#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
+#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
+#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
+#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
+#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
+#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
+#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
+#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
+#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
+#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
+#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
+#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
+#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
+#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
+
+/** @} */
+/** @} End of group EFR32MG1P_FPUEH */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpcrc.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpcrc.h
new file mode 100644
index 000000000..8d7ddea16
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpcrc.h
@@ -0,0 +1,192 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_GPCRC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_GPCRC GPCRC
+ * @{
+ * @brief EFR32MG1P_GPCRC Register Declaration
+ ******************************************************************************/
+/** GPCRC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t INIT; /**< CRC Init Value */
+ __IOM uint32_t POLY; /**< CRC Polynomial Value */
+ __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
+ __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
+ __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
+ __IM uint32_t DATA; /**< CRC Data Register */
+ __IM uint32_t DATAREV; /**< CRC Data Reverse Register */
+ __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
+} GPCRC_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_GPCRC
+ * @{
+ * @defgroup EFR32MG1P_GPCRC_BitFields GPCRC Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for GPCRC CTRL */
+#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
+#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */
+#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */
+#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
+#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
+#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */
+#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
+#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
+#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
+#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
+#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
+#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+
+/* Bit fields for GPCRC CMD */
+#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
+#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */
+#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
+#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
+#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
+
+/* Bit fields for GPCRC INIT */
+#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
+#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
+#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
+
+/* Bit fields for GPCRC POLY */
+#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
+#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
+#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
+
+/* Bit fields for GPCRC INPUTDATA */
+#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
+#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
+
+/* Bit fields for GPCRC INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
+#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
+
+/* Bit fields for GPCRC INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
+#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
+
+/* Bit fields for GPCRC DATA */
+#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
+#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
+#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
+
+/* Bit fields for GPCRC DATAREV */
+#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
+#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
+
+/* Bit fields for GPCRC DATABYTEREV */
+#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
+#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
+
+/** @} */
+/** @} End of group EFR32MG1P_GPCRC */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpio.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpio.h
new file mode 100644
index 000000000..23350ab88
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpio.h
@@ -0,0 +1,1359 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_GPIO register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_GPIO GPIO
+ * @{
+ * @brief EFR32MG1P_GPIO Register Declaration
+ ******************************************************************************/
+/** GPIO Register Declaration */
+typedef struct {
+ GPIO_P_TypeDef P[6U]; /**< Port configuration bits */
+
+ uint32_t RESERVED0[184U]; /**< Reserved for future use **/
+ __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
+ __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
+ __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */
+ __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */
+ __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
+ __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
+ __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t EM4WUEN; /**< EM4 Wake Up Enable Register */
+
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
+ __IOM uint32_t INSENSE; /**< Input Sense Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+} GPIO_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_GPIO
+ * @{
+ * @defgroup EFR32MG1P_GPIO_BitFields GPIO Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for GPIO P_CTRL */
+#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive Strength for Port */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */
+#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */
+#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data in Disable */
+#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */
+#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */
+#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate Drive Strength for Port */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */
+#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */
+#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data in Disable */
+#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */
+#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */
+#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+
+/* Bit fields for GPIO P_MODEL */
+#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
+#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
+#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
+#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
+#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */
+#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */
+#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */
+#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */
+#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */
+#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */
+#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */
+#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */
+#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */
+#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */
+#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */
+#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */
+#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
+
+/* Bit fields for GPIO P_MODEH */
+#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */
+#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */
+#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */
+#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */
+#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */
+#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */
+#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */
+#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */
+#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */
+#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */
+#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */
+#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */
+#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */
+#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */
+#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */
+#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */
+#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
+
+/* Bit fields for GPIO P_DOUT */
+#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */
+#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */
+#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */
+#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */
+#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */
+#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */
+
+/* Bit fields for GPIO P_DOUTTGL */
+#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */
+#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */
+#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */
+#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */
+#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */
+#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */
+
+/* Bit fields for GPIO P_DIN */
+#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */
+#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */
+#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */
+#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */
+#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */
+#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */
+
+/* Bit fields for GPIO P_PINLOCKN */
+#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */
+#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */
+#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */
+#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */
+#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */
+#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */
+
+/* Bit fields for GPIO P_OVTDIS */
+#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */
+#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */
+#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */
+#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */
+#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */
+#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */
+
+/* Bit fields for GPIO EXTIPSELL */
+#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
+
+/* Bit fields for GPIO EXTIPSELH */
+#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
+
+/* Bit fields for GPIO EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
+
+/* Bit fields for GPIO EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
+
+/* Bit fields for GPIO EXTIRISE */
+#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */
+#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */
+
+/* Bit fields for GPIO EXTIFALL */
+#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */
+#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */
+
+/* Bit fields for GPIO EXTILEVEL */
+#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */
+#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */
+#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */
+#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */
+#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */
+#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */
+#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */
+#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */
+#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */
+#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */
+#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */
+#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */
+#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */
+#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */
+#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */
+#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */
+#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */
+#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */
+#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */
+#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
+#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
+
+/* Bit fields for GPIO IF */
+#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */
+#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */
+#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
+#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
+#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */
+#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */
+
+/* Bit fields for GPIO IFS */
+#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */
+#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */
+#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
+#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
+#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */
+#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */
+#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */
+#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */
+
+/* Bit fields for GPIO IFC */
+#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */
+#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */
+#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
+#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
+#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */
+#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */
+#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */
+#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */
+
+/* Bit fields for GPIO IEN */
+#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */
+#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */
+#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
+#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
+#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */
+
+/* Bit fields for GPIO EM4WUEN */
+#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */
+#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */
+
+/* Bit fields for GPIO ROUTEPEN */
+#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */
+#define _GPIO_ROUTEPEN_MASK 0x0000001FUL /**< Mask for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */
+#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */
+#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */
+#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */
+#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */
+#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */
+#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */
+#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */
+#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */
+#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */
+#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */
+#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
+#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
+
+/* Bit fields for GPIO ROUTELOC0 */
+#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */
+#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */
+#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */
+#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */
+
+/* Bit fields for GPIO INSENSE */
+#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */
+#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */
+#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */
+#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */
+#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */
+#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */
+#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */
+#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */
+#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */
+#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */
+#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */
+
+/* Bit fields for GPIO LOCK */
+#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */
+#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
+#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
+#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
+
+/** @} */
+/** @} End of group EFR32MG1P_GPIO */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpio_p.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpio_p.h
new file mode 100644
index 000000000..391c13ac7
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_gpio_p.h
@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_GPIO_P register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief GPIO_P GPIO P Register
+ * @ingroup EFR32MG1P_GPIO
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t CTRL; /**< Port Control Register */
+ __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
+ __IOM uint32_t MODEH; /**< Port Pin Mode High Register */
+ __IOM uint32_t DOUT; /**< Port Data Out Register */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
+ __IM uint32_t DIN; /**< Port Data in Register */
+ __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */
+ uint32_t RESERVED2[1U]; /**< Reserved future */
+} GPIO_P_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_i2c.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_i2c.h
new file mode 100644
index 000000000..e0741e76b
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_i2c.h
@@ -0,0 +1,928 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_I2C register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_I2C I2C
+ * @{
+ * @brief EFR32MG1P_I2C Register Declaration
+ ******************************************************************************/
+/** I2C Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATE; /**< State Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Division Register */
+ __IOM uint32_t SADDR; /**< Slave Address Register */
+ __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
+ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
+ __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
+ __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
+ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
+ __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+} I2C_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_I2C
+ * @{
+ * @defgroup EFR32MG1P_I2C_BitFields I2C Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for I2C CTRL */
+#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
+#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
+#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
+#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
+#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
+#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
+#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
+#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */
+#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
+#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
+#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
+#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
+#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
+#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
+#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
+#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
+#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
+#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
+#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
+#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
+#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
+#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
+#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
+#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
+#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
+#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
+#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
+#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
+
+/* Bit fields for I2C CMD */
+#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
+#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
+#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */
+#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */
+#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
+#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
+#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
+#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
+#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
+#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
+#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
+#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
+#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */
+#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
+#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
+#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */
+#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
+#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
+#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
+#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
+#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
+
+/* Bit fields for I2C STATE */
+#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
+#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
+#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
+#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
+#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
+#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
+#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
+#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
+#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
+#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
+#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
+#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
+#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
+#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
+#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
+#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
+#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
+#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
+#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
+#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
+#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
+#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
+#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
+#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
+#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
+#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
+#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
+#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
+#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
+
+/* Bit fields for I2C STATUS */
+#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
+#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
+#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
+#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
+#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
+#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
+#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
+#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
+#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
+#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
+#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
+#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
+#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */
+#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
+#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
+#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */
+#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
+#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
+#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
+#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
+#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
+#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
+#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
+#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
+#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
+#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
+#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
+
+/* Bit fields for I2C CLKDIV */
+#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
+#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
+#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
+#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
+#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
+#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
+
+/* Bit fields for I2C SADDR */
+#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
+#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
+#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
+#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
+#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
+#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
+
+/* Bit fields for I2C SADDRMASK */
+#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
+#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
+#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
+
+/* Bit fields for I2C RXDATA */
+#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
+#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
+#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
+
+/* Bit fields for I2C RXDOUBLE */
+#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+
+/* Bit fields for I2C RXDATAP */
+#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
+#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
+#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
+
+/* Bit fields for I2C RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+
+/* Bit fields for I2C TXDATA */
+#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
+#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
+#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
+
+/* Bit fields for I2C TXDOUBLE */
+#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+
+/* Bit fields for I2C IF */
+#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
+#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
+#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */
+#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */
+#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
+#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
+#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
+#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
+#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
+#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
+#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
+#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
+#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
+#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
+#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
+#define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
+#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
+#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
+#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
+#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
+#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
+#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
+#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
+#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
+#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
+#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
+#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
+#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
+#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
+#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
+#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
+#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
+#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
+#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
+#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
+#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
+#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
+#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
+#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
+#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */
+#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
+#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
+#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
+#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
+#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
+#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
+#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
+#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
+
+/* Bit fields for I2C IFS */
+#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
+#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
+#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
+#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
+#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
+#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
+#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
+#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
+#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
+#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
+#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
+#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
+#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
+#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
+#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
+#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
+#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
+#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
+#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
+#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
+#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
+#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
+#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
+#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
+#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
+#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
+#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
+#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
+#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
+#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
+#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
+#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
+#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
+#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
+#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
+#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
+#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
+#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
+#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
+#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
+#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
+
+/* Bit fields for I2C IFC */
+#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
+#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
+#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
+#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
+#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
+#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
+#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
+#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
+#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
+#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
+#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
+#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
+#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
+#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
+#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
+#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
+#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
+#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
+#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
+#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
+#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
+#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
+#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
+#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
+#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
+#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
+#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
+#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
+#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
+#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
+#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
+#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
+#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
+#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
+#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
+#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
+#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
+#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
+#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
+#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
+#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
+#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
+#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
+#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
+
+/* Bit fields for I2C IEN */
+#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
+#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
+#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
+#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
+#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
+#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
+#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
+#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
+#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
+#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
+#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
+#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
+#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
+#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
+#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
+#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
+#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
+#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
+#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
+#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
+#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
+#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
+#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
+#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
+#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
+#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
+#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
+#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
+#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
+#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
+#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
+#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
+#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
+#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
+#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
+#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
+#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
+#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
+#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
+#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
+#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
+#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
+#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
+
+/* Bit fields for I2C ROUTEPEN */
+#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
+#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
+#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
+#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
+#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
+#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
+#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
+#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
+#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
+
+/* Bit fields for I2C ROUTELOC0 */
+#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
+#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */
+#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
+#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */
+#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
+#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
+#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
+
+/** @} */
+/** @} End of group EFR32MG1P_I2C */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_idac.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_idac.h
new file mode 100644
index 000000000..b6934b810
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_idac.h
@@ -0,0 +1,324 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_IDAC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_IDAC IDAC
+ * @{
+ * @brief EFR32MG1P_IDAC Register Declaration
+ ******************************************************************************/
+/** IDAC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CURPROG; /**< Current Programming Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
+
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
+ __IM uint32_t APORTREQ; /**< APORT Request Status Register */
+ __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
+} IDAC_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_IDAC
+ * @{
+ * @defgroup EFR32MG1P_IDAC_BitFields IDAC Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for IDAC CTRL */
+#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
+#define _IDAC_CTRL_MASK 0x00F17FFFUL /**< Mask for IDAC_CTRL */
+#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
+#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
+#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
+#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
+#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
+#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
+#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
+#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
+#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
+#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */
+#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */
+#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */
+#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */
+#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */
+#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */
+#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */
+#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */
+#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */
+#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */
+#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */
+#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */
+#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */
+#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */
+#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */
+#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */
+#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */
+#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */
+#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */
+#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */
+#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */
+#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
+#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */
+#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */
+#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */
+#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */
+
+/* Bit fields for IDAC CURPROG */
+#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */
+#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
+#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
+#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
+#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
+#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
+#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
+#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
+#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
+#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */
+#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */
+#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */
+#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */
+
+/* Bit fields for IDAC DUTYCONFIG */
+#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
+#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
+#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
+
+/* Bit fields for IDAC STATUS */
+#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */
+#define _IDAC_STATUS_MASK 0x00000002UL /**< Mask for IDAC_STATUS */
+#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */
+#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
+#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
+
+/* Bit fields for IDAC IF */
+#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */
+#define _IDAC_IF_MASK 0x00000002UL /**< Mask for IDAC_IF */
+#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */
+#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
+#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
+
+/* Bit fields for IDAC IFS */
+#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */
+#define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */
+#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */
+#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
+#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
+
+/* Bit fields for IDAC IFC */
+#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */
+#define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */
+#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */
+#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
+#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
+
+/* Bit fields for IDAC IEN */
+#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */
+#define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */
+#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */
+#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
+#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
+#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
+#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
+
+/* Bit fields for IDAC APORTREQ */
+#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
+#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */
+#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
+#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
+#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
+#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
+#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
+#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
+#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
+
+/* Bit fields for IDAC APORTCONFLICT */
+#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
+#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
+#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
+
+/** @} */
+/** @} End of group EFR32MG1P_IDAC */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_ldma.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_ldma.h
new file mode 100644
index 000000000..1048aeea0
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_ldma.h
@@ -0,0 +1,568 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_LDMA register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_LDMA LDMA
+ * @{
+ * @brief EFR32MG1P_LDMA Register Declaration
+ ******************************************************************************/
+/** LDMA Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< DMA Control Register */
+ __IM uint32_t STATUS; /**< DMA Status Register */
+ __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
+ uint32_t RESERVED0[5U]; /**< Reserved for future use **/
+ __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
+ __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
+ __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
+ __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
+ __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
+ __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
+ __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
+ __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
+ __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
+ uint32_t RESERVED1[7U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+
+ uint32_t RESERVED2[4U]; /**< Reserved registers */
+ LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
+} LDMA_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_LDMA
+ * @{
+ * @defgroup EFR32MG1P_LDMA_BitFields LDMA Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for LDMA CTRL */
+#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */
+#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */
+#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
+#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
+#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
+#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
+#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
+#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
+#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
+#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */
+#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
+
+/* Bit fields for LDMA STATUS */
+#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */
+#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */
+#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
+#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
+#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
+#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
+#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
+#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
+#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
+#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */
+#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
+#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */
+#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
+#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
+#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
+#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
+#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
+
+/* Bit fields for LDMA SYNC */
+#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
+#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
+#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
+#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
+#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
+#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
+
+/* Bit fields for LDMA CHEN */
+#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
+#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
+#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
+
+/* Bit fields for LDMA CHBUSY */
+#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
+#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */
+#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
+#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */
+#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
+#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
+
+/* Bit fields for LDMA CHDONE */
+#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
+#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */
+#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
+#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */
+#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+
+/* Bit fields for LDMA DBGHALT */
+#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
+#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
+
+/* Bit fields for LDMA SWREQ */
+#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
+#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
+#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
+
+/* Bit fields for LDMA REQDIS */
+#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
+#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
+#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
+
+/* Bit fields for LDMA REQPEND */
+#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
+#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
+#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
+
+/* Bit fields for LDMA LINKLOAD */
+#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
+#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
+
+/* Bit fields for LDMA REQCLEAR */
+#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
+#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
+
+/* Bit fields for LDMA IF */
+#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
+#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */
+#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
+#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
+#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
+#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
+#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
+
+/* Bit fields for LDMA IFS */
+#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
+#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */
+#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
+#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
+#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
+#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
+#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
+#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
+#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
+#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
+
+/* Bit fields for LDMA IFC */
+#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
+#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */
+#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
+#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
+#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
+#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
+#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
+#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
+#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
+#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
+
+/* Bit fields for LDMA IEN */
+#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
+#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */
+#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
+#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
+#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
+#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
+#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
+
+/* Bit fields for LDMA CH_REQSEL */
+#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR 0x00000000UL /**< Mode CRYPTODATA0WR for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR 0x00000001UL /**< Mode CRYPTODATA0XWR for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD 0x00000002UL /**< Mode CRYPTODATA0RD for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR 0x00000003UL /**< Mode CRYPTODATA1WR for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD 0x00000004UL /**< Mode CRYPTODATA1RD for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR << 0) /**< Shifted mode CRYPTODATA0WR for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR << 0) /**< Shifted mode CRYPTODATA0XWR for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD << 0) /**< Shifted mode CRYPTODATA0RD for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR << 0) /**< Shifted mode CRYPTODATA1WR for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD << 0) /**< Shifted mode CRYPTODATA1RD for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
+#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO 0x00000031UL /**< Mode CRYPTO for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
+#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO << 16) /**< Shifted mode CRYPTO for LDMA_CH_REQSEL */
+
+/* Bit fields for LDMA CH_CFG */
+#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
+#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
+#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
+#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
+#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
+#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
+#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
+#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
+#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
+
+/* Bit fields for LDMA CH_LOOP */
+#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
+#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
+#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
+#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
+#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
+#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
+
+/* Bit fields for LDMA CH_CTRL */
+#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
+#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
+#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
+#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
+#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
+#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
+#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
+#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
+#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
+#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
+#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
+#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
+#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
+#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
+#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
+#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
+#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
+#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
+#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
+#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
+#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
+#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
+#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
+#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
+#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
+#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
+#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
+#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
+#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
+#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
+#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
+#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
+#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
+#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
+#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
+#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
+#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
+
+/* Bit fields for LDMA CH_SRC */
+#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
+#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
+#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
+#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
+#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
+#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
+
+/* Bit fields for LDMA CH_DST */
+#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
+#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
+#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
+#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
+#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
+#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
+
+/* Bit fields for LDMA CH_LINK */
+#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
+#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
+#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
+#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
+#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
+#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
+#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
+#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
+#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+
+/** @} */
+/** @} End of group EFR32MG1P_LDMA */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_ldma_ch.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_ldma_ch.h
new file mode 100644
index 000000000..c9b6e7e5d
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_ldma_ch.h
@@ -0,0 +1,56 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_LDMA_CH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief LDMA_CH LDMA CH Register
+ * @ingroup EFR32MG1P_LDMA
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
+ __IOM uint32_t CFG; /**< Channel Configuration Register */
+ __IOM uint32_t LOOP; /**< Channel Loop Counter Register */
+ __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
+ __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
+ __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
+ __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
+ uint32_t RESERVED0[5U]; /**< Reserved future */
+} LDMA_CH_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_letimer.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_letimer.h
new file mode 100644
index 000000000..971cb5c7f
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_letimer.h
@@ -0,0 +1,627 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_LETIMER register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_LETIMER LETIMER
+ * @{
+ * @brief EFR32MG1P_LETIMER Register Declaration
+ ******************************************************************************/
+/** LETIMER Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IOM uint32_t COMP0; /**< Compare Value Register 0 */
+ __IOM uint32_t COMP1; /**< Compare Value Register 1 */
+ __IOM uint32_t REP0; /**< Repeat Counter Register 0 */
+ __IOM uint32_t REP1; /**< Repeat Counter Register 1 */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
+ __IOM uint32_t PRSSEL; /**< PRS Input Select Register */
+} LETIMER_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_LETIMER
+ * @{
+ * @defgroup EFR32MG1P_LETIMER_BitFields LETIMER Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for LETIMER CTRL */
+#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
+#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
+#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
+#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
+#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
+#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
+#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
+#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
+#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
+#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
+#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
+#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
+#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
+#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
+#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
+#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
+#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */
+#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
+#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
+#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
+#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
+#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
+#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+
+/* Bit fields for LETIMER CMD */
+#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
+#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
+#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
+#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
+#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
+#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
+#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
+#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
+#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
+#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
+#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
+#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
+#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
+#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
+#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
+#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
+#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
+#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
+
+/* Bit fields for LETIMER STATUS */
+#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
+#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
+#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
+#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
+#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
+
+/* Bit fields for LETIMER CNT */
+#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
+#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
+#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
+
+/* Bit fields for LETIMER COMP0 */
+#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
+#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
+#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
+
+/* Bit fields for LETIMER COMP1 */
+#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
+#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
+#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
+
+/* Bit fields for LETIMER REP0 */
+#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
+#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
+#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
+
+/* Bit fields for LETIMER REP1 */
+#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
+#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
+#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
+
+/* Bit fields for LETIMER IF */
+#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
+#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
+#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
+#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
+#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
+#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
+#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
+#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
+
+/* Bit fields for LETIMER IFS */
+#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */
+#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */
+#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */
+#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */
+#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */
+#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */
+#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */
+#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
+#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */
+
+/* Bit fields for LETIMER IFC */
+#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */
+#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */
+#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */
+#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */
+#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */
+#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */
+#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */
+#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
+#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */
+
+/* Bit fields for LETIMER IEN */
+#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
+#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
+#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */
+#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */
+#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */
+#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */
+#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */
+#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
+
+/* Bit fields for LETIMER SYNCBUSY */
+#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
+#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
+#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */
+#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */
+#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+
+/* Bit fields for LETIMER ROUTEPEN */
+#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */
+#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */
+#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */
+#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */
+#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */
+#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */
+#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */
+#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
+#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
+
+/* Bit fields for LETIMER ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */
+#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */
+#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */
+#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
+#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
+
+/* Bit fields for LETIMER PRSSEL */
+#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
+#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
+#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */
+
+/** @} */
+/** @} End of group EFR32MG1P_LETIMER */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_leuart.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_leuart.h
new file mode 100644
index 000000000..c35ade400
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_leuart.h
@@ -0,0 +1,842 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_LEUART register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_LEUART LEUART
+ * @{
+ * @brief EFR32MG1P_LEUART Register Declaration
+ ******************************************************************************/
+/** LEUART Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Control Register */
+ __IOM uint32_t STARTFRAME; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
+ __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
+ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
+ __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
+ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
+
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IOM uint32_t INPUT; /**< LEUART Input Register */
+} LEUART_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_LEUART
+ * @{
+ * @defgroup EFR32MG1P_LEUART_BitFields LEUART Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for LEUART CTRL */
+#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
+#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
+#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
+#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
+#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
+#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
+#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
+#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
+#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
+#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
+#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
+#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
+#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
+#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
+#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
+#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
+#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
+#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
+#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
+#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
+#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */
+#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
+#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
+#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */
+#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
+#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
+#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
+#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
+#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
+#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
+#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
+#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
+#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
+#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
+#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
+#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
+#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
+#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
+#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
+#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
+#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
+#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
+#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
+#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
+#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
+#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
+#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
+#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
+#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
+#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
+#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
+#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
+
+/* Bit fields for LEUART CMD */
+#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
+#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
+#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
+#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
+#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
+#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
+#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
+#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
+#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
+#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
+#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
+#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
+#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
+#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
+#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
+#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
+#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
+#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
+#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
+#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
+#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
+#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
+#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
+#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
+#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
+#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
+#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
+#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
+
+/* Bit fields for LEUART STATUS */
+#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */
+#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */
+#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
+#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
+#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
+#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
+#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
+#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
+#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
+#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
+#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
+#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
+#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
+#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
+#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
+#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
+#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
+#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
+#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */
+#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */
+#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */
+#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
+#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */
+
+/* Bit fields for LEUART CLKDIV */
+#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
+#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */
+#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
+#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */
+#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
+#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
+
+/* Bit fields for LEUART STARTFRAME */
+#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
+#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
+#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
+
+/* Bit fields for LEUART SIGFRAME */
+#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
+#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
+#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
+
+/* Bit fields for LEUART RXDATAX */
+#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
+#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
+#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
+#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
+#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
+#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
+#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
+#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
+#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
+#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
+#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
+#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
+
+/* Bit fields for LEUART RXDATA */
+#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
+#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
+#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
+#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
+
+/* Bit fields for LEUART RXDATAXP */
+#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
+#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
+#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
+#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
+#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
+#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
+#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
+#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
+#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
+#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
+#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
+#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
+
+/* Bit fields for LEUART TXDATAX */
+#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
+#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
+#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
+#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
+#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
+#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
+#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
+#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
+#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
+#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
+#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
+#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
+#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
+#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
+
+/* Bit fields for LEUART TXDATA */
+#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
+#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
+#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
+
+/* Bit fields for LEUART IF */
+#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
+#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
+#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
+#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
+#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
+#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
+#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
+#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
+#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
+#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
+#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
+#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
+#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
+#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
+#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
+#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
+#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
+#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
+#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
+#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
+#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
+#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
+#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
+#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
+#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
+
+/* Bit fields for LEUART IFS */
+#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
+#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
+#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
+#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
+#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
+#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */
+#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */
+#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */
+#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */
+#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
+#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
+#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */
+#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
+#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
+#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */
+#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */
+#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */
+#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
+#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
+#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
+
+/* Bit fields for LEUART IFC */
+#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
+#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
+#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
+#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
+#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
+#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */
+#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */
+#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */
+#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */
+#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
+#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
+#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */
+#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
+#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
+#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */
+#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */
+#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */
+#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
+#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
+#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
+
+/* Bit fields for LEUART IEN */
+#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
+#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
+#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
+#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
+#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
+#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
+#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
+#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
+#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
+#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
+#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
+#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */
+#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
+#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
+#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */
+#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
+#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
+#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */
+#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
+#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
+#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */
+#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
+#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
+#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */
+#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
+#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
+#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */
+#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
+#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
+#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */
+#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
+#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
+#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */
+#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
+#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
+#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
+#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
+
+/* Bit fields for LEUART PULSECTRL */
+#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
+#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
+#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
+#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
+#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
+#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
+#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
+#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
+#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
+#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
+#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
+#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
+
+/* Bit fields for LEUART FREEZE */
+#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
+#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
+#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
+#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
+#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
+#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
+#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
+#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
+
+/* Bit fields for LEUART SYNCBUSY */
+#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
+#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
+#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
+#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
+#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
+#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
+#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
+#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
+#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
+#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
+#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
+#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
+#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
+#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
+#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
+#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
+#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
+#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
+#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
+#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
+#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
+#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
+#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
+#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
+#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
+#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
+#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
+
+/* Bit fields for LEUART ROUTEPEN */
+#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */
+#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
+#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
+#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
+#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
+#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
+#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
+#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
+#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
+
+/* Bit fields for LEUART ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */
+#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */
+#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */
+#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */
+#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */
+#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
+#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
+
+/* Bit fields for LEUART INPUT */
+#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
+#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
+#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */
+#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
+#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
+#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */
+#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */
+#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */
+#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
+#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */
+
+/** @} */
+/** @} End of group EFR32MG1P_LEUART */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_msc.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_msc.h
new file mode 100644
index 000000000..8087cbe4e
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_msc.h
@@ -0,0 +1,508 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_MSC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_MSC MSC
+ * @{
+ * @brief EFR32MG1P_MSC Register Declaration
+ ******************************************************************************/
+/** MSC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Memory System Control Register */
+ __IOM uint32_t READCTRL; /**< Read Control Register */
+ __IOM uint32_t WRITECTRL; /**< Write Control Register */
+ __IOM uint32_t WRITECMD; /**< Write Command Register */
+ __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t WDATA; /**< Write Data Register */
+ __IM uint32_t STATUS; /**< Status Register */
+
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */
+ __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
+ __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
+
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
+
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
+ __IOM uint32_t STARTUP; /**< Startup Control */
+
+ uint32_t RESERVED4[5U]; /**< Reserved for future use **/
+ __IOM uint32_t CMD; /**< Command Register */
+} MSC_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_MSC
+ * @{
+ * @defgroup EFR32MG1P_MSC_BitFields MSC Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for MSC CTRL */
+#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
+#define _MSC_CTRL_MASK 0x0000000FUL /**< Mask for MSC_CTRL */
+#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */
+#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */
+#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */
+#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */
+#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */
+#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
+#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */
+#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
+#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
+#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */
+#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */
+#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */
+#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
+#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */
+
+/* Bit fields for MSC READCTRL */
+#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */
+#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */
+#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
+#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
+#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
+#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
+#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
+#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
+#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
+#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
+#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
+#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
+#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
+#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
+#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */
+#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */
+#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */
+#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */
+#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */
+#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */
+#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */
+#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */
+#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */
+
+/* Bit fields for MSC WRITECTRL */
+#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
+#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
+#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
+#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+
+/* Bit fields for MSC WRITECMD */
+#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
+#define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
+#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */
+#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
+#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
+#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
+#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
+#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
+#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
+#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
+#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
+#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
+#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
+#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */
+#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */
+#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */
+#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+
+/* Bit fields for MSC ADDRB */
+#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
+#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
+#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
+
+/* Bit fields for MSC WDATA */
+#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
+#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
+#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
+#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
+#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
+#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
+
+/* Bit fields for MSC STATUS */
+#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
+#define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
+#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
+#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
+#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
+#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
+#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
+#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
+#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
+#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
+#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
+#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
+#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
+#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
+#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
+#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
+
+/* Bit fields for MSC IF */
+#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
+#define _MSC_IF_MASK 0x0000003FUL /**< Mask for MSC_IF */
+#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
+#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
+#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
+#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
+#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
+#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
+#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
+#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
+#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
+#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
+#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
+#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
+#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */
+#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
+#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */
+#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
+#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
+
+/* Bit fields for MSC IFS */
+#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
+#define _MSC_IFS_MASK 0x0000003FUL /**< Mask for MSC_IFS */
+#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */
+#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
+#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
+#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */
+#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
+#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
+#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */
+#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
+#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
+#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */
+#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
+#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
+#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */
+#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
+#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */
+#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
+#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
+#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
+
+/* Bit fields for MSC IFC */
+#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
+#define _MSC_IFC_MASK 0x0000003FUL /**< Mask for MSC_IFC */
+#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */
+#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
+#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
+#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */
+#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
+#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
+#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */
+#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
+#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
+#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */
+#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
+#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
+#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */
+#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
+#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */
+#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
+#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
+#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
+
+/* Bit fields for MSC IEN */
+#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
+#define _MSC_IEN_MASK 0x0000003FUL /**< Mask for MSC_IEN */
+#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */
+#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
+#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
+#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */
+#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
+#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
+#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */
+#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
+#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
+#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */
+#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
+#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
+#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */
+#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
+#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */
+#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
+#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
+#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
+
+/* Bit fields for MSC LOCK */
+#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
+#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
+
+/* Bit fields for MSC CACHECMD */
+#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */
+#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */
+#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
+#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
+#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
+#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
+#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
+#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
+#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
+#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
+#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
+#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
+#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */
+
+/* Bit fields for MSC CACHEHITS */
+#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
+#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
+#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
+
+/* Bit fields for MSC CACHEMISSES */
+#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
+#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
+#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
+
+/* Bit fields for MSC MASSLOCK */
+#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
+#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
+
+/* Bit fields for MSC STARTUP */
+#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */
+#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */
+#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */
+#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */
+#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */
+#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */
+#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */
+#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */
+#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */
+#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */
+#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */
+#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */
+#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */
+#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */
+#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */
+#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
+#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */
+#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */
+#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
+#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */
+
+/* Bit fields for MSC CMD */
+#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
+#define _MSC_CMD_MASK 0x00000001UL /**< Mask for MSC_CMD */
+#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
+#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
+#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
+#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
+
+/** @} */
+/** @} End of group EFR32MG1P_MSC */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_pcnt.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_pcnt.h
new file mode 100644
index 000000000..048f2d5c5
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_pcnt.h
@@ -0,0 +1,713 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_PCNT register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_PCNT PCNT
+ * @{
+ * @brief EFR32MG1P_PCNT Register Declaration
+ ******************************************************************************/
+/** PCNT Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t TOP; /**< Top Value Register */
+ __IOM uint32_t TOPB; /**< Top Value Buffer Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+
+ uint32_t RESERVED2[7U]; /**< Reserved for future use **/
+ __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t INPUT; /**< PCNT Input Register */
+ __IOM uint32_t OVSCFG; /**< Oversampling Config Register */
+} PCNT_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_PCNT
+ * @{
+ * @defgroup EFR32MG1P_PCNT_BitFields PCNT Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for PCNT CTRL */
+#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
+#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
+#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */
+#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */
+#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */
+#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
+#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */
+#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */
+#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */
+#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */
+#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */
+#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */
+#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */
+#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */
+#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */
+#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */
+#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */
+#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */
+#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */
+#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */
+#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */
+#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */
+#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */
+#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */
+#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */
+#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
+#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */
+#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */
+#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */
+#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */
+#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */
+#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */
+#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */
+#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */
+#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */
+#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */
+#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */
+#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */
+#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */
+#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */
+#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */
+#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */
+#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */
+#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */
+#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */
+#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */
+#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */
+#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */
+#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */
+#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */
+#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */
+#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */
+#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */
+#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */
+#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */
+
+/* Bit fields for PCNT CMD */
+#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
+#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */
+#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */
+#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */
+#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */
+#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */
+#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
+
+/* Bit fields for PCNT STATUS */
+#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
+#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */
+#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
+#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
+#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
+#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
+
+/* Bit fields for PCNT CNT */
+#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
+#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
+#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
+#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
+
+/* Bit fields for PCNT TOP */
+#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
+#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
+#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
+#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
+
+/* Bit fields for PCNT TOPB */
+#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
+#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
+#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
+
+/* Bit fields for PCNT IF */
+#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
+#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */
+#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
+#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
+#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
+#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
+#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
+#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
+#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
+#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
+#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */
+#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
+#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
+#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */
+#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */
+
+/* Bit fields for PCNT IFS */
+#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */
+#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */
+#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */
+#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */
+#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
+#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */
+#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */
+#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
+#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */
+#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */
+#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */
+#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
+#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
+#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */
+#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
+#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */
+
+/* Bit fields for PCNT IFC */
+#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */
+#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */
+#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */
+#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */
+#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
+#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */
+#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */
+#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
+#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */
+#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */
+#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */
+#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
+#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
+#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */
+#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
+#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */
+
+/* Bit fields for PCNT IEN */
+#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
+#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */
+#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */
+#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
+#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
+#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */
+#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
+#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
+#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */
+#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */
+#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */
+#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
+#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
+#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */
+#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */
+
+/* Bit fields for PCNT ROUTELOC0 */
+#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */
+#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */
+#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */
+#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
+#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
+
+/* Bit fields for PCNT FREEZE */
+#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */
+#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
+#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */
+#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */
+#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */
+#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */
+#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */
+#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */
+
+/* Bit fields for PCNT SYNCBUSY */
+#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
+#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
+#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
+#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */
+#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */
+#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */
+#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */
+#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+
+/* Bit fields for PCNT AUXCNT */
+#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
+#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
+
+/* Bit fields for PCNT INPUT */
+#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */
+#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */
+#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */
+#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
+#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */
+#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */
+#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */
+#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */
+#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */
+#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
+#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */
+#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */
+#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */
+#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
+#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */
+
+/* Bit fields for PCNT OVSCFG */
+#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */
+#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */
+#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */
+#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */
+#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
+#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
+#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */
+#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */
+#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */
+#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
+#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
+
+/** @} */
+/** @} End of group EFR32MG1P_PCNT */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs.h
new file mode 100644
index 000000000..824fee1c7
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs.h
@@ -0,0 +1,962 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_PRS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_PRS PRS
+ * @{
+ * @brief EFR32MG1P_PRS Register Declaration
+ ******************************************************************************/
+/** PRS Register Declaration */
+typedef struct {
+ __IOM uint32_t SWPULSE; /**< Software Pulse Register */
+ __IOM uint32_t SWLEVEL; /**< Software Level Register */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
+ __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
+
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */
+ __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IM uint32_t PEEK; /**< PRS Channel Values */
+
+ uint32_t RESERVED3[3U]; /**< Reserved registers */
+ PRS_CH_TypeDef CH[12U]; /**< Channel registers */
+} PRS_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_PRS
+ * @{
+ * @defgroup EFR32MG1P_PRS_BitFields PRS Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for PRS SWPULSE */
+#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
+#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
+#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
+#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
+#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
+#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
+#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
+#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
+#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
+#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
+#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
+#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
+#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
+#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
+#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
+#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
+#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
+#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
+#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
+#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
+#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
+#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
+#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
+#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
+#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
+#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
+#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
+#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
+#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
+#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
+#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
+#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
+#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
+#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
+#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
+#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
+#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
+#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
+#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
+#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
+
+/* Bit fields for PRS SWLEVEL */
+#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
+#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
+#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
+#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
+#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
+#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
+#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
+#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
+#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
+#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
+#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
+#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
+#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
+#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
+#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
+#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
+#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
+#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
+#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
+#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
+#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
+#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
+#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
+#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
+#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
+#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
+#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
+#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
+#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
+#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
+#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
+#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
+#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
+#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
+#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
+#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
+#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
+#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
+#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
+
+/* Bit fields for PRS ROUTEPEN */
+#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */
+#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
+#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
+#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
+#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
+#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
+#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
+#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
+#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
+#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
+#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
+#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
+#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
+#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */
+#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */
+#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */
+#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */
+#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */
+#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */
+#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */
+#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */
+#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */
+#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */
+#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */
+#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */
+#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */
+#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */
+#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */
+#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */
+#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */
+#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */
+#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */
+#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */
+#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */
+#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */
+#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */
+#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */
+#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
+#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
+
+/* Bit fields for PRS ROUTELOC0 */
+#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */
+#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */
+#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */
+#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */
+#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */
+#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */
+#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */
+#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */
+#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */
+#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */
+#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */
+
+/* Bit fields for PRS ROUTELOC1 */
+#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */
+#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */
+#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */
+#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */
+#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */
+#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */
+#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */
+#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */
+#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */
+#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */
+#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */
+
+/* Bit fields for PRS ROUTELOC2 */
+#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */
+#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */
+#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */
+#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */
+#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */
+#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */
+#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */
+#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */
+#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
+#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
+#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
+
+/* Bit fields for PRS CTRL */
+#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */
+#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */
+#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */
+#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */
+#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */
+#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */
+#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */
+#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */
+#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */
+#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */
+#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */
+
+/* Bit fields for PRS DMAREQ0 */
+#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */
+#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */
+#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */
+#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */
+
+/* Bit fields for PRS DMAREQ1 */
+#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */
+#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */
+#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */
+#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */
+
+/* Bit fields for PRS PEEK */
+#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */
+#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */
+#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */
+#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */
+#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */
+#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */
+#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */
+#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */
+#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */
+#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */
+#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */
+#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */
+#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */
+#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */
+#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */
+#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */
+#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */
+#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */
+#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */
+#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */
+#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */
+#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */
+#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */
+#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */
+#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */
+#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */
+#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */
+#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */
+#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */
+#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */
+#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */
+#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */
+#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */
+#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */
+#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */
+#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */
+#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */
+#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */
+#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
+#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */
+
+/* Bit fields for PRS CH_CTRL */
+#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
+#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */
+#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */
+#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000006UL /**< Mode ACMP0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000007UL /**< Mode ACMP1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000029UL /**< Mode RTCC for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000003CUL /**< Mode CRYOTIMER for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_CMU 0x0000003DUL /**< Mode CMU for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */
+#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */
+#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */
+#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
+#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
+#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
+#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */
+#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */
+#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */
+#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */
+#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */
+#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */
+#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */
+#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */
+#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */
+#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */
+#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */
+#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */
+#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */
+#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */
+#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */
+#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
+#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
+
+/** @} */
+/** @} End of group EFR32MG1P_PRS */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs_ch.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs_ch.h
new file mode 100644
index 000000000..4ba1c2db0
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs_ch.h
@@ -0,0 +1,49 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_PRS_CH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief PRS_CH PRS CH Register
+ * @ingroup EFR32MG1P_PRS
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t CTRL; /**< Channel Control Register */
+} PRS_CH_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs_signals.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs_signals.h
new file mode 100644
index 000000000..fe91c2ead
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_prs_signals.h
@@ -0,0 +1,134 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_PRS_SIGNALS register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_PRS
+ * @{
+ * @addtogroup EFR32MG1P_PRS_Signals PRS Signals
+ * @{
+ * @brief PRS Signal names
+ ******************************************************************************/
+#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */
+#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */
+#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */
+#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */
+#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */
+#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */
+#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */
+#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */
+#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */
+#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */
+#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */
+#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */
+#define PRS_ACMP0_OUT ((6 << 8) + 0) /**< PRS Analog comparator output */
+#define PRS_ACMP1_OUT ((7 << 8) + 0) /**< PRS Analog comparator output */
+#define PRS_ADC0_SINGLE ((8 << 8) + 0) /**< PRS ADC single conversion done */
+#define PRS_ADC0_SCAN ((8 << 8) + 1) /**< PRS ADC scan conversion done */
+#define PRS_USART0_IRTX ((16 << 8) + 0) /**< PRS USART 0 IRDA out */
+#define PRS_USART0_TXC ((16 << 8) + 1) /**< PRS USART 0 TX complete */
+#define PRS_USART0_RXDATAV ((16 << 8) + 2) /**< PRS USART 0 RX Data Valid */
+#define PRS_USART0_RTS ((16 << 8) + 3) /**< PRS USART 0 RTS */
+#define PRS_USART0_TX ((16 << 8) + 5) /**< PRS USART 0 TX */
+#define PRS_USART0_CS ((16 << 8) + 6) /**< PRS USART 0 CS */
+#define PRS_USART1_TXC ((17 << 8) + 1) /**< PRS USART 1 TX complete */
+#define PRS_USART1_RXDATAV ((17 << 8) + 2) /**< PRS USART 1 RX Data Valid */
+#define PRS_USART1_RTS ((17 << 8) + 3) /**< PRS USART 0 RTS */
+#define PRS_USART1_TX ((17 << 8) + 5) /**< PRS USART 1 TX */
+#define PRS_USART1_CS ((17 << 8) + 6) /**< PRS USART 1 CS */
+#define PRS_TIMER0_UF ((28 << 8) + 0) /**< PRS Timer 0 Underflow */
+#define PRS_TIMER0_OF ((28 << 8) + 1) /**< PRS Timer 0 Overflow */
+#define PRS_TIMER0_CC0 ((28 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */
+#define PRS_TIMER0_CC1 ((28 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */
+#define PRS_TIMER0_CC2 ((28 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */
+#define PRS_TIMER1_UF ((29 << 8) + 0) /**< PRS Timer 1 Underflow */
+#define PRS_TIMER1_OF ((29 << 8) + 1) /**< PRS Timer 1 Overflow */
+#define PRS_TIMER1_CC0 ((29 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */
+#define PRS_TIMER1_CC1 ((29 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */
+#define PRS_TIMER1_CC2 ((29 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */
+#define PRS_TIMER1_CC3 ((29 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */
+#define PRS_RAC_ACTIVE ((32 << 8) + 0) /**< PRS RAC is active */
+#define PRS_RAC_TX ((32 << 8) + 1) /**< PRS RAC is in TX */
+#define PRS_RAC_RX ((32 << 8) + 2) /**< PRS RAC is in RX */
+#define PRS_RAC_LNAEN ((32 << 8) + 3) /**< PRS LNA enable */
+#define PRS_RAC_PAEN ((32 << 8) + 4) /**< PRS PA enable */
+#define PRS_PROTIMER_LBTS ((35 << 8) + 5) /**< PRS Listen Before Talk Success */
+#define PRS_PROTIMER_LBTR ((35 << 8) + 6) /**< PRS Listen Before Talk Retry */
+#define PRS_PROTIMER_LBTF ((35 << 8) + 7) /**< PRS Listen Before Talk Failure */
+#define PRS_MODEM_FRAMEDET ((38 << 8) + 0) /**< PRS Frame detected */
+#define PRS_MODEM_PREDET ((38 << 8) + 1) /**< PRS Receive preamble detected */
+#define PRS_MODEM_TIMDET ((38 << 8) + 2) /**< PRS Receive timing detected */
+#define PRS_MODEM_FRAMESENT ((38 << 8) + 3) /**< PRS Entire frame transmitted */
+#define PRS_MODEM_SYNCSENT ((38 << 8) + 4) /**< PRS Syncword transmitted */
+#define PRS_MODEM_PRESENT ((38 << 8) + 5) /**< PRS Preamble transmitted */
+#define PRS_MODEM_ANT0 ((39 << 8) + 5) /**< PRS Antenna 0 select */
+#define PRS_MODEM_ANT1 ((39 << 8) + 6) /**< PRS Antenna 1 select */
+#define PRS_RTCC_CCV0 ((41 << 8) + 1) /**< PRS RTCC Compare 0 */
+#define PRS_RTCC_CCV1 ((41 << 8) + 2) /**< PRS RTCC Compare 1 */
+#define PRS_RTCC_CCV2 ((41 << 8) + 3) /**< PRS RTCC Compare 2 */
+#define PRS_GPIO_PIN0 ((48 << 8) + 0) /**< PRS GPIO pin 0 */
+#define PRS_GPIO_PIN1 ((48 << 8) + 1) /**< PRS GPIO pin 1 */
+#define PRS_GPIO_PIN2 ((48 << 8) + 2) /**< PRS GPIO pin 2 */
+#define PRS_GPIO_PIN3 ((48 << 8) + 3) /**< PRS GPIO pin 3 */
+#define PRS_GPIO_PIN4 ((48 << 8) + 4) /**< PRS GPIO pin 4 */
+#define PRS_GPIO_PIN5 ((48 << 8) + 5) /**< PRS GPIO pin 5 */
+#define PRS_GPIO_PIN6 ((48 << 8) + 6) /**< PRS GPIO pin 6 */
+#define PRS_GPIO_PIN7 ((48 << 8) + 7) /**< PRS GPIO pin 7 */
+#define PRS_GPIO_PIN8 ((49 << 8) + 0) /**< PRS GPIO pin 8 */
+#define PRS_GPIO_PIN9 ((49 << 8) + 1) /**< PRS GPIO pin 9 */
+#define PRS_GPIO_PIN10 ((49 << 8) + 2) /**< PRS GPIO pin 10 */
+#define PRS_GPIO_PIN11 ((49 << 8) + 3) /**< PRS GPIO pin 11 */
+#define PRS_GPIO_PIN12 ((49 << 8) + 4) /**< PRS GPIO pin 12 */
+#define PRS_GPIO_PIN13 ((49 << 8) + 5) /**< PRS GPIO pin 13 */
+#define PRS_GPIO_PIN14 ((49 << 8) + 6) /**< PRS GPIO pin 14 */
+#define PRS_GPIO_PIN15 ((49 << 8) + 7) /**< PRS GPIO pin 15 */
+#define PRS_LETIMER0_CH0 ((52 << 8) + 0) /**< PRS LETIMER CH0 Out */
+#define PRS_LETIMER0_CH1 ((52 << 8) + 1) /**< PRS LETIMER CH1 Out */
+#define PRS_PCNT0_TCC ((54 << 8) + 0) /**< PRS Triggered compare match */
+#define PRS_PCNT0_UFOF ((54 << 8) + 1) /**< PRS Counter overflow or underflow */
+#define PRS_PCNT0_DIR ((54 << 8) + 2) /**< PRS Counter direction */
+#define PRS_RFSENSE_WU ((59 << 8) + 0) /**< PRS RFSENSE Output */
+#define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */
+#define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */
+#define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */
+#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */
+
+/** @} */
+/** @} End of group EFR32MG1P_PRS */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rmu.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rmu.h
new file mode 100644
index 000000000..6d86b45f6
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rmu.h
@@ -0,0 +1,198 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_RMU register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_RMU RMU
+ * @{
+ * @brief EFR32MG1P_RMU Register Declaration
+ ******************************************************************************/
+/** RMU Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IM uint32_t RSTCAUSE; /**< Reset Cause Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t RST; /**< Reset Control Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+} RMU_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_RMU
+ * @{
+ * @defgroup EFR32MG1P_RMU_BitFields RMU Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for RMU CTRL */
+#define _RMU_CTRL_RESETVALUE 0x00004224UL /**< Default value for RMU_CTRL */
+#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */
+#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */
+#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */
+#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */
+#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */
+#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */
+#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */
+#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */
+#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
+#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */
+#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */
+#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */
+#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
+#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */
+
+/* Bit fields for RMU RSTCAUSE */
+#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
+#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power on Reset */
+#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
+#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */
+#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */
+#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */
+#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */
+#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */
+#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */
+#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */
+#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */
+#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */
+#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */
+#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */
+#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */
+#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */
+#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */
+#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */
+#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */
+#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */
+#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */
+#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */
+#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
+#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
+
+/* Bit fields for RMU CMD */
+#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
+#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
+#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
+#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
+#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
+#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
+
+/* Bit fields for RMU RST */
+#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */
+#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */
+
+/* Bit fields for RMU LOCK */
+#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */
+#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
+#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
+#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
+
+/** @} */
+/** @} End of group EFR32MG1P_RMU */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_romtable.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_romtable.h
new file mode 100644
index 000000000..6937673ea
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_romtable.h
@@ -0,0 +1,79 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_ROMTABLE register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_ROMTABLE ROM Table, Chip Revision Information
+ * @{
+ * @brief Chip Information, Revision numbers
+ ******************************************************************************/
+/** ROMTABLE Register Declaration */
+typedef struct {
+ __IM uint32_t PID4; /**< JEP_106_BANK */
+ __IM uint32_t PID5; /**< Unused */
+ __IM uint32_t PID6; /**< Unused */
+ __IM uint32_t PID7; /**< Unused */
+ __IM uint32_t PID0; /**< Chip family LSB, chip major revision */
+ __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
+ __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
+ __IM uint32_t PID3; /**< Chip minor rev LSB */
+ __IM uint32_t CID0; /**< Unused */
+} ROMTABLE_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_ROMTABLE
+ * @{
+ * @defgroup EFR32MG1P_ROMTABLE_BitFields ROM Table Bit Field definitions
+ * @{
+ ******************************************************************************/
+/* Bit fields for EFR32MG1P_ROMTABLE */
+#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
+#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
+#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */
+#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */
+#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
+#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
+#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
+#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
+
+/** @} */
+/** @} End of group EFR32MG1P_ROMTABLE */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc.h
new file mode 100644
index 000000000..b837b376e
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc.h
@@ -0,0 +1,702 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_RTCC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_RTCC RTCC
+ * @{
+ * @brief EFR32MG1P_RTCC Register Declaration
+ ******************************************************************************/
+/** RTCC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
+ __IOM uint32_t TIME; /**< Time of Day Register */
+ __IOM uint32_t DATE; /**< Date Register */
+ __IM uint32_t IF; /**< RTCC Interrupt Flags */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
+
+ RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */
+
+ uint32_t RESERVED0[37U]; /**< Reserved registers */
+ RTCC_RET_TypeDef RET[32U]; /**< RetentionReg */
+} RTCC_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_RTCC
+ * @{
+ * @defgroup EFR32MG1P_RTCC_BitFields RTCC Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for RTCC CTRL */
+#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
+#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */
+#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */
+#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */
+#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */
+#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
+#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */
+#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
+#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */
+#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
+#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
+#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */
+#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
+#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
+#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */
+#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */
+#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */
+#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
+#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */
+#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */
+#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
+#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
+#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */
+#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
+#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
+#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */
+#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
+#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
+#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */
+#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
+#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
+#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */
+#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
+#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
+#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
+#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */
+
+/* Bit fields for RTCC PRECNT */
+#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */
+#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */
+#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
+#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
+#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */
+#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */
+
+/* Bit fields for RTCC CNT */
+#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */
+#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */
+#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */
+#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */
+#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */
+#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */
+
+/* Bit fields for RTCC COMBCNT */
+#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */
+#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */
+#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
+#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
+#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
+#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
+#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */
+#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */
+#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
+#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
+
+/* Bit fields for RTCC TIME */
+#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */
+#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */
+#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */
+#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */
+#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */
+#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */
+#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */
+#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */
+#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */
+#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */
+#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */
+#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */
+#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */
+#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */
+#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */
+#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
+#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */
+
+/* Bit fields for RTCC DATE */
+#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */
+#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */
+#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */
+#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */
+#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */
+#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */
+#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */
+#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
+#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
+#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
+#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
+#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */
+#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */
+#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */
+#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */
+#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */
+#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */
+#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */
+#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
+#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */
+
+/* Bit fields for RTCC IF */
+#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */
+#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */
+#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */
+#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
+#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */
+#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
+#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */
+#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
+#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */
+#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
+#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */
+#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */
+#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */
+#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */
+#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */
+#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */
+#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */
+#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
+#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */
+
+/* Bit fields for RTCC IFS */
+#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */
+#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */
+#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
+#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */
+#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
+#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */
+#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
+#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */
+#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
+#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */
+#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
+#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */
+#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */
+#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */
+#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */
+#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */
+#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */
+#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */
+#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
+#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */
+
+/* Bit fields for RTCC IFC */
+#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */
+#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */
+#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
+#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */
+#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
+#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */
+#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
+#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */
+#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
+#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */
+#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
+#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */
+#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */
+#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */
+#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */
+#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */
+#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */
+#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */
+#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
+#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */
+
+/* Bit fields for RTCC IEN */
+#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */
+#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */
+#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
+#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */
+#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
+#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */
+#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
+#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
+#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */
+#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
+#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
+#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */
+#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
+#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
+#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */
+#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
+#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
+#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */
+#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
+#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
+#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */
+#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
+#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
+#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */
+#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
+#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
+#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */
+#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
+#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
+#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */
+#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
+#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
+#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */
+#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
+#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
+#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
+#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */
+
+/* Bit fields for RTCC STATUS */
+#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */
+#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */
+
+/* Bit fields for RTCC CMD */
+#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
+#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
+#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */
+#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
+#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
+#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
+#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */
+
+/* Bit fields for RTCC SYNCBUSY */
+#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */
+#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */
+#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */
+#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */
+#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */
+#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */
+#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */
+
+/* Bit fields for RTCC POWERDOWN */
+#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
+#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
+#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */
+#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
+#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
+#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
+#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */
+
+/* Bit fields for RTCC LOCK */
+#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */
+#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
+#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
+#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
+
+/* Bit fields for RTCC EM4WUEN */
+#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
+#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
+#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
+#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
+#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
+#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
+#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */
+
+/* Bit fields for RTCC CC_CTRL */
+#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */
+#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */
+#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */
+#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */
+#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */
+#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */
+#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */
+#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */
+#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */
+#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
+#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
+#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */
+#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
+#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */
+#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
+#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
+#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */
+#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */
+#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */
+
+/* Bit fields for RTCC CC_CCV */
+#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */
+#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */
+#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */
+#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */
+#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */
+#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */
+
+/* Bit fields for RTCC CC_TIME */
+#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */
+#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */
+#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */
+#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */
+#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */
+#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */
+#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */
+#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */
+#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */
+#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */
+#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */
+#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */
+#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
+#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
+
+/* Bit fields for RTCC CC_DATE */
+#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */
+#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */
+#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */
+#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */
+#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */
+#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
+#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
+#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
+#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
+#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
+#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
+
+/* Bit fields for RTCC RET_REG */
+#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */
+#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */
+#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */
+#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */
+#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
+#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
+
+/** @} */
+/** @} End of group EFR32MG1P_RTCC */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc_cc.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc_cc.h
new file mode 100644
index 000000000..d038c30b1
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc_cc.h
@@ -0,0 +1,52 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_RTCC_CC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief RTCC_CC RTCC CC Register
+ * @ingroup EFR32MG1P_RTCC
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t CTRL; /**< CC Channel Control Register */
+ __IOM uint32_t CCV; /**< Capture/Compare Value Register */
+ __IOM uint32_t TIME; /**< Capture/Compare Time Register */
+ __IOM uint32_t DATE; /**< Capture/Compare Date Register */
+} RTCC_CC_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc_ret.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc_ret.h
new file mode 100644
index 000000000..6bb576863
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_rtcc_ret.h
@@ -0,0 +1,49 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_RTCC_RET register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief RTCC_RET RTCC RET Register
+ * @ingroup EFR32MG1P_RTCC
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t REG; /**< Retention Register */
+} RTCC_RET_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_timer.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_timer.h
new file mode 100644
index 000000000..cbe0e314d
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_timer.h
@@ -0,0 +1,1582 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_TIMER register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_TIMER TIMER
+ * @{
+ * @brief EFR32MG1P_TIMER Register Declaration
+ ******************************************************************************/
+/** TIMER Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t TOP; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
+
+ uint32_t RESERVED2[8U]; /**< Reserved registers */
+ TIMER_CC_TypeDef CC[4U]; /**< Compare/Capture Channel */
+
+ __IOM uint32_t DTCTRL; /**< DTI Control Register */
+ __IOM uint32_t DTTIME; /**< DTI Time Control Register */
+ __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */
+ __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
+ __IM uint32_t DTFAULT; /**< DTI Fault Register */
+ __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */
+ __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
+} TIMER_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_TIMER
+ * @{
+ * @defgroup EFR32MG1P_TIMER_BitFields TIMER Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for TIMER CTRL */
+#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
+#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
+#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
+#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
+#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
+#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */
+#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */
+#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
+#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */
+#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
+#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
+#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
+#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
+#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
+#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
+#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
+#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
+#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
+#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
+#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
+#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */
+#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */
+#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
+#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
+#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
+#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
+#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
+#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
+#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
+#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
+#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
+#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
+#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */
+#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
+#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
+#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
+#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
+#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
+#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
+#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
+#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
+#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
+#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
+#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
+#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */
+
+/* Bit fields for TIMER CMD */
+#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
+#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
+#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
+#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
+#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
+#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
+#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
+#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
+#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
+
+/* Bit fields for TIMER STATUS */
+#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
+#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
+#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
+#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
+#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
+#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
+#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
+#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
+#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
+#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
+#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
+#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
+#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
+#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
+#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
+#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
+#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
+#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
+#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
+#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
+#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
+#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
+#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
+#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
+#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
+#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
+#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
+#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
+#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
+#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
+#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
+#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
+#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
+#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
+#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
+#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
+#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+
+/* Bit fields for TIMER IF */
+#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
+#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */
+#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
+#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
+#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
+#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
+#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
+#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
+#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
+#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */
+
+/* Bit fields for TIMER IFS */
+#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
+#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */
+#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
+#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
+#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
+#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
+#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
+#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
+#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
+#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
+#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
+#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
+#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
+#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
+#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */
+
+/* Bit fields for TIMER IFC */
+#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
+#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */
+#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
+#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
+#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
+#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
+#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
+#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
+#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
+#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
+#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
+#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
+#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
+#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
+#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */
+
+/* Bit fields for TIMER IEN */
+#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
+#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */
+#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
+#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
+#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
+#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
+#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
+#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
+#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
+#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
+#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
+#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
+#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
+#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */
+
+/* Bit fields for TIMER TOP */
+#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
+#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
+#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
+#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
+
+/* Bit fields for TIMER TOPB */
+#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
+#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
+#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
+
+/* Bit fields for TIMER CNT */
+#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
+#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
+#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
+#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
+
+/* Bit fields for TIMER LOCK */
+#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */
+#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
+#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
+#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
+
+/* Bit fields for TIMER ROUTEPEN */
+#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */
+#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
+#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
+#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
+#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
+#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
+#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
+#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
+#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
+#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
+#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
+#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
+#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
+#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
+#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
+#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
+#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
+#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
+#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
+#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
+#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
+#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
+
+/* Bit fields for TIMER ROUTELOC0 */
+#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
+#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
+#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
+#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
+#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
+#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
+#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
+
+/* Bit fields for TIMER ROUTELOC2 */
+#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
+#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
+#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
+#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */
+#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
+#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
+
+/* Bit fields for TIMER CC_CTRL */
+#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
+#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
+#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
+#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
+#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
+#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
+#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
+#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
+#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
+#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
+#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
+#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
+#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
+#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
+#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
+#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
+#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
+#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
+
+/* Bit fields for TIMER CC_CCV */
+#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
+#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
+#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
+#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
+#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
+#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
+
+/* Bit fields for TIMER CC_CCVP */
+#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
+#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
+#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
+#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
+#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
+#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
+
+/* Bit fields for TIMER CC_CCVB */
+#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
+#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
+#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
+#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
+#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
+#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
+
+/* Bit fields for TIMER DTCTRL */
+#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
+#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
+#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
+#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
+#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
+#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
+#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
+#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
+#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
+#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
+#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
+#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
+#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
+#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
+#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
+#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
+#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
+#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
+#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
+#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+
+/* Bit fields for TIMER DTTIME */
+#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
+#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
+#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
+#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
+#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
+#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
+#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
+#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
+#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
+#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
+#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
+
+/* Bit fields for TIMER DTFC */
+#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
+#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
+#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */
+#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
+#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */
+#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */
+#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
+#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
+#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
+#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
+#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
+#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
+#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
+#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
+#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
+#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
+#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
+#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
+#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
+#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
+#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
+#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
+
+/* Bit fields for TIMER DTOGEN */
+#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
+#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+
+/* Bit fields for TIMER DTFAULT */
+#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
+#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
+#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
+#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
+#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
+#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+
+/* Bit fields for TIMER DTFAULTC */
+#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
+#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
+#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
+#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
+#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
+#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+
+/* Bit fields for TIMER DTLOCK */
+#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
+#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
+#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
+
+/** @} */
+/** @} End of group EFR32MG1P_TIMER */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_timer_cc.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_timer_cc.h
new file mode 100644
index 000000000..4c7ab67c5
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_timer_cc.h
@@ -0,0 +1,52 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_TIMER_CC register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief TIMER_CC TIMER CC Register
+ * @ingroup EFR32MG1P_TIMER
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t CTRL; /**< CC Channel Control Register */
+ __IOM uint32_t CCV; /**< CC Channel Value Register */
+ __IM uint32_t CCVP; /**< CC Channel Value Peek Register */
+ __IOM uint32_t CCVB; /**< CC Channel Buffer Register */
+} TIMER_CC_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_usart.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_usart.h
new file mode 100644
index 000000000..d3c78c195
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_usart.h
@@ -0,0 +1,1979 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_USART register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_USART USART
+ * @{
+ * @brief EFR32MG1P_USART Register Declaration
+ ******************************************************************************/
+/** USART Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t FRAME; /**< USART Frame Format Register */
+ __IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< USART Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Control Register */
+ __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
+ __IM uint32_t RXDATA; /**< RX Buffer Data Register */
+ __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
+ __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
+ __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
+ __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
+ __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
+ __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
+ __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
+ __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t IRCTRL; /**< IrDA Control Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t INPUT; /**< USART Input Register */
+ __IOM uint32_t I2SCTRL; /**< I2S Control Register */
+ __IOM uint32_t TIMING; /**< Timing Register */
+ __IOM uint32_t CTRLX; /**< Control Register Extended */
+ __IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */
+ __IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */
+ __IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
+} USART_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_USART
+ * @{
+ * @defgroup EFR32MG1P_USART_BitFields USART Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for USART CTRL */
+#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
+#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */
+#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
+#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
+#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
+#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
+#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
+#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
+#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
+#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
+#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
+#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
+#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
+#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
+#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
+#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
+#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
+#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
+#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
+#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
+#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
+#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
+#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
+#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
+#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
+#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
+#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
+#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
+#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
+#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
+#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
+#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
+#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
+#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
+#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */
+#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
+#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
+#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
+#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
+#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
+#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
+#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
+#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
+#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
+#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */
+#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
+#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
+#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
+#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
+#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
+#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
+#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
+#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
+#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
+#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
+#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
+#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
+#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
+#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
+#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
+#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
+#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */
+#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
+#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
+#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
+#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
+#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
+#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
+#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
+#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
+#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
+#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
+#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
+#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
+#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
+#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
+#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
+#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
+#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
+#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
+#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
+#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
+#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
+#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
+#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
+#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */
+#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
+#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
+#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */
+#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
+#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
+#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */
+#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
+#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
+#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
+#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */
+#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
+#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
+#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
+#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
+#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
+#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
+#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
+#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
+#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
+#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
+
+/* Bit fields for USART FRAME */
+#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
+#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
+#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
+#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
+#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
+#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
+#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
+#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
+#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
+#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
+#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
+#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
+#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
+#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
+#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
+#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
+#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
+#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
+#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
+#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
+#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
+#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
+#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
+#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
+#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
+#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
+#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
+#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
+#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
+#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
+#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
+#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
+#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
+#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
+#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
+#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
+#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
+#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
+
+/* Bit fields for USART TRIGCTRL */
+#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
+#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
+#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
+#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
+#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
+#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
+#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
+#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
+#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
+#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */
+#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
+#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
+#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */
+#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
+#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
+#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */
+#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
+#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
+#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */
+#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
+#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
+#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */
+#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
+#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
+#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */
+#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
+#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
+#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */
+#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */
+#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */
+
+/* Bit fields for USART CMD */
+#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
+#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
+#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
+#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
+#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
+#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
+#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
+#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
+#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
+#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
+#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
+#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
+#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
+#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
+#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
+#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
+#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
+#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
+#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
+#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
+#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
+#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
+#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
+#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
+#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
+#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
+#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
+#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
+#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
+#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
+#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
+#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
+#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
+#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
+#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
+#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
+#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
+#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
+#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
+
+/* Bit fields for USART STATUS */
+#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */
+#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */
+#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
+#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
+#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
+#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
+#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
+#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
+#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
+#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
+#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
+#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
+#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
+#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
+#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
+#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
+#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
+#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
+#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
+#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
+#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
+#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
+#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
+#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
+#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
+#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
+#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
+#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
+#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
+#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
+#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
+#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
+#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
+#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
+#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
+#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
+#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
+#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
+#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
+#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
+#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
+#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
+#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */
+#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
+#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
+#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
+#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
+#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
+#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */
+
+/* Bit fields for USART CLKDIV */
+#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
+#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */
+#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
+#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
+#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */
+#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
+#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
+#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
+
+/* Bit fields for USART RXDATAX */
+#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
+#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
+#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
+#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
+#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
+#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
+#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
+#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
+#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
+#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
+#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
+
+/* Bit fields for USART RXDATA */
+#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
+#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
+#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
+
+/* Bit fields for USART RXDOUBLEX */
+#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
+#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
+#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
+#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
+#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
+#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
+#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
+#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
+#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
+#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
+#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
+#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
+#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
+#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
+#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
+#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
+#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+
+/* Bit fields for USART RXDOUBLE */
+#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
+#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
+#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
+#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
+#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
+
+/* Bit fields for USART RXDATAXP */
+#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
+#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
+#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
+#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
+#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
+#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
+#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
+#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
+#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
+#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
+#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+
+/* Bit fields for USART RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
+#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
+#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
+#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
+#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
+#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
+#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
+#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
+#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
+#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
+#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
+#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
+#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
+#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
+#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
+#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
+#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+
+/* Bit fields for USART TXDATAX */
+#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
+#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
+#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
+#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
+#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
+#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
+#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
+#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
+#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
+#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
+#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
+#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
+#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
+#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
+#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
+#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
+#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
+
+/* Bit fields for USART TXDATA */
+#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
+#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
+#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
+
+/* Bit fields for USART TXDOUBLEX */
+#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
+#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
+#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
+#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
+#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
+#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
+#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
+#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
+#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */
+#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
+#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
+#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
+#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
+#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
+#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
+#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
+#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
+#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
+#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
+#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
+#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
+#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
+#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
+#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
+#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
+#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */
+#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
+#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
+#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
+#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
+#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
+#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
+#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
+#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
+#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+
+/* Bit fields for USART TXDOUBLE */
+#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
+#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
+#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
+#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
+#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
+
+/* Bit fields for USART IF */
+#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
+#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */
+#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
+#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
+#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
+#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
+#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
+#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
+#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
+#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
+#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
+#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
+#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
+#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
+#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
+#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
+#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
+#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
+#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
+#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
+#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
+#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
+#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
+#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
+#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
+#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
+#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
+#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
+#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
+#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
+#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
+#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
+#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
+#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
+#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
+#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */
+#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
+#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
+#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
+#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
+#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
+#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
+#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */
+#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
+#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
+#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */
+#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
+#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
+#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */
+#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
+#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
+#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */
+
+/* Bit fields for USART IFS */
+#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
+#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */
+#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
+#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
+#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
+#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */
+#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
+#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
+#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */
+#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
+#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
+#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */
+#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
+#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
+#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */
+#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
+#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
+#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */
+#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
+#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
+#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */
+#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
+#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
+#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */
+#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
+#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
+#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */
+#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
+#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
+#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */
+#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
+#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
+#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */
+#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
+#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
+#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */
+#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */
+#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
+#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
+#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */
+#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
+#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
+#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */
+#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
+#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
+#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
+#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */
+
+/* Bit fields for USART IFC */
+#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
+#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */
+#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
+#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
+#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
+#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */
+#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
+#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
+#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */
+#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
+#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
+#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */
+#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
+#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
+#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */
+#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
+#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
+#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */
+#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
+#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
+#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */
+#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
+#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
+#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */
+#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
+#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
+#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */
+#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
+#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
+#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */
+#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
+#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
+#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */
+#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
+#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
+#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */
+#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */
+#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
+#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
+#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */
+#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
+#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
+#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */
+#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
+#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
+#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
+#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */
+
+/* Bit fields for USART IEN */
+#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
+#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */
+#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
+#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
+#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
+#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
+#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
+#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
+#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
+#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
+#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
+#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */
+#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
+#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
+#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */
+#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
+#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
+#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */
+#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
+#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
+#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */
+#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
+#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
+#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */
+#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
+#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
+#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */
+#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
+#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
+#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */
+#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
+#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
+#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */
+#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
+#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
+#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */
+#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
+#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
+#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */
+#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
+#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
+#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */
+#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */
+#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
+#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
+#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */
+#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
+#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
+#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */
+#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
+#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
+#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */
+
+/* Bit fields for USART IRCTRL */
+#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
+#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */
+#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
+#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
+#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
+#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
+#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
+#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
+#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
+#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
+#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
+#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
+#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
+#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */
+#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */
+#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */
+#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */
+#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */
+
+/* Bit fields for USART INPUT */
+#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
+#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
+#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
+#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
+#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
+#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */
+#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */
+#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */
+#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
+#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */
+#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */
+#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
+#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */
+#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */
+#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */
+#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */
+#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */
+#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
+#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */
+
+/* Bit fields for USART I2SCTRL */
+#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
+#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
+#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
+#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
+#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
+#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
+#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
+#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
+#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
+#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
+#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
+#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
+#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
+#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */
+#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
+#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
+#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */
+#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
+#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
+#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
+#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
+#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
+
+/* Bit fields for USART TIMING */
+#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */
+#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */
+#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
+#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
+#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
+#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
+#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
+#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
+#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
+#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
+#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
+#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */
+
+/* Bit fields for USART CTRLX */
+#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
+#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
+#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */
+#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
+#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
+#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
+#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
+#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
+#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */
+#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
+#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
+#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
+#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
+#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
+#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */
+
+/* Bit fields for USART TIMECMP0 */
+#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */
+#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
+#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+
+/* Bit fields for USART TIMECMP1 */
+#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */
+#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
+#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+
+/* Bit fields for USART TIMECMP2 */
+#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */
+#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
+#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+
+/* Bit fields for USART ROUTEPEN */
+#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */
+#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
+#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
+#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
+#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
+#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
+#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
+#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */
+#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
+#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
+#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
+#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
+#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
+#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */
+#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */
+#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */
+#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */
+#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */
+#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */
+#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
+#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
+
+/* Bit fields for USART ROUTELOC0 */
+#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */
+#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */
+#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */
+#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */
+#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */
+#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */
+#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */
+#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */
+#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
+#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
+#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
+
+/* Bit fields for USART ROUTELOC1 */
+#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */
+#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */
+#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */
+#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */
+#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
+#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
+#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
+
+/** @} */
+/** @} End of group EFR32MG1P_USART */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_wdog.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_wdog.h
new file mode 100644
index 000000000..4d01ea0ec
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_wdog.h
@@ -0,0 +1,340 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_WDOG register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32MG1P_WDOG WDOG
+ * @{
+ * @brief EFR32MG1P_WDOG Register Declaration
+ ******************************************************************************/
+/** WDOG Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+
+ WDOG_PCH_TypeDef PCH[2U]; /**< PCH */
+
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Watchdog Interrupt Flags */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+} WDOG_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32MG1P_WDOG
+ * @{
+ * @defgroup EFR32MG1P_WDOG_BitFields WDOG Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for WDOG CTRL */
+#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
+#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */
+#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
+#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
+#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
+#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
+#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
+#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
+#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
+#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
+#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
+#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
+#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
+#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
+#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration Lock */
+#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
+#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
+#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
+#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
+#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
+#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
+#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
+#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
+#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
+#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
+#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
+#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
+#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
+#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
+#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
+#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */
+#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */
+#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */
+#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */
+#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */
+#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */
+#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */
+#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */
+#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */
+#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */
+#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */
+#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */
+#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
+#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */
+#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */
+#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */
+
+/* Bit fields for WDOG CMD */
+#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
+#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
+#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
+#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
+#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
+
+/* Bit fields for WDOG SYNCBUSY */
+#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
+#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
+#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
+#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
+#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
+#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */
+#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+
+/* Bit fields for WDOG PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
+#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS Missing Event Will Trigger a Watchdog Reset */
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
+#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
+
+/* Bit fields for WDOG IF */
+#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
+#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
+#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
+#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
+#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
+#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
+#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
+#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
+#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
+#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
+#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */
+#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */
+#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
+
+/* Bit fields for WDOG IFS */
+#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */
+#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */
+#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */
+#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
+#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */
+#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
+#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
+#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */
+#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
+#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
+#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */
+#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */
+#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
+#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
+
+/* Bit fields for WDOG IFC */
+#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */
+#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */
+#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */
+#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
+#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */
+#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
+#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
+#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */
+#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
+#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
+#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */
+#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */
+#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
+#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
+
+/* Bit fields for WDOG IEN */
+#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
+#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
+#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */
+#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
+#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */
+#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
+#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
+#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */
+#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
+#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
+#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */
+#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */
+#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
+
+/** @} */
+/** @} End of group EFR32MG1P_WDOG */
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_wdog_pch.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_wdog_pch.h
new file mode 100644
index 000000000..6c4a33609
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/efr32mg1p_wdog_pch.h
@@ -0,0 +1,49 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32MG1P_WDOG_PCH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief WDOG_PCH WDOG PCH Register
+ * @ingroup EFR32MG1P_WDOG
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t PRSCTRL; /**< PRS Control Register */
+} WDOG_PCH_TypeDef;
+
+/** @} End of group Parts */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/em_device.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/em_device.h
new file mode 100644
index 000000000..a485fa8b0
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/em_device.h
@@ -0,0 +1,104 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
+ * microcontroller devices
+ *
+ * This is a convenience header file for defining the part number on the
+ * build command line, instead of specifying the part specific header file.
+ *
+ * @verbatim
+ * Example: Add "-DEFM32G890F128" to your build options, to define part
+ * Add "#include "em_device.h" to your source files
+ * @endverbatim
+ *
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
+
+#if defined(EFR32MG1P131F256GM48)
+#include "efr32mg1p131f256gm48.h"
+
+#elif defined(EFR32MG1P132F256GJ43)
+#include "efr32mg1p132f256gj43.h"
+
+#elif defined(EFR32MG1P132F256GM32)
+#include "efr32mg1p132f256gm32.h"
+
+#elif defined(EFR32MG1P132F256GM48)
+#include "efr32mg1p132f256gm48.h"
+
+#elif defined(EFR32MG1P132F256IM32)
+#include "efr32mg1p132f256im32.h"
+
+#elif defined(EFR32MG1P132F256IM48)
+#include "efr32mg1p132f256im48.h"
+
+#elif defined(EFR32MG1P133F256GM48)
+#include "efr32mg1p133f256gm48.h"
+
+#elif defined(EFR32MG1P231F256GM48)
+#include "efr32mg1p231f256gm48.h"
+
+#elif defined(EFR32MG1P232F256GJ43)
+#include "efr32mg1p232f256gj43.h"
+
+#elif defined(EFR32MG1P232F256GM32)
+#include "efr32mg1p232f256gm32.h"
+
+#elif defined(EFR32MG1P232F256GM48)
+#include "efr32mg1p232f256gm48.h"
+
+#elif defined(EFR32MG1P232F256IM32)
+#include "efr32mg1p232f256im32.h"
+
+#elif defined(EFR32MG1P232F256IM48)
+#include "efr32mg1p232f256im48.h"
+
+#elif defined(EFR32MG1P233F256GM48)
+#include "efr32mg1p233f256gm48.h"
+
+#elif defined(EFR32MG1P233F256IM48)
+#include "efr32mg1p233f256im48.h"
+
+#elif defined(EFR32MG1P632F256GM32)
+#include "efr32mg1p632f256gm32.h"
+
+#elif defined(EFR32MG1P632F256IM32)
+#include "efr32mg1p632f256im32.h"
+
+#elif defined(EFR32MG1P732F256GM32)
+#include "efr32mg1p732f256gm32.h"
+
+#elif defined(EFR32MG1P732F256IM32)
+#include "efr32mg1p732f256im32.h"
+
+#else
+#error "em_device.h: PART NUMBER undefined"
+#endif
+#endif /* EM_DEVICE_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Include/system_efr32mg1p.h b/gecko/Device/SiliconLabs/EFR32MG1P/Include/system_efr32mg1p.h
new file mode 100644
index 000000000..66b4fc13b
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Include/system_efr32mg1p.h
@@ -0,0 +1,167 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_EFR32_H
+#define SYSTEM_EFR32_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32 EFR32
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
+/*******************************************************************************
+ ************************** GLOBAL VARIABLES *******************************
+ ******************************************************************************/
+
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
+
+/*******************************************************************************
+ ***************************** PROTOTYPES **********************************
+ ******************************************************************************/
+
+void Reset_Handler(void); /**< Reset Handler */
+void NMI_Handler(void); /**< NMI Handler */
+void HardFault_Handler(void); /**< Hard Fault Handler */
+void MemManage_Handler(void); /**< MPU Fault Handler */
+void BusFault_Handler(void); /**< Bus Fault Handler */
+void UsageFault_Handler(void); /**< Usage Fault Handler */
+void SVC_Handler(void); /**< SVCall Handler */
+void DebugMon_Handler(void); /**< Debug Monitor Handler */
+void PendSV_Handler(void); /**< PendSV Handler */
+void SysTick_Handler(void); /**< SysTick Handler */
+
+void EMU_IRQHandler(void); /**< EMU IRQ Handler */
+void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
+void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
+void FRC_IRQHandler(void); /**< FRC IRQ Handler */
+void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
+void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
+void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
+void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
+void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
+void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
+void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
+void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
+void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
+void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
+void ADC0_IRQHandler(void); /**< ADC0 IRQ Handler */
+void IDAC0_IRQHandler(void); /**< IDAC0 IRQ Handler */
+void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
+void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
+void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
+void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */
+void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */
+void LEUART0_IRQHandler(void); /**< LEUART0 IRQ Handler */
+void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
+void CMU_IRQHandler(void); /**< CMU IRQ Handler */
+void MSC_IRQHandler(void); /**< MSC IRQ Handler */
+void CRYPTO_IRQHandler(void); /**< CRYPTO IRQ Handler */
+void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
+void AGC_IRQHandler(void); /**< AGC IRQ Handler */
+void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
+void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */
+void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
+void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */
+void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */
+
+#if (__FPU_PRESENT == 1)
+void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */
+#endif
+
+uint32_t SystemCoreClockGet(void);
+
+/***************************************************************************//**
+ * @brief
+ * Update CMSIS SystemCoreClock variable.
+ *
+ * @details
+ * CMSIS defines a global variable SystemCoreClock that shall hold the
+ * core frequency in Hz. If the core frequency is dynamically changed, the
+ * variable must be kept updated in order to be CMSIS compliant.
+ *
+ * Notice that only if changing the core clock frequency through the EFR CMU
+ * API, this variable will be kept updated. This function is only provided
+ * for CMSIS compliance and if a user modifies the the core clock outside
+ * the CMU API.
+ ******************************************************************************/
+static __INLINE void SystemCoreClockUpdate(void)
+{
+ (void)SystemCoreClockGet();
+}
+
+uint32_t SystemMaxCoreClockGet(void);
+
+void SystemInit(void);
+uint32_t SystemHFClockGet(void);
+
+uint32_t SystemHFXOClockGet(void);
+void SystemHFXOClockSet(uint32_t freq);
+
+uint32_t SystemLFRCOClockGet(void);
+uint32_t SystemULFRCOClockGet(void);
+
+uint32_t SystemLFXOClockGet(void);
+void SystemLFXOClockSet(uint32_t freq);
+
+/** @} End of group */
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SYSTEM_EFR32_H */
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/ARM/startup_efr32mg1p.s b/gecko/Device/SiliconLabs/EFR32MG1P/Source/ARM/startup_efr32mg1p.s
new file mode 100644
index 000000000..3c5694810
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/ARM/startup_efr32mg1p.s
@@ -0,0 +1,300 @@
+;/**************************************************************************//**
+; * @file
+; * @brief CMSIS Core Device Startup File for
+; * Silicon Labs EFR32MG1P Device Series
+; ******************************************************************************
+; * # License
+; *
+; * The licensor of this software is Silicon Laboratories Inc. Your use of this
+; * software is governed by the terms of Silicon Labs Master Software License
+; * Agreement (MSLA) available at
+; * www.silabs.com/about-us/legal/master-software-license-agreement. This
+; * software is Third Party Software licensed by Silicon Labs from a third party
+; * and is governed by the sections of the MSLA applicable to Third Party
+; * Software and the additional terms set forth below.
+; *
+; *****************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ IF :DEF: __STACK_SIZE
+Stack_Size EQU __STACK_SIZE
+ ELSE
+Stack_Size EQU 0x00000400
+ ENDIF
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ IF :DEF: __HEAP_SIZE
+Heap_Size EQU __HEAP_SIZE
+ ELSE
+Heap_Size EQU 0x00000C00
+ ENDIF
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY, ALIGN=8
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD sl_app_properties ; Application properties
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+
+ DCD EMU_IRQHandler ; 0: EMU Interrupt
+ DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt
+ DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt
+ DCD FRC_IRQHandler ; 3: FRC Interrupt
+ DCD MODEM_IRQHandler ; 4: MODEM Interrupt
+ DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt
+ DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt
+ DCD BUFC_IRQHandler ; 7: BUFC Interrupt
+ DCD LDMA_IRQHandler ; 8: LDMA Interrupt
+ DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt
+ DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt
+ DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt
+ DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt
+ DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt
+ DCD ADC0_IRQHandler ; 14: ADC0 Interrupt
+ DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt
+ DCD I2C0_IRQHandler ; 16: I2C0 Interrupt
+ DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt
+ DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt
+ DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt
+ DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt
+ DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt
+ DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt
+ DCD CMU_IRQHandler ; 23: CMU Interrupt
+ DCD MSC_IRQHandler ; 24: MSC Interrupt
+ DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt
+ DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
+ DCD AGC_IRQHandler ; 27: AGC Interrupt
+ DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt
+ DCD RTCC_IRQHandler ; 29: RTCC Interrupt
+ DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt
+ DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt
+ DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt
+ DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt
+
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ EXPORT sl_app_properties [WEAK]
+sl_app_properties ; Provide a dummy value for the sl_app_properties symbol.
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT EMU_IRQHandler [WEAK]
+ EXPORT FRC_PRI_IRQHandler [WEAK]
+ EXPORT WDOG0_IRQHandler [WEAK]
+ EXPORT FRC_IRQHandler [WEAK]
+ EXPORT MODEM_IRQHandler [WEAK]
+ EXPORT RAC_SEQ_IRQHandler [WEAK]
+ EXPORT RAC_RSM_IRQHandler [WEAK]
+ EXPORT BUFC_IRQHandler [WEAK]
+ EXPORT LDMA_IRQHandler [WEAK]
+ EXPORT GPIO_EVEN_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT USART0_RX_IRQHandler [WEAK]
+ EXPORT USART0_TX_IRQHandler [WEAK]
+ EXPORT ACMP0_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT IDAC0_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT GPIO_ODD_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT USART1_RX_IRQHandler [WEAK]
+ EXPORT USART1_TX_IRQHandler [WEAK]
+ EXPORT LEUART0_IRQHandler [WEAK]
+ EXPORT PCNT0_IRQHandler [WEAK]
+ EXPORT CMU_IRQHandler [WEAK]
+ EXPORT MSC_IRQHandler [WEAK]
+ EXPORT CRYPTO_IRQHandler [WEAK]
+ EXPORT LETIMER0_IRQHandler [WEAK]
+ EXPORT AGC_IRQHandler [WEAK]
+ EXPORT PROTIMER_IRQHandler [WEAK]
+ EXPORT RTCC_IRQHandler [WEAK]
+ EXPORT SYNTH_IRQHandler [WEAK]
+ EXPORT CRYOTIMER_IRQHandler [WEAK]
+ EXPORT RFSENSE_IRQHandler [WEAK]
+ EXPORT FPUEH_IRQHandler [WEAK]
+
+
+EMU_IRQHandler
+FRC_PRI_IRQHandler
+WDOG0_IRQHandler
+FRC_IRQHandler
+MODEM_IRQHandler
+RAC_SEQ_IRQHandler
+RAC_RSM_IRQHandler
+BUFC_IRQHandler
+LDMA_IRQHandler
+GPIO_EVEN_IRQHandler
+TIMER0_IRQHandler
+USART0_RX_IRQHandler
+USART0_TX_IRQHandler
+ACMP0_IRQHandler
+ADC0_IRQHandler
+IDAC0_IRQHandler
+I2C0_IRQHandler
+GPIO_ODD_IRQHandler
+TIMER1_IRQHandler
+USART1_RX_IRQHandler
+USART1_TX_IRQHandler
+LEUART0_IRQHandler
+PCNT0_IRQHandler
+CMU_IRQHandler
+MSC_IRQHandler
+CRYPTO_IRQHandler
+LETIMER0_IRQHandler
+AGC_IRQHandler
+PROTIMER_IRQHandler
+RTCC_IRQHandler
+SYNTH_IRQHandler
+CRYOTIMER_IRQHandler
+RFSENSE_IRQHandler
+FPUEH_IRQHandler
+ B .
+ ENDP
+
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/efr32mg1p.ld b/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/efr32mg1p.ld
new file mode 100644
index 000000000..c1a12cab9
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/efr32mg1p.ld
@@ -0,0 +1,229 @@
+/***************************************************************************//**
+ * Linker script for Silicon Labs EFR32MG1P devices
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 31744
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN (4);
+ PROVIDE (__ram_func_section_start = .);
+ *(.ram)
+ PROVIDE (__ram_func_section_end = .);
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ _end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+ /* Check if FLASH usage exceeds FLASH size */
+ ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
+}
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/startup_efr32mg1p.S b/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/startup_efr32mg1p.S
new file mode 100644
index 000000000..a4a82300f
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/startup_efr32mg1p.S
@@ -0,0 +1,332 @@
+/***************************************************************************//**
+ * @file
+ * @brief startup file for Silicon Labs EFR32MG1P devices.
+ * For use with GCC for ARM Embedded Processors
+ *******************************************************************************
+ * # License
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is Third Party Software licensed by Silicon Labs from a third party
+ * and is governed by the sections of the MSLA applicable to Third Party
+ * Software and the additional terms set forth below.
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long sl_app_properties /* Application properties */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long EMU_IRQHandler /* 0 - EMU */
+ .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */
+ .long WDOG0_IRQHandler /* 2 - WDOG0 */
+ .long FRC_IRQHandler /* 3 - FRC */
+ .long MODEM_IRQHandler /* 4 - MODEM */
+ .long RAC_SEQ_IRQHandler /* 5 - RAC_SEQ */
+ .long RAC_RSM_IRQHandler /* 6 - RAC_RSM */
+ .long BUFC_IRQHandler /* 7 - BUFC */
+ .long LDMA_IRQHandler /* 8 - LDMA */
+ .long GPIO_EVEN_IRQHandler /* 9 - GPIO_EVEN */
+ .long TIMER0_IRQHandler /* 10 - TIMER0 */
+ .long USART0_RX_IRQHandler /* 11 - USART0_RX */
+ .long USART0_TX_IRQHandler /* 12 - USART0_TX */
+ .long ACMP0_IRQHandler /* 13 - ACMP0 */
+ .long ADC0_IRQHandler /* 14 - ADC0 */
+ .long IDAC0_IRQHandler /* 15 - IDAC0 */
+ .long I2C0_IRQHandler /* 16 - I2C0 */
+ .long GPIO_ODD_IRQHandler /* 17 - GPIO_ODD */
+ .long TIMER1_IRQHandler /* 18 - TIMER1 */
+ .long USART1_RX_IRQHandler /* 19 - USART1_RX */
+ .long USART1_TX_IRQHandler /* 20 - USART1_TX */
+ .long LEUART0_IRQHandler /* 21 - LEUART0 */
+ .long PCNT0_IRQHandler /* 22 - PCNT0 */
+ .long CMU_IRQHandler /* 23 - CMU */
+ .long MSC_IRQHandler /* 24 - MSC */
+ .long CRYPTO_IRQHandler /* 25 - CRYPTO */
+ .long LETIMER0_IRQHandler /* 26 - LETIMER0 */
+ .long AGC_IRQHandler /* 27 - AGC */
+ .long PROTIMER_IRQHandler /* 28 - PROTIMER */
+ .long RTCC_IRQHandler /* 29 - RTCC */
+ .long SYNTH_IRQHandler /* 30 - SYNTH */
+ .long CRYOTIMER_IRQHandler /* 31 - CRYOTIMER */
+ .long RFSENSE_IRQHandler /* 32 - RFSENSE */
+ .long FPUEH_IRQHandler /* 33 - FPUEH */
+
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+#ifndef __NO_SYSTEM_INIT
+ ldr r0, =SystemInit
+ blx r0
+#endif
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /* __STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __zero_table_start__ and __zero_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+ .weak sl_app_properties
+ .type sl_app_properties, %common
+Default_Handler:
+sl_app_properties: /* Provide a dummy value for the sl_app_properties symbol. */
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers.
+ */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+
+ def_irq_handler EMU_IRQHandler
+ def_irq_handler FRC_PRI_IRQHandler
+ def_irq_handler WDOG0_IRQHandler
+ def_irq_handler FRC_IRQHandler
+ def_irq_handler MODEM_IRQHandler
+ def_irq_handler RAC_SEQ_IRQHandler
+ def_irq_handler RAC_RSM_IRQHandler
+ def_irq_handler BUFC_IRQHandler
+ def_irq_handler LDMA_IRQHandler
+ def_irq_handler GPIO_EVEN_IRQHandler
+ def_irq_handler TIMER0_IRQHandler
+ def_irq_handler USART0_RX_IRQHandler
+ def_irq_handler USART0_TX_IRQHandler
+ def_irq_handler ACMP0_IRQHandler
+ def_irq_handler ADC0_IRQHandler
+ def_irq_handler IDAC0_IRQHandler
+ def_irq_handler I2C0_IRQHandler
+ def_irq_handler GPIO_ODD_IRQHandler
+ def_irq_handler TIMER1_IRQHandler
+ def_irq_handler USART1_RX_IRQHandler
+ def_irq_handler USART1_TX_IRQHandler
+ def_irq_handler LEUART0_IRQHandler
+ def_irq_handler PCNT0_IRQHandler
+ def_irq_handler CMU_IRQHandler
+ def_irq_handler MSC_IRQHandler
+ def_irq_handler CRYPTO_IRQHandler
+ def_irq_handler LETIMER0_IRQHandler
+ def_irq_handler AGC_IRQHandler
+ def_irq_handler PROTIMER_IRQHandler
+ def_irq_handler RTCC_IRQHandler
+ def_irq_handler SYNTH_IRQHandler
+ def_irq_handler CRYOTIMER_IRQHandler
+ def_irq_handler RFSENSE_IRQHandler
+ def_irq_handler FPUEH_IRQHandler
+
+ .end
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/startup_efr32mg1p.c b/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/startup_efr32mg1p.c
new file mode 100644
index 000000000..00801b223
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/GCC/startup_efr32mg1p.c
@@ -0,0 +1,324 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Compatible EFR32MG1P startup file in C.
+ * Should be used with GCC 'GNU Tools ARM Embedded'
+ *******************************************************************************
+ * # License
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is Third Party Software licensed by Silicon Labs from a third party
+ * and is governed by the sections of the MSLA applicable to Third Party
+ * Software and the additional terms set forth below.
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include
+#include "em_device.h" /* The correct device header file. */
+
+/*----------------------------------------------------------------------------
+ * Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+ * External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit(void); /* CMSIS System Initialization */
+#endif
+
+/*----------------------------------------------------------------------------
+ * Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+/*----------------------------------------------------------------------------
+ * User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+#define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+#define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M Processor Exceptions */
+void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+/* Provide a dummy value for the sl_app_properties symbol. */
+void sl_app_properties(void); /* Prototype to please MISRA checkers. */
+void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* Part Specific Interrupts */
+
+void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void IDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CRYPTO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CRYOTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RFSENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const tVectorEntry __Vectors[];
+const tVectorEntry __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M Exception Handlers */
+ { .topOfStack = &__StackTop }, /* Initial Stack Pointer */
+ { Reset_Handler }, /* Reset Handler */
+ { NMI_Handler }, /* NMI Handler */
+ { HardFault_Handler }, /* Hard Fault Handler */
+ { MemManage_Handler }, /* MPU Fault Handler */
+ { BusFault_Handler }, /* Bus Fault Handler */
+ { UsageFault_Handler }, /* Usage Fault Handler */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+ { SVC_Handler }, /* SVCall Handler */
+ { DebugMon_Handler }, /* Debug Monitor Handler */
+ { sl_app_properties }, /* Application properties*/
+ { PendSV_Handler }, /* PendSV Handler */
+ { SysTick_Handler }, /* SysTick Handler */
+
+ /* External interrupts */
+
+ { EMU_IRQHandler }, /* 0 */
+ { FRC_PRI_IRQHandler }, /* 1 */
+ { WDOG0_IRQHandler }, /* 2 */
+ { FRC_IRQHandler }, /* 3 */
+ { MODEM_IRQHandler }, /* 4 */
+ { RAC_SEQ_IRQHandler }, /* 5 */
+ { RAC_RSM_IRQHandler }, /* 6 */
+ { BUFC_IRQHandler }, /* 7 */
+ { LDMA_IRQHandler }, /* 8 */
+ { GPIO_EVEN_IRQHandler }, /* 9 */
+ { TIMER0_IRQHandler }, /* 10 */
+ { USART0_RX_IRQHandler }, /* 11 */
+ { USART0_TX_IRQHandler }, /* 12 */
+ { ACMP0_IRQHandler }, /* 13 */
+ { ADC0_IRQHandler }, /* 14 */
+ { IDAC0_IRQHandler }, /* 15 */
+ { I2C0_IRQHandler }, /* 16 */
+ { GPIO_ODD_IRQHandler }, /* 17 */
+ { TIMER1_IRQHandler }, /* 18 */
+ { USART1_RX_IRQHandler }, /* 19 */
+ { USART1_TX_IRQHandler }, /* 20 */
+ { LEUART0_IRQHandler }, /* 21 */
+ { PCNT0_IRQHandler }, /* 22 */
+ { CMU_IRQHandler }, /* 23 */
+ { MSC_IRQHandler }, /* 24 */
+ { CRYPTO_IRQHandler }, /* 25 */
+ { LETIMER0_IRQHandler }, /* 26 */
+ { AGC_IRQHandler }, /* 27 */
+ { PROTIMER_IRQHandler }, /* 28 */
+ { RTCC_IRQHandler }, /* 29 */
+ { SYNTH_IRQHandler }, /* 30 */
+ { CRYOTIMER_IRQHandler }, /* 31 */
+ { RFSENSE_IRQHandler }, /* 32 */
+ { FPUEH_IRQHandler }, /* 33 */
+};
+
+/*----------------------------------------------------------------------------
+ * Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+ uint32_t start, end;
+ uint32_t tableStart __attribute__((unused));
+ uint32_t tableEnd __attribute__((unused));
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ tableStart = (uint32_t) &__copy_table_start__;
+ tableEnd = (uint32_t) &__copy_table_end__;
+
+ for (; tableStart < tableEnd; tableStart += 12U) {
+ pSrc = (uint32_t *) (*(uint32_t *) tableStart);
+ start = *(uint32_t *) (tableStart + 4U);
+ end = *(uint32_t *) (tableStart + 8U) + start;
+ pDest = (uint32_t *) start;
+ for (; start < end; start += 4U) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+ start = (uint32_t) &__data_start__;
+ end = (uint32_t) &__data_end__;
+
+ for (; start < end; start += 4U) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __zero_table_start__ and __zero_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ tableStart = (uint32_t) &__zero_table_start__;
+ tableEnd = (uint32_t) &__zero_table_end__;
+
+ for (; tableStart < tableEnd; tableStart += 8U) {
+ start = *(uint32_t *) tableStart;
+ end = *(uint32_t *) (tableStart + 4U) + start;
+ pDest = (uint32_t *) start;
+ for (; start < end; start += 4U) {
+ *pDest++ = 0UL;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+ start = (uint32_t) &__bss_start__;
+ end = (uint32_t) &__bss_end__;
+
+ for (; start < end; start += 4U) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+}
+
+/*----------------------------------------------------------------------------
+ * Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while (true) {
+ }
+}
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/IAR/startup_efr32mg1p.c b/gecko/Device/SiliconLabs/EFR32MG1P/Source/IAR/startup_efr32mg1p.c
new file mode 100644
index 000000000..a3647ccfc
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/IAR/startup_efr32mg1p.c
@@ -0,0 +1,370 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Compatible EFR32MG1P startup file in C for IAR EWARM
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include
+#include "em_device.h" /* The correct device header file. */
+
+#pragma language=extended
+#pragma segment="CSTACK"
+
+/* IAR start function */
+extern void __iar_program_start(void);
+/* CMSIS init function */
+extern void SystemInit(void);
+
+/* Auto defined by linker */
+extern unsigned char CSTACK$$Limit;
+
+__weak void Reset_Handler(void)
+{
+ SystemInit();
+ __iar_program_start();
+}
+
+/* Provide a dummy value for the sl_app_properties symbol. */
+void sl_app_properties(void); /* Prototype to please MISRA checkers. */
+__weak void sl_app_properties(void)
+{
+}
+
+__weak void NMI_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void HardFault_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void MemManage_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void BusFault_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void UsageFault_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void SVC_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void DebugMon_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void PendSV_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void SysTick_Handler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void EMU_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void FRC_PRI_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void WDOG0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void FRC_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void MODEM_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void RAC_SEQ_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void RAC_RSM_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void BUFC_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void LDMA_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void GPIO_EVEN_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void TIMER0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void USART0_RX_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void USART0_TX_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void ACMP0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void ADC0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void IDAC0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void I2C0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void GPIO_ODD_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void TIMER1_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void USART1_RX_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void USART1_TX_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void LEUART0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void PCNT0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void CMU_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void MSC_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void CRYPTO_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void LETIMER0_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void AGC_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void PROTIMER_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void RTCC_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void SYNTH_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void CRYOTIMER_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void RFSENSE_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+__weak void FPUEH_IRQHandler(void)
+{
+ while (true) {
+ }
+}
+
+#pragma data_alignment=256
+#pragma location = ".intvec"
+const tVectorEntry __vector_table[] = {
+ { .topOfStack = &CSTACK$$Limit }, /* With IAR, the CSTACK is defined via */
+ /* project options settings */
+
+ { Reset_Handler },
+ { NMI_Handler },
+ { HardFault_Handler },
+ { MemManage_Handler },
+ { BusFault_Handler },
+ { UsageFault_Handler },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { SVC_Handler },
+ { DebugMon_Handler },
+ { sl_app_properties },
+ { PendSV_Handler },
+ { SysTick_Handler },
+ { EMU_IRQHandler }, /* 0 */
+ { FRC_PRI_IRQHandler }, /* 1 */
+ { WDOG0_IRQHandler }, /* 2 */
+ { FRC_IRQHandler }, /* 3 */
+ { MODEM_IRQHandler }, /* 4 */
+ { RAC_SEQ_IRQHandler }, /* 5 */
+ { RAC_RSM_IRQHandler }, /* 6 */
+ { BUFC_IRQHandler }, /* 7 */
+ { LDMA_IRQHandler }, /* 8 */
+ { GPIO_EVEN_IRQHandler }, /* 9 */
+ { TIMER0_IRQHandler }, /* 10 */
+ { USART0_RX_IRQHandler }, /* 11 */
+ { USART0_TX_IRQHandler }, /* 12 */
+ { ACMP0_IRQHandler }, /* 13 */
+ { ADC0_IRQHandler }, /* 14 */
+ { IDAC0_IRQHandler }, /* 15 */
+ { I2C0_IRQHandler }, /* 16 */
+ { GPIO_ODD_IRQHandler }, /* 17 */
+ { TIMER1_IRQHandler }, /* 18 */
+ { USART1_RX_IRQHandler }, /* 19 */
+ { USART1_TX_IRQHandler }, /* 20 */
+ { LEUART0_IRQHandler }, /* 21 */
+ { PCNT0_IRQHandler }, /* 22 */
+ { CMU_IRQHandler }, /* 23 */
+ { MSC_IRQHandler }, /* 24 */
+ { CRYPTO_IRQHandler }, /* 25 */
+ { LETIMER0_IRQHandler }, /* 26 */
+ { AGC_IRQHandler }, /* 27 */
+ { PROTIMER_IRQHandler }, /* 28 */
+ { RTCC_IRQHandler }, /* 29 */
+ { SYNTH_IRQHandler }, /* 30 */
+ { CRYOTIMER_IRQHandler }, /* 31 */
+ { RFSENSE_IRQHandler }, /* 32 */
+ { FPUEH_IRQHandler }, /* 33 */
+};
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/IAR/startup_efr32mg1p.s b/gecko/Device/SiliconLabs/EFR32MG1P/Source/IAR/startup_efr32mg1p.s
new file mode 100644
index 000000000..3485af3b3
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/IAR/startup_efr32mg1p.s
@@ -0,0 +1,367 @@
+;/**************************************************************************//**
+; * @file
+; * @brief CMSIS Core Device Startup File
+; * Silicon Labs EFR32MG1P Device Series
+; ******************************************************************************
+; * # License
+; *
+; * The licensor of this software is Silicon Laboratories Inc. Your use of this
+; * software is governed by the terms of Silicon Labs Master Software License
+; * Agreement (MSLA) available at
+; * www.silabs.com/about-us/legal/master-software-license-agreement. This
+; * software is Third Party Software licensed by Silicon Labs from a third party
+; * and is governed by the sections of the MSLA applicable to Third Party
+; * Software and the additional terms set forth below.
+; *
+; *****************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+;
+; When debugging in RAM, it can be located in RAM with at least a 128 byte
+; alignment, 256 byte alignment is requied if all interrupt vectors are in use.
+;
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(8)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD sl_app_properties
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+
+ DCD EMU_IRQHandler ; 0: EMU Interrupt
+ DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt
+ DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt
+ DCD FRC_IRQHandler ; 3: FRC Interrupt
+ DCD MODEM_IRQHandler ; 4: MODEM Interrupt
+ DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt
+ DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt
+ DCD BUFC_IRQHandler ; 7: BUFC Interrupt
+ DCD LDMA_IRQHandler ; 8: LDMA Interrupt
+ DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt
+ DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt
+ DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt
+ DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt
+ DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt
+ DCD ADC0_IRQHandler ; 14: ADC0 Interrupt
+ DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt
+ DCD I2C0_IRQHandler ; 16: I2C0 Interrupt
+ DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt
+ DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt
+ DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt
+ DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt
+ DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt
+ DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt
+ DCD CMU_IRQHandler ; 23: CMU Interrupt
+ DCD MSC_IRQHandler ; 24: MSC Interrupt
+ DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt
+ DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
+ DCD AGC_IRQHandler ; 27: AGC Interrupt
+ DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt
+ DCD RTCC_IRQHandler ; 29: RTCC Interrupt
+ DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt
+ DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt
+ DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt
+ DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK sl_app_properties
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+sl_app_properties ; Provide a dummy value for the sl_app_properties symbol.
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ ; Device specific interrupt handlers
+
+ PUBWEAK EMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EMU_IRQHandler
+ B EMU_IRQHandler
+
+ PUBWEAK FRC_PRI_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FRC_PRI_IRQHandler
+ B FRC_PRI_IRQHandler
+
+ PUBWEAK WDOG0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WDOG0_IRQHandler
+ B WDOG0_IRQHandler
+
+ PUBWEAK FRC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FRC_IRQHandler
+ B FRC_IRQHandler
+
+ PUBWEAK MODEM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MODEM_IRQHandler
+ B MODEM_IRQHandler
+
+ PUBWEAK RAC_SEQ_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RAC_SEQ_IRQHandler
+ B RAC_SEQ_IRQHandler
+
+ PUBWEAK RAC_RSM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RAC_RSM_IRQHandler
+ B RAC_RSM_IRQHandler
+
+ PUBWEAK BUFC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BUFC_IRQHandler
+ B BUFC_IRQHandler
+
+ PUBWEAK LDMA_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LDMA_IRQHandler
+ B LDMA_IRQHandler
+
+ PUBWEAK GPIO_EVEN_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_EVEN_IRQHandler
+ B GPIO_EVEN_IRQHandler
+
+ PUBWEAK TIMER0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+ B TIMER0_IRQHandler
+
+ PUBWEAK USART0_RX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART0_RX_IRQHandler
+ B USART0_RX_IRQHandler
+
+ PUBWEAK USART0_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART0_TX_IRQHandler
+ B USART0_TX_IRQHandler
+
+ PUBWEAK ACMP0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ACMP0_IRQHandler
+ B ACMP0_IRQHandler
+
+ PUBWEAK ADC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC0_IRQHandler
+ B ADC0_IRQHandler
+
+ PUBWEAK IDAC0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+IDAC0_IRQHandler
+ B IDAC0_IRQHandler
+
+ PUBWEAK I2C0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C0_IRQHandler
+ B I2C0_IRQHandler
+
+ PUBWEAK GPIO_ODD_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_ODD_IRQHandler
+ B GPIO_ODD_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK USART1_RX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_RX_IRQHandler
+ B USART1_RX_IRQHandler
+
+ PUBWEAK USART1_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_TX_IRQHandler
+ B USART1_TX_IRQHandler
+
+ PUBWEAK LEUART0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LEUART0_IRQHandler
+ B LEUART0_IRQHandler
+
+ PUBWEAK PCNT0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PCNT0_IRQHandler
+ B PCNT0_IRQHandler
+
+ PUBWEAK CMU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CMU_IRQHandler
+ B CMU_IRQHandler
+
+ PUBWEAK MSC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MSC_IRQHandler
+ B MSC_IRQHandler
+
+ PUBWEAK CRYPTO_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CRYPTO_IRQHandler
+ B CRYPTO_IRQHandler
+
+ PUBWEAK LETIMER0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+LETIMER0_IRQHandler
+ B LETIMER0_IRQHandler
+
+ PUBWEAK AGC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AGC_IRQHandler
+ B AGC_IRQHandler
+
+ PUBWEAK PROTIMER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PROTIMER_IRQHandler
+ B PROTIMER_IRQHandler
+
+ PUBWEAK RTCC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RTCC_IRQHandler
+ B RTCC_IRQHandler
+
+ PUBWEAK SYNTH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SYNTH_IRQHandler
+ B SYNTH_IRQHandler
+
+ PUBWEAK CRYOTIMER_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CRYOTIMER_IRQHandler
+ B CRYOTIMER_IRQHandler
+
+ PUBWEAK RFSENSE_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+RFSENSE_IRQHandler
+ B RFSENSE_IRQHandler
+
+ PUBWEAK FPUEH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FPUEH_IRQHandler
+ B FPUEH_IRQHandler
+
+
+ END
diff --git a/gecko/Device/SiliconLabs/EFR32MG1P/Source/system_efr32mg1p.c b/gecko/Device/SiliconLabs/EFR32MG1P/Source/system_efr32mg1p.c
new file mode 100644
index 000000000..c7dae5f56
--- /dev/null
+++ b/gecko/Device/SiliconLabs/EFR32MG1P/Source/system_efr32mg1p.c
@@ -0,0 +1,395 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include
+#include "em_device.h"
+
+/*******************************************************************************
+ ****************************** DEFINES ************************************
+ ******************************************************************************/
+
+/** LFRCO frequency, tuned to below frequency during manufacturing. */
+#define EFR32_LFRCO_FREQ (32768UL)
+/** ULFRCO frequency */
+#define EFR32_ULFRCO_FREQ (1000UL)
+
+/*******************************************************************************
+ ************************** LOCAL VARIABLES ********************************
+ ******************************************************************************/
+
+/* System oscillator frequencies. These frequencies are normally constant */
+/* for a target, but they are made configurable in order to allow run-time */
+/* handling of different boards. The crystal oscillator clocks can be set */
+/* compile time to a non-default value by defining respective EFR32_nFXO_FREQ */
+/* values according to board design. By defining the EFR32_nFXO_FREQ to 0, */
+/* one indicates that the oscillator is not present, in order to save some */
+/* SW footprint. */
+
+#ifndef EFR32_HFRCO_MAX_FREQ
+/** Maximum HFRCO frequency */
+#define EFR32_HFRCO_MAX_FREQ (38000000UL)
+#endif
+
+#ifndef EFR32_HFXO_FREQ
+/** HFXO frequency */
+#define EFR32_HFXO_FREQ (38400000UL)
+#endif
+
+#ifndef EFR32_HFRCO_STARTUP_FREQ
+/** HFRCO startup frequency */
+#define EFR32_HFRCO_STARTUP_FREQ (19000000UL)
+#endif
+
+/* Do not define variable if HF crystal oscillator not present */
+#if (EFR32_HFXO_FREQ > 0U)
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** System HFXO clock. */
+static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ;
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
+#endif
+
+#ifndef EFR32_LFXO_FREQ
+/** LFXO frequency */
+#define EFR32_LFXO_FREQ (EFR32_LFRCO_FREQ)
+#endif
+/* Do not define variable if LF crystal oscillator not present */
+#if (EFR32_LFXO_FREQ > 0U)
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** System LFXO clock. */
+static uint32_t SystemLFXOClock = EFR32_LFXO_FREQ;
+/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
+#endif
+
+/*******************************************************************************
+ ************************** GLOBAL VARIABLES *******************************
+ ******************************************************************************/
+
+/**
+ * @brief
+ * System System Clock Frequency (Core Clock).
+ *
+ * @details
+ * Required CMSIS global variable that must be kept up-to-date.
+ */
+uint32_t SystemCoreClock = EFR32_HFRCO_STARTUP_FREQ;
+
+/**
+ * @brief
+ * System HFRCO frequency
+ *
+ * @note
+ * This is an EFR32 proprietary variable, not part of the CMSIS definition.
+ *
+ * @details
+ * Frequency of the system HFRCO oscillator
+ */
+uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ;
+
+/*******************************************************************************
+ ************************** GLOBAL FUNCTIONS *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ * Get the current core clock frequency.
+ *
+ * @details
+ * Calculate and get the current core clock frequency based on the current
+ * configuration. Assuming that the SystemCoreClock global variable is
+ * maintained, the core clock frequency is stored in that variable as well.
+ * This function will however calculate the core clock based on actual HW
+ * configuration. It will also update the SystemCoreClock global variable.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * The current core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemCoreClockGet(void)
+{
+ uint32_t ret;
+ uint32_t presc;
+
+ ret = SystemHFClockGet();
+ presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
+ >> _CMU_HFCOREPRESC_PRESC_SHIFT;
+ ret /= presc + 1U;
+
+ /* Keep CMSIS system clock variable up-to-date */
+ SystemCoreClock = ret;
+
+ return ret;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the maximum core clock frequency.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+#if (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ)
+ return EFR32_HFRCO_MAX_FREQ;
+#else
+ return EFR32_HFXO_FREQ;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the current HFCLK frequency.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * The current HFCLK frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemHFClockGet(void)
+{
+ uint32_t ret;
+
+ switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) {
+ case CMU_HFCLKSTATUS_SELECTED_LFXO:
+#if (EFR32_LFXO_FREQ > 0U)
+ ret = SystemLFXOClock;
+#else
+ /* We should not get here, since core should not be clocked. May */
+ /* be caused by a misconfiguration though. */
+ ret = 0U;
+#endif
+ break;
+
+ case CMU_HFCLKSTATUS_SELECTED_LFRCO:
+ ret = EFR32_LFRCO_FREQ;
+ break;
+
+ case CMU_HFCLKSTATUS_SELECTED_HFXO:
+#if (EFR32_HFXO_FREQ > 0U)
+ ret = SystemHFXOClock;
+#else
+ /* We should not get here, since core should not be clocked. May */
+ /* be caused by a misconfiguration though. */
+ ret = 0U;
+#endif
+ break;
+
+ default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
+ ret = SystemHfrcoFreq;
+ break;
+ }
+
+ return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
+ >> _CMU_HFPRESC_PRESC_SHIFT));
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * HFXO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemHFXOClockGet(void)
+{
+ /* External crystal oscillator present? */
+#if (EFR32_HFXO_FREQ > 0U)
+ return SystemHFXOClock;
+#else
+ return 0U;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This function is mainly provided for being able to handle target systems
+ * with different HF crystal oscillator frequencies run-time. If used, it
+ * should probably only be used once during system startup.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @param[in] freq
+ * HFXO frequency in Hz used for target.
+ ******************************************************************************/
+void SystemHFXOClockSet(uint32_t freq)
+{
+ /* External crystal oscillator present? */
+#if (EFR32_HFXO_FREQ > 0U)
+ SystemHFXOClock = freq;
+
+ /* Update core clock frequency if HFXO is used to clock core */
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
+ == CMU_HFCLKSTATUS_SELECTED_HFXO) {
+ /* The function will update the global variable */
+ (void)SystemCoreClockGet();
+ }
+#else
+ (void)freq; /* Unused parameter */
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ * Initialize the system.
+ *
+ * @details
+ * Do required generic HW system init.
+ *
+ * @note
+ * This function is invoked during system init, before the main() routine
+ * and any data has been initialized. For this reason, it cannot do any
+ * initialization of variables etc.
+ ******************************************************************************/
+void SystemInit(void)
+{
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)&__Vectors;
+#endif
+
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Set floating point coprosessor access mode. */
+ SCB->CPACR |= ((3UL << 10 * 2) /* set CP10 Full Access */
+ | (3UL << 11 * 2)); /* set CP11 Full Access */
+#endif
+
+#if defined(UNALIGNED_SUPPORT_DISABLE)
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /****************************
+ * Fix for errata DCDC_E206
+ * Enable bypass switch as errata workaround. The bypass current limit will be
+ * disabled again in CHIP_Init() to avoid added current consumption. */
+
+ EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT;
+ EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK)
+ | EMU_DCDCCTRL_DCDCMODE_BYPASS;
+ *(volatile uint32_t *)(0x400E3074) &= ~(0x1UL << 0);
+ *(volatile uint32_t *)(0x400E3060) &= ~(0x1UL << 28);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * LFRCO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemLFRCOClockGet(void)
+{
+ /* Currently we assume that this frequency is properly tuned during */
+ /* manufacturing and is not changed after reset. If future requirements */
+ /* for re-tuning by user, we can add support for that. */
+ return EFR32_LFRCO_FREQ;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get ultra low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * ULFRCO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemULFRCOClockGet(void)
+{
+ /* The ULFRCO frequency is not tuned, and can be very inaccurate */
+ return EFR32_ULFRCO_FREQ;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @return
+ * LFXO frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemLFXOClockGet(void)
+{
+ /* External crystal oscillator present? */
+#if (EFR32_LFXO_FREQ > 0U)
+ return SystemLFXOClock;
+#else
+ return 0U;
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This function is mainly provided for being able to handle target systems
+ * with different HF crystal oscillator frequencies run-time. If used, it
+ * should probably only be used once during system startup.
+ *
+ * @note
+ * This is an EFR32 proprietary function, not part of the CMSIS definition.
+ *
+ * @param[in] freq
+ * LFXO frequency in Hz used for target.
+ ******************************************************************************/
+void SystemLFXOClockSet(uint32_t freq)
+{
+ /* External crystal oscillator present? */
+#if (EFR32_LFXO_FREQ > 0U)
+ SystemLFXOClock = freq;
+
+ /* Update core clock frequency if LFXO is used to clock core */
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
+ == CMU_HFCLKSTATUS_SELECTED_LFXO) {
+ /* The function will update the global variable */
+ (void)SystemCoreClockGet();
+ }
+#else
+ (void)freq; /* Unused parameter */
+#endif
+}