|
| 1 | +/* |
| 2 | + * Copyright (c) 2026, Niklas Hauser |
| 3 | + * |
| 4 | + * This file is part of the modm project. |
| 5 | + * |
| 6 | + * This Source Code Form is subject to the terms of the Mozilla Public |
| 7 | + * License, v. 2.0. If a copy of the MPL was not distributed with this |
| 8 | + * file, You can obtain one at http://mozilla.org/MPL/2.0/. |
| 9 | + */ |
| 10 | +// ---------------------------------------------------------------------------- |
| 11 | + |
| 12 | +#pragma once |
| 13 | + |
| 14 | +#include <modm/architecture/interface/spi_device.hpp> |
| 15 | +#include <modm/architecture/interface/i2c_device.hpp> |
| 16 | +#include <modm/processing/fiber.hpp> |
| 17 | + |
| 18 | +namespace modm |
| 19 | +{ |
| 20 | + |
| 21 | +/** |
| 22 | + * MAX14661 I2C Transport Layer. |
| 23 | + * |
| 24 | + * In I2C mode the switches of each bank are updated through the shadow |
| 25 | + * registers: the desired 16-bit channel mask is written into the two |
| 26 | + * shadow registers of a bank, and then the "copy shadow registers to |
| 27 | + * switches" command is issued for that bank. There is no command that |
| 28 | + * copies both banks at once, so bank A and bank B always have to be |
| 29 | + * updated with two separate register writes. |
| 30 | + * |
| 31 | + * The I2C interface is compliant with Fast Mode (up to 400kHz). The slave |
| 32 | + * address is configured by the A0/A1 pins. |
| 33 | + * |
| 34 | + * @see Max14661 |
| 35 | + * |
| 36 | + * @ingroup modm_driver_max14661 |
| 37 | + * @author Niklas Hauser |
| 38 | + */ |
| 39 | +template < class I2cMaster > |
| 40 | +class Max14661TransportI2c : public modm::I2cDevice< I2cMaster > |
| 41 | +{ |
| 42 | +public: |
| 43 | + Max14661TransportI2c(uint8_t address) : I2cDevice<I2cMaster>(address) {} |
| 44 | + |
| 45 | +protected: |
| 46 | + /// Write the 16-bit channel mask into the bank A shadow registers |
| 47 | + /// and copy them to the bank A switches. |
| 48 | + bool |
| 49 | + writeChannelsA(uint16_t mask) |
| 50 | + { |
| 51 | + // SHDW0/SHDW1 = 0x10/0x11, CMD_A = 0x14 |
| 52 | + return writeShadow(0x10, 0x14, mask); |
| 53 | + } |
| 54 | + |
| 55 | + /// Write the 16-bit channel mask into the bank B shadow registers |
| 56 | + /// and copy them to the bank B switches. |
| 57 | + bool |
| 58 | + writeChannelsB(uint16_t mask) |
| 59 | + { |
| 60 | + // SHDW2/SHDW3 = 0x12/0x13, CMD_B = 0x15 |
| 61 | + return writeShadow(0x12, 0x15, mask); |
| 62 | + } |
| 63 | + |
| 64 | +private: |
| 65 | + bool |
| 66 | + writeShadow(uint8_t shadowRegister, uint8_t commandRegister, uint16_t mask) |
| 67 | + { |
| 68 | + // SHDWx: low byte, SHDWx+1: high byte, auto-incrementing register address |
| 69 | + buffer[0] = shadowRegister; |
| 70 | + buffer[1] = uint8_t(mask); |
| 71 | + buffer[2] = uint8_t(mask >> 8); |
| 72 | + if (not this->write(buffer, 3)) |
| 73 | + return false; |
| 74 | + |
| 75 | + // 0b10001 = copy shadow registers of this bank to the switches |
| 76 | + buffer[0] = commandRegister; |
| 77 | + buffer[1] = 0b10001; |
| 78 | + return this->write(buffer, 2); |
| 79 | + } |
| 80 | + |
| 81 | + uint8_t buffer[3]; |
| 82 | +}; |
| 83 | + |
| 84 | +/** |
| 85 | + * MAX14661 SPI Transport Layer. |
| 86 | + * |
| 87 | + * In SPI mode the MAX14661 has no addressable registers: it is a plain |
| 88 | + * 32-bit shift register and all 32 switches (16 of bank A, 16 of bank B) |
| 89 | + * are transitioned simultaneously on the rising edge of CS. This transport |
| 90 | + * therefore caches both channel masks locally and always shifts out the |
| 91 | + * complete 32-bit word, so that updating one bank does not disturb the |
| 92 | + * other. |
| 93 | + * |
| 94 | + * The SPI interface requires Mode3 and can be clocked with up to ~10MHz. |
| 95 | + * |
| 96 | + * @see Max14661 |
| 97 | + * |
| 98 | + * @tparam Cs connected chip select pin |
| 99 | + * |
| 100 | + * @ingroup modm_driver_max14661 |
| 101 | + * @author Niklas Hauser |
| 102 | + */ |
| 103 | +template < class SpiMaster, class Cs > |
| 104 | +class Max14661TransportSpi : public modm::SpiDevice< SpiMaster > |
| 105 | +{ |
| 106 | +public: |
| 107 | + Max14661TransportSpi(uint8_t) |
| 108 | + { |
| 109 | + Cs::setOutput(modm::Gpio::High); |
| 110 | + } |
| 111 | + |
| 112 | +protected: |
| 113 | + /// Set the bank A channel mask and shift the complete 32-bit switch |
| 114 | + /// state into the device. |
| 115 | + bool |
| 116 | + writeChannelsA(uint16_t mask) |
| 117 | + { |
| 118 | + maskA = mask; |
| 119 | + return writeShiftRegister(); |
| 120 | + } |
| 121 | + |
| 122 | + /// Set the bank B channel mask and shift the complete 32-bit switch |
| 123 | + /// state into the device. |
| 124 | + bool |
| 125 | + writeChannelsB(uint16_t mask) |
| 126 | + { |
| 127 | + maskB = mask; |
| 128 | + return writeShiftRegister(); |
| 129 | + } |
| 130 | + |
| 131 | +private: |
| 132 | + bool |
| 133 | + writeShiftRegister() |
| 134 | + { |
| 135 | + modm::this_fiber::poll([&]{ return this->acquireMaster(); }); |
| 136 | + Cs::reset(); |
| 137 | + |
| 138 | + // Table 4: SW16B..SW09B, SW08B..SW01B, SW16A..SW09A, SW08A..SW01A |
| 139 | + const uint8_t buffer[4] |
| 140 | + { |
| 141 | + uint8_t(maskB >> 8), |
| 142 | + uint8_t(maskB), |
| 143 | + uint8_t(maskA >> 8), |
| 144 | + uint8_t(maskA), |
| 145 | + }; |
| 146 | + SpiMaster::transfer(buffer, nullptr, 4); |
| 147 | + |
| 148 | + if (this->releaseMaster()) |
| 149 | + Cs::set(); |
| 150 | + |
| 151 | + return true; |
| 152 | + } |
| 153 | + |
| 154 | + uint16_t maskA{0}; |
| 155 | + uint16_t maskB{0}; |
| 156 | +}; |
| 157 | + |
| 158 | +} // namespace modm |
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