[rcc] Add HSE prescaler to RTC clock source

Author: salkinium

src/modm/platform/clock/stm32/module.lb

@@ -89,6 +89,10 @@ def build(env):
         (target["family"] == "l4" and target["name"][0] in ["p", "q", "r", "s"])
     properties["pllsai_p_usb"] = (target["family"] == "f7") or \
         ((target["family"] == "f4") and target["name"] in ["46", "69", "79"])
+    properties["rtcpre"] = target.family in ["f2", "f4", "f7", "h7", "l0", "l1"]
+    properties["cfgr_rtc"] = "CR" if target.family in ["l0", "l1"] else \
+        ("CFGR1" if target.family in ["h5"]  else "CFGR")
+
 
     if target.family in ["h7"]:
         if target.name in ["a3", "b0", "b3"]:

src/modm/platform/clock/stm32/rcc.hpp.in

@@ -204,6 +204,16 @@ public:
 		LowSpeedExternalClock = Lse,
 		LowSpeedExternalCrystal = Lse
 	};
+%% if target.family in ["l0", "l1"]
+	enum class
+	RealTimeClockHsePrescaler : uint8_t
+	{
+		Div2 = 0,
+		Div4 = 1,
+		Div8 = 2,
+		Div16 = 3,
+	};
+%% endif
 
 	enum class
 	WatchdogClockSource : uint32_t
@@ -788,8 +798,11 @@ public:
 	enableSystemClock(SystemClockSource src, uint32_t waitCycles = 2048);
 
 	static inline bool
-	enableRealTimeClock(RealTimeClockSource src)
+	enableRealTimeClock(RealTimeClockSource src{% if rtcpre %}, {% if target.family in ["l0", "l1"] %}RealTimeClockHsePrescaler hseDiv = RealTimeClockHsePrescaler::Div16{% else %}uint8_t hseDiv = 0xff{% endif %}{% endif %})
 	{
+%% if rtcpre
+		RCC->{{cfgr_rtc}} = (RCC->{{cfgr_rtc}} & ~RCC_{{cfgr_rtc}}_RTCPRE_Msk) | ((uint8_t(hseDiv) << RCC_{{cfgr_rtc}}_RTCPRE_Pos) & RCC_{{cfgr_rtc}}_RTCPRE_Msk);
+%% endif
 		RCC->{{bdcr}} = (RCC->{{bdcr}} & ~RCC_{{bdcr}}_RTCSEL) | RCC_{{bdcr}}_RTCEN | uint32_t(src);
 		return true;
 	}