diff --git a/README.md b/README.md index e189b10..6c3bdd5 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ -# vck5000_vivado_custom_ulp_design -An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000 +# vck5000_vivado_ulp +Vivado ulp design example for the User Logic Partition targeting VCK5000 ## Description @@ -133,7 +133,10 @@ After the Vivado project build completes, a platform device image will be genera ``` cp xcl_generator/ulp.xclbin host_sw_with_aie/ -cd host_sw_with_aie +cd aie_core_elf +# Generate ELF file for AIE core +make compile +cd ../host_sw_with_aie make compile make run ``` diff --git a/constrs/_user_impl_clk.xdc b/constrs/_user_impl_clk.xdc index 652a65d..e534ef2 100644 --- a/constrs/_user_impl_clk.xdc +++ b/constrs/_user_impl_clk.xdc @@ -4,8 +4,8 @@ # 500 MHz create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 150 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 # 400 MHz -create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 120 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 +#create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 120 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 # 300 MHz -create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 90 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 +#create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 90 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 # 200 MHz -create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 60 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 +#create_generated_clock -name clkwiz_aclk_kernel_00_clk_out1 -divide_by 10 -multiply_by 60 -source top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKIN1 top_i/blp/blp_logic/ulp_clocking/clkwiz_aclk_kernel_00/inst/clock_primitive_inst/MMCME5_inst/CLKOUT0 diff --git a/ulp_bd_with_aie_16.tcl b/ulp_bd_with_aie_16.tcl index f1c0a32..de1a56c 100644 --- a/ulp_bd_with_aie_16.tcl +++ b/ulp_bd_with_aie_16.tcl @@ -1,6 +1,6 @@ ################################################################ -# This is a generated script based on design: ulp +# This is a generated script based on design: ulp_inst_0 # # Though there are limitations about the generated script, # the main purpose of this utility is to make learning @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2021.2 +set scripts_vivado_version 2022.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -35,12 +35,11 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ################################################################ # To test this script, run the following commands from Vivado Tcl console: -# source ulp_script.tcl +# source ulp_inst_0_script.tcl # If there is no project opened, this script will create a # project, but make sure you do not have an existing project # <./myproj/project_1.xpr> in the current working folder. - set kernel [lindex $argv 0] set list_projs [get_projects -quiet] @@ -49,11 +48,13 @@ if { $list_projs eq "" } { set_property BOARD_PART xilinx.com:vck5000:part0:1.0 [current_project] } + source setup_ip_repos.tcl + # CHANGE DESIGN NAME HERE variable design_name -set design_name ulp +set design_name ulp_inst_0 # If you do not already have an existing IP Integrator design open, # you can create a design using the following command: @@ -106,7 +107,7 @@ if { ${design_name} eq "" } { common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - create_bd_design $design_name + create_bd_design -bdsource Vitis $design_name common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name @@ -129,19 +130,18 @@ if { $bCheckIPs == 1 } { set list_check_ips "\ xilinx.com:ip:ai_engine:2.0\ xilinx.com:ip:axi_bram_ctrl:4.1\ +xilinx.com:ip:axi_firewall:1.2\ +xilinx.com:ip:axi_dbg_hub:2.0\ xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:smartconnect:1.0\ xilinx.com:ip:axi_noc:1.0\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:RTLKernel:data_mover_mm2mm:1.0\ xilinx.com:ip:emb_mem_gen:1.0\ -xilinx.com:ip:shell_utils_frequency_counter:1.0\ -xilinx.com:ip:util_ds_buf:2.2\ -xilinx.com:ip:ii_level0_wire:1.0\ -xilinx.com:RTLKernel:${kernel}:1.0\ -xilinx.com:ip:pipeline_reg:1.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:util_ff:1.0\ +xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:smartconnect:1.0\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:gt_bridge_ip:1.1\ -xilinx.com:ip:gt_quad_base:1.1\ " set list_ips_missing "" @@ -171,13 +171,13 @@ if { $bCheckIPsPassed != 1 } { ################################################################## -# Hierarchical cell: gt_null1 -proc create_hier_cell_gt_null1 { parentCell nameHier } { +# Hierarchical cell: reset_controllers +proc create_hier_cell_reset_controllers { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_gt_null1() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_reset_controllers() - Empty argument(s)!"} return } @@ -206,65 +206,94 @@ proc create_hier_cell_gt_null1 { parentCell nameHier } { current_bd_instance $hier_obj # Create interface pins - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT_Serial - # Create pins - create_bd_pin -dir I -type clk gt_refclk - - # Create instance: gt_bridge_ip, and set properties - set gt_bridge_ip [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_bridge_ip:1.1 gt_bridge_ip ] - set_property -dict [ list \ - CONFIG.IP_NO_OF_LANES {1} \ - ] $gt_bridge_ip - - # Create instance: gt_quad_base, and set properties - set gt_quad_base [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_quad_base:1.1 gt_quad_base ] - set_property -dict [ list \ - CONFIG.PORTS_INFO_DICT {\ - LANE_SEL_DICT {PROT0 {RX0 TX0} unconnected {RX1 RX2 RX3 TX1 TX2 TX3}}\ - GT_TYPE {GTY}\ - REG_CONF_INTF {APB3_INTF}\ - BOARD_PARAMETER {}\ - } \ - CONFIG.PROT0_GT_DIRECTION {DUPLEX} \ - CONFIG.PROT0_NO_OF_LANES {1} \ - CONFIG.PROT0_PRESET {None} \ - CONFIG.PROT0_RX_MASTERCLK_SRC {RX0} \ - CONFIG.PROT0_TX_MASTERCLK_SRC {TX0} \ - CONFIG.PROT_OUTCLK_VALUES {\ -CH0_RXOUTCLK 322.266 CH0_TXOUTCLK 322.266 CH1_RXOUTCLK 390.625 CH1_TXOUTCLK\ -390.625 CH2_RXOUTCLK 390.625 CH2_TXOUTCLK 390.625 CH3_RXOUTCLK 390.625\ -CH3_TXOUTCLK 390.625} \ - CONFIG.REFCLK_STRING {HSCLK0_LCPLLGTREFCLK0 refclk_PROT0_R0_156.25_MHz_unique1} \ - ] $gt_quad_base + create_bd_pin -dir I -type clk clk_kernel0 + create_bd_pin -dir I -type clk clk_kernel1 + create_bd_pin -dir I -type clk clk_pcie + create_bd_pin -dir I -type clk clk_pl_axi + create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_kernel0_ic + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_kernel1_ic + create_bd_pin -dir I -type rst resetn_pcie + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pcie_axi + create_bd_pin -dir O -from 0 -to 0 -type rst resetn_pl_axi + create_bd_pin -dir I -type rst resetn_ulp + + # Create instance: pipereg_kernel0, and set properties + set pipereg_kernel0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 pipereg_kernel0 ] + + # Create instance: pipereg_kernel1, and set properties + set pipereg_kernel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 pipereg_kernel1 ] + + # Create instance: pipereg_pcie0, and set properties + set pipereg_pcie0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 pipereg_pcie0 ] + + # Create instance: pipereg_pl_axi0, and set properties + set pipereg_pl_axi0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 pipereg_pl_axi0 ] + + # Create instance: reset_sync_fixed, and set properties + set reset_sync_fixed [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 reset_sync_fixed ] + set_property -dict [list \ + CONFIG.C_AUX_RESET_HIGH {0} \ + CONFIG.C_AUX_RST_WIDTH {1} \ + CONFIG.C_EXT_RST_WIDTH {1} \ + ] $reset_sync_fixed + + + # Create instance: reset_sync_kernel0, and set properties + set reset_sync_kernel0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 reset_sync_kernel0 ] + set_property -dict [list \ + CONFIG.C_AUX_RESET_HIGH {0} \ + CONFIG.C_AUX_RST_WIDTH {1} \ + CONFIG.C_EXT_RST_WIDTH {1} \ + ] $reset_sync_kernel0 + + + # Create instance: reset_sync_kernel1, and set properties + set reset_sync_kernel1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 reset_sync_kernel1 ] + set_property -dict [list \ + CONFIG.C_AUX_RESET_HIGH {0} \ + CONFIG.C_AUX_RST_WIDTH {1} \ + CONFIG.C_EXT_RST_WIDTH {1} \ + ] $reset_sync_kernel1 + + + # Create instance: rstn_const, and set properties + set rstn_const [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rstn_const ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $rstn_const - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - ] $xlconstant_0 - - # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins GT_Serial] [get_bd_intf_pins gt_quad_base/GT_Serial] - connect_bd_intf_net -intf_net gt_bridge_ip_GT_RX0 [get_bd_intf_pins gt_bridge_ip/GT_RX0] [get_bd_intf_pins gt_quad_base/RX0_GT_IP_Interface] - connect_bd_intf_net -intf_net gt_bridge_ip_GT_TX0 [get_bd_intf_pins gt_bridge_ip/GT_TX0] [get_bd_intf_pins gt_quad_base/TX0_GT_IP_Interface] # Create port connections - connect_bd_net -net GT_REFCLK0_1_1 [get_bd_pins gt_refclk] [get_bd_pins gt_quad_base/GT_REFCLK0] - connect_bd_net -net xlconstant_0_dout [get_bd_pins gt_bridge_ip/apb3clk] [get_bd_pins gt_bridge_ip/gt_rxusrclk] [get_bd_pins gt_bridge_ip/gt_txusrclk] [get_bd_pins gt_bridge_ip/gtreset_in] [get_bd_pins gt_quad_base/apb3clk] [get_bd_pins gt_quad_base/ch0_iloreset] [get_bd_pins gt_quad_base/ch0_rxusrclk] [get_bd_pins gt_quad_base/ch0_txusrclk] [get_bd_pins gt_quad_base/hsclk0_lcpllreset] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net clk_kernel0_1 [get_bd_pins clk_kernel0] [get_bd_pins pipereg_kernel0/clk] [get_bd_pins reset_sync_kernel0/slowest_sync_clk] + connect_bd_net -net clk_kernel1_1 [get_bd_pins clk_kernel1] [get_bd_pins pipereg_kernel1/clk] [get_bd_pins reset_sync_kernel1/slowest_sync_clk] + connect_bd_net -net clk_pcie_1 [get_bd_pins clk_pcie] [get_bd_pins pipereg_pcie0/clk] + connect_bd_net -net clk_pl_axi_1 [get_bd_pins clk_pl_axi] [get_bd_pins pipereg_pl_axi0/clk] [get_bd_pins reset_sync_fixed/slowest_sync_clk] + connect_bd_net -net pipereg_kernel0_q [get_bd_pins resetn_kernel0_ic] [get_bd_pins pipereg_kernel0/Q] + connect_bd_net -net pipereg_kernel1_q [get_bd_pins resetn_kernel1_ic] [get_bd_pins pipereg_kernel1/Q] + connect_bd_net -net pipereg_pcie0_q [get_bd_pins resetn_pcie_axi] [get_bd_pins pipereg_pcie0/Q] + connect_bd_net -net pipereg_pl_axi0_q [get_bd_pins resetn_pl_axi] [get_bd_pins pipereg_pl_axi0/Q] + connect_bd_net -net reset_sync_kernel0_interconnect_aresetn [get_bd_pins pipereg_kernel0/D] [get_bd_pins reset_sync_kernel0/interconnect_aresetn] + connect_bd_net -net reset_sync_kernel0_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins reset_sync_kernel0/peripheral_aresetn] + connect_bd_net -net reset_sync_kernel1_interconnect_aresetn [get_bd_pins pipereg_kernel1/D] [get_bd_pins reset_sync_kernel1/interconnect_aresetn] + connect_bd_net -net resetn_pcie_1 [get_bd_pins resetn_pcie] [get_bd_pins pipereg_pcie0/D] + connect_bd_net -net resetn_ulp_1 [get_bd_pins resetn_ulp] [get_bd_pins pipereg_pl_axi0/D] [get_bd_pins reset_sync_fixed/ext_reset_in] [get_bd_pins reset_sync_kernel0/ext_reset_in] [get_bd_pins reset_sync_kernel1/ext_reset_in] + connect_bd_net -net rstn_const_dout [get_bd_pins pipereg_kernel0/reset] [get_bd_pins pipereg_kernel1/reset] [get_bd_pins pipereg_pcie0/reset] [get_bd_pins pipereg_pl_axi0/reset] [get_bd_pins rstn_const/dout] # Restore current instance current_bd_instance $oldCurInst } -# Hierarchical cell: gt_null0 -proc create_hier_cell_gt_null0 { parentCell nameHier } { +# Hierarchical cell: kernel_interrupt +proc create_hier_cell_kernel_interrupt { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_gt_null0() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_kernel_interrupt() - Empty argument(s)!"} return } @@ -293,53 +322,28 @@ proc create_hier_cell_gt_null0 { parentCell nameHier } { current_bd_instance $hier_obj # Create interface pins - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 GT_Serial - # Create pins - create_bd_pin -dir I -type clk gt_refclk + create_bd_pin -dir I -from 31 -to 0 In0 + create_bd_pin -dir O -from 127 -to 0 xlconcat_interrupt_dout - # Create instance: gt_bridge_ip, and set properties - set gt_bridge_ip [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_bridge_ip:1.1 gt_bridge_ip ] - set_property -dict [ list \ - CONFIG.IP_NO_OF_LANES {1} \ - ] $gt_bridge_ip + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property CONFIG.IN0_WIDTH {32} $xlconcat_0 - # Create instance: gt_quad_base, and set properties - set gt_quad_base [ create_bd_cell -type ip -vlnv xilinx.com:ip:gt_quad_base:1.1 gt_quad_base ] - set_property -dict [ list \ - CONFIG.PORTS_INFO_DICT {\ - LANE_SEL_DICT {PROT0 {RX0 TX0} unconnected {RX1 RX2 RX3 TX1 TX2 TX3}}\ - GT_TYPE {GTY}\ - REG_CONF_INTF {APB3_INTF}\ - BOARD_PARAMETER {}\ - } \ - CONFIG.PROT0_GT_DIRECTION {DUPLEX} \ - CONFIG.PROT0_NO_OF_LANES {1} \ - CONFIG.PROT0_PRESET {None} \ - CONFIG.PROT0_RX_MASTERCLK_SRC {RX0} \ - CONFIG.PROT0_TX_MASTERCLK_SRC {TX0} \ - CONFIG.PROT_OUTCLK_VALUES {\ -CH0_RXOUTCLK 322.266 CH0_TXOUTCLK 322.266 CH1_RXOUTCLK 390.625 CH1_TXOUTCLK\ -390.625 CH2_RXOUTCLK 390.625 CH2_TXOUTCLK 390.625 CH3_RXOUTCLK 390.625\ -CH3_TXOUTCLK 390.625} \ - CONFIG.REFCLK_STRING {HSCLK0_LCPLLGTREFCLK0 refclk_PROT0_R0_156.25_MHz_unique1} \ - ] $gt_quad_base # Create instance: xlconstant_0, and set properties set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - ] $xlconstant_0 + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {96} \ + ] $xlconstant_0 - # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins GT_Serial] [get_bd_intf_pins gt_quad_base/GT_Serial] - connect_bd_intf_net -intf_net gt_bridge_ip_GT_RX0 [get_bd_intf_pins gt_bridge_ip/GT_RX0] [get_bd_intf_pins gt_quad_base/RX0_GT_IP_Interface] - connect_bd_intf_net -intf_net gt_bridge_ip_GT_TX0 [get_bd_intf_pins gt_bridge_ip/GT_TX0] [get_bd_intf_pins gt_quad_base/TX0_GT_IP_Interface] # Create port connections - connect_bd_net -net GT_REFCLK0_0_1 [get_bd_pins gt_refclk] [get_bd_pins gt_quad_base/GT_REFCLK0] - connect_bd_net -net xlconstant_0_dout [get_bd_pins gt_bridge_ip/apb3clk] [get_bd_pins gt_bridge_ip/gt_rxusrclk] [get_bd_pins gt_bridge_ip/gt_txusrclk] [get_bd_pins gt_bridge_ip/gtreset_in] [get_bd_pins gt_quad_base/apb3clk] [get_bd_pins gt_quad_base/ch0_iloreset] [get_bd_pins gt_quad_base/ch0_rxusrclk] [get_bd_pins gt_quad_base/ch0_txusrclk] [get_bd_pins gt_quad_base/hsclk0_lcpllreset] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_interrupt_dout] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout] # Restore current instance current_bd_instance $oldCurInst @@ -348,7 +352,7 @@ CH3_TXOUTCLK 390.625} \ # Procedure to create entire design; Provide argument to make # procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell kernel } { +proc create_root_design { parentCell } { variable script_folder variable design_name @@ -379,72 +383,44 @@ proc create_root_design { parentCell kernel } { # Create interface ports - set BLP_M_AXI_DATA_C2H_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 BLP_M_AXI_DATA_C2H_00 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {44} \ - CONFIG.DATA_WIDTH {512} \ - CONFIG.FREQ_HZ {249997498} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.NUM_READ_OUTSTANDING {16} \ - CONFIG.NUM_WRITE_OUTSTANDING {16} \ - CONFIG.PHASE {0} \ - CONFIG.PROTOCOL {AXI4} \ - ] $BLP_M_AXI_DATA_C2H_00 - - set BLP_M_INI_MC_00 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_M_INI_MC_00 ] - set_property -dict [ list \ - CONFIG.COMPUTED_STRATEGY {load} \ - CONFIG.INI_STRATEGY {load} \ - ] $BLP_M_INI_MC_00 - - set BLP_M_INI_MC_01 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_M_INI_MC_01 ] - set_property -dict [ list \ - CONFIG.COMPUTED_STRATEGY {load} \ - CONFIG.INI_STRATEGY {load} \ - ] $BLP_M_INI_MC_01 - - set BLP_S_AXI_CTRL_MGMT_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 BLP_S_AXI_CTRL_MGMT_00 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {25} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.FREQ_HZ {99999001} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {0} \ - CONFIG.MAX_BURST_LENGTH {1} \ - CONFIG.NUM_READ_OUTSTANDING {2} \ - CONFIG.NUM_READ_THREADS {1} \ - CONFIG.NUM_WRITE_OUTSTANDING {2} \ - CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PHASE {0} \ - CONFIG.PROTOCOL {AXI4LITE} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {0} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $BLP_S_AXI_CTRL_MGMT_00 - - set BLP_S_AXI_CTRL_USER_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 BLP_S_AXI_CTRL_USER_00 ] + set BLP_M_M00_INI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_M_M00_INI_0 ] + set_property APERTURES {{0xC1_0000_0000 12G}} [get_bd_intf_ports BLP_M_M00_INI_0] + + set BLP_M_M01_INI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_M_M01_INI_0 ] + set_property APERTURES {{0xC1_0000_0000 12G}} [get_bd_intf_ports BLP_M_M01_INI_0] + + set BLP_M_M02_INI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_M_M02_INI_0 ] + set_property APERTURES {{0xC1_0000_0000 12G}} [get_bd_intf_ports BLP_M_M02_INI_0] + + set BLP_S_AXI_CTRL_USER_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 -portmaps { \ + ARADDR { physical_name BLP_S_AXI_CTRL_USER_00_araddr direction I left 63 right 0 } \ + ARPROT { physical_name BLP_S_AXI_CTRL_USER_00_arprot direction I left 2 right 0 } \ + ARREADY { physical_name BLP_S_AXI_CTRL_USER_00_arready direction O } \ + ARVALID { physical_name BLP_S_AXI_CTRL_USER_00_arvalid direction I } \ + AWADDR { physical_name BLP_S_AXI_CTRL_USER_00_awaddr direction I left 63 right 0 } \ + AWPROT { physical_name BLP_S_AXI_CTRL_USER_00_awprot direction I left 2 right 0 } \ + AWREADY { physical_name BLP_S_AXI_CTRL_USER_00_awready direction O } \ + AWVALID { physical_name BLP_S_AXI_CTRL_USER_00_awvalid direction I } \ + BREADY { physical_name BLP_S_AXI_CTRL_USER_00_bready direction I } \ + BRESP { physical_name BLP_S_AXI_CTRL_USER_00_bresp direction O left 1 right 0 } \ + BVALID { physical_name BLP_S_AXI_CTRL_USER_00_bvalid direction O } \ + RDATA { physical_name BLP_S_AXI_CTRL_USER_00_rdata direction O left 31 right 0 } \ + RREADY { physical_name BLP_S_AXI_CTRL_USER_00_rready direction I } \ + RRESP { physical_name BLP_S_AXI_CTRL_USER_00_rresp direction O left 1 right 0 } \ + RVALID { physical_name BLP_S_AXI_CTRL_USER_00_rvalid direction O } \ + WDATA { physical_name BLP_S_AXI_CTRL_USER_00_wdata direction I left 31 right 0 } \ + WREADY { physical_name BLP_S_AXI_CTRL_USER_00_wready direction O } \ + WSTRB { physical_name BLP_S_AXI_CTRL_USER_00_wstrb direction I left 3 right 0 } \ + WVALID { physical_name BLP_S_AXI_CTRL_USER_00_wvalid direction I } \ + } \ + BLP_S_AXI_CTRL_USER_00 ] set_property -dict [ list \ - CONFIG.ADDR_WIDTH {25} \ + CONFIG.ADDR_WIDTH {64} \ CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ CONFIG.DATA_WIDTH {32} \ - CONFIG.FREQ_HZ {99999001} \ + CONFIG.FREQ_HZ {99999992} \ CONFIG.HAS_BRESP {1} \ CONFIG.HAS_BURST {0} \ CONFIG.HAS_CACHE {0} \ @@ -455,12 +431,13 @@ proc create_root_design { parentCell kernel } { CONFIG.HAS_RRESP {1} \ CONFIG.HAS_WSTRB {1} \ CONFIG.ID_WIDTH {0} \ + CONFIG.INSERT_VIP {0} \ CONFIG.MAX_BURST_LENGTH {1} \ CONFIG.NUM_READ_OUTSTANDING {2} \ CONFIG.NUM_READ_THREADS {1} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PHASE {0} \ + CONFIG.PHASE {0.0} \ CONFIG.PROTOCOL {AXI4LITE} \ CONFIG.READ_WRITE_MODE {READ_WRITE} \ CONFIG.RUSER_BITS_PER_BYTE {0} \ @@ -469,93 +446,172 @@ proc create_root_design { parentCell kernel } { CONFIG.WUSER_BITS_PER_BYTE {0} \ CONFIG.WUSER_WIDTH {0} \ ] $BLP_S_AXI_CTRL_USER_00 - - set BLP_S_AXI_DATA_H2C_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 BLP_S_AXI_DATA_H2C_00 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {44} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {512} \ - CONFIG.FREQ_HZ {249997498} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {1} \ - CONFIG.HAS_CACHE {1} \ - CONFIG.HAS_LOCK {1} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {2} \ - CONFIG.MAX_BURST_LENGTH {256} \ - CONFIG.NUM_READ_OUTSTANDING {16} \ - CONFIG.NUM_READ_THREADS {2} \ - CONFIG.NUM_WRITE_OUTSTANDING {16} \ - CONFIG.NUM_WRITE_THREADS {2} \ - CONFIG.PHASE {0} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {1} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $BLP_S_AXI_DATA_H2C_00 + set_property APERTURES {{0x202_0000_0000 32M}} [get_bd_intf_ports BLP_S_AXI_CTRL_USER_00] + set_property HDL_ATTRIBUTE.LOCKED {true} [get_bd_intf_ports BLP_S_AXI_CTRL_USER_00] set BLP_S_INI_AIE_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_S_INI_AIE_00 ] - set_property -dict [ list \ - CONFIG.INI_STRATEGY {load} \ - ] $BLP_S_INI_AIE_00 - set gt0_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt0_refclk ] + set BLP_S_INI_DBG_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_S_INI_DBG_00 ] + + set BLP_S_INI_PLRAM_00 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:inimm_rtl:1.0 BLP_S_INI_PLRAM_00 ] + + set qsfp0_161mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 -board_intf qsfp0_161mhz qsfp0_161mhz ] set_property -dict [ list \ + CONFIG.CAN_DEBUG {false} \ CONFIG.FREQ_HZ {161132812} \ - ] $gt0_refclk + ] $qsfp0_161mhz + set_property HDL_ATTRIBUTE.BOARD_INTERFACE {qsfp0_161mhz} [get_bd_intf_ports qsfp0_161mhz] + set_property HDL_ATTRIBUTE.LOCKED {TRUE} [get_bd_intf_ports qsfp0_161mhz] - set gt0_serial [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt0_serial ] + set qsfp0_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 -board_intf qsfp0_4x qsfp0_4x ] + set_property -dict [ list \ + CONFIG.CAN_DEBUG {false} \ + ] $qsfp0_4x + set_property HDL_ATTRIBUTE.BOARD_INTERFACE {qsfp0_4x} [get_bd_intf_ports qsfp0_4x] + set_property HDL_ATTRIBUTE.LOCKED {TRUE} [get_bd_intf_ports qsfp0_4x] - set gt1_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 gt1_refclk ] + set qsfp1_161mhz [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 -board_intf qsfp1_161mhz qsfp1_161mhz ] set_property -dict [ list \ + CONFIG.CAN_DEBUG {false} \ CONFIG.FREQ_HZ {161132812} \ - ] $gt1_refclk + ] $qsfp1_161mhz + set_property HDL_ATTRIBUTE.BOARD_INTERFACE {qsfp1_161mhz} [get_bd_intf_ports qsfp1_161mhz] + set_property HDL_ATTRIBUTE.LOCKED {TRUE} [get_bd_intf_ports qsfp1_161mhz] - set gt1_serial [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt1_serial ] + set qsfp1_4x [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 -board_intf qsfp1_4x qsfp1_4x ] + set_property -dict [ list \ + CONFIG.CAN_DEBUG {false} \ + ] $qsfp1_4x + set_property HDL_ATTRIBUTE.BOARD_INTERFACE {qsfp1_4x} [get_bd_intf_ports qsfp1_4x] + set_property HDL_ATTRIBUTE.LOCKED {TRUE} [get_bd_intf_ports qsfp1_4x] # Create ports + set blp_m_dbg_hub_fw_00 [ create_bd_port -dir O -from 0 -to 0 -type intr blp_m_dbg_hub_fw_00 ] + set blp_m_ext_tog_ctrl_kernel_00_enable [ create_bd_port -dir O -from 0 -to 0 blp_m_ext_tog_ctrl_kernel_00_enable ] + set blp_m_ext_tog_ctrl_kernel_00_in [ create_bd_port -dir O -from 0 -to 0 blp_m_ext_tog_ctrl_kernel_00_in ] + set blp_m_ext_tog_ctrl_kernel_01_enable [ create_bd_port -dir O -from 0 -to 0 blp_m_ext_tog_ctrl_kernel_01_enable ] + set blp_m_ext_tog_ctrl_kernel_01_in [ create_bd_port -dir O -from 0 -to 0 blp_m_ext_tog_ctrl_kernel_01_in ] set blp_m_irq_kernel_00 [ create_bd_port -dir O -from 127 -to 0 -type intr blp_m_irq_kernel_00 ] - set blp_s_aclk_ctrl_00 [ create_bd_port -dir I -type clk -freq_hz 99999001 blp_s_aclk_ctrl_00 ] - set_property -dict [ list \ - CONFIG.CLK_DOMAIN {level0_cips_0_pl0_ref_clk} \ - CONFIG.PHASE {0} \ + set blp_s_aclk_ctrl_00 [ create_bd_port -dir I -type clk blp_s_aclk_ctrl_00 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {BLP_S_AXI_CTRL_USER_00} \ + CONFIG.CLK_DOMAIN {bd_4885_pspmc_0_0_pl0_ref_clk} \ + CONFIG.FREQ_HZ {99999992} \ + CONFIG.FREQ_TOLERANCE_HZ {0} \ + CONFIG.INSERT_VIP {0} \ + CONFIG.PHASE {0.0} \ ] $blp_s_aclk_ctrl_00 - set blp_s_aclk_kernel_00 [ create_bd_port -dir I -type clk -freq_hz 199998000 blp_s_aclk_kernel_00 ] - set_property -dict [ list \ - CONFIG.CLK_DOMAIN {level0_clkwiz_kernel0_0_clk_out1} \ - CONFIG.PHASE {0} \ + set_property CONFIG.ASSOCIATED_BUSIF.VALUE_SRC STRONG $blp_s_aclk_ctrl_00 + set_property CONFIG.CLK_DOMAIN.VALUE_SRC STRONG $blp_s_aclk_ctrl_00 + set_property CONFIG.FREQ_HZ.VALUE_SRC STRONG $blp_s_aclk_ctrl_00 + set_property CONFIG.FREQ_TOLERANCE_HZ.VALUE_SRC STRONG $blp_s_aclk_ctrl_00 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aclk_ctrl_00 + set_property CONFIG.PHASE.VALUE_SRC STRONG $blp_s_aclk_ctrl_00 + + set blp_s_aclk_ext_tog_kernel_00 [ create_bd_port -dir I -type clk blp_s_aclk_ext_tog_kernel_00 ] + set_property -dict [ list \ + CONFIG.CLK_DOMAIN {cd_aclk_ext_tog_kernel_00} \ + CONFIG.FREQ_HZ {299996999} \ + CONFIG.FREQ_TOLERANCE_HZ {0} \ + CONFIG.INSERT_VIP {0} \ + CONFIG.PHASE {0.0} \ + ] $blp_s_aclk_ext_tog_kernel_00 + set_property CONFIG.CLK_DOMAIN.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_00 + set_property CONFIG.FREQ_HZ.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_00 + set_property CONFIG.FREQ_TOLERANCE_HZ.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_00 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_00 + set_property CONFIG.PHASE.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_00 + + set blp_s_aclk_ext_tog_kernel_01 [ create_bd_port -dir I -type clk blp_s_aclk_ext_tog_kernel_01 ] + set_property -dict [ list \ + CONFIG.CLK_DOMAIN {cd_aclk_ext_tog_kernel_01} \ + CONFIG.FREQ_HZ {499994999} \ + CONFIG.FREQ_TOLERANCE_HZ {0} \ + CONFIG.INSERT_VIP {0} \ + CONFIG.PHASE {0.0} \ + ] $blp_s_aclk_ext_tog_kernel_01 + set_property CONFIG.CLK_DOMAIN.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_01 + set_property CONFIG.FREQ_HZ.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_01 + set_property CONFIG.FREQ_TOLERANCE_HZ.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_01 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_01 + set_property CONFIG.PHASE.VALUE_SRC STRONG $blp_s_aclk_ext_tog_kernel_01 + + set blp_s_aclk_kernel_00 [ create_bd_port -dir I -type clk blp_s_aclk_kernel_00 ] + set_property -dict [ list \ + CONFIG.CLK_DOMAIN {cd_aclk_kernel_00} \ + CONFIG.FREQ_HZ {299996999} \ + CONFIG.FREQ_TOLERANCE_HZ {0} \ + CONFIG.INSERT_VIP {0} \ + CONFIG.PHASE {0.0} \ ] $blp_s_aclk_kernel_00 - set blp_s_aclk_kernel_01 [ create_bd_port -dir I -type clk -freq_hz 299996999 blp_s_aclk_kernel_01 ] - set_property -dict [ list \ - CONFIG.CLK_DOMAIN {level0_clkwiz_kernel1_0_clk_out1} \ - CONFIG.PHASE {0} \ + set_property CONFIG.CLK_DOMAIN.VALUE_SRC STRONG $blp_s_aclk_kernel_00 + set_property CONFIG.FREQ_HZ.VALUE_SRC STRONG $blp_s_aclk_kernel_00 + set_property CONFIG.FREQ_TOLERANCE_HZ.VALUE_SRC STRONG $blp_s_aclk_kernel_00 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aclk_kernel_00 + set_property CONFIG.PHASE.VALUE_SRC STRONG $blp_s_aclk_kernel_00 + + set blp_s_aclk_kernel_01 [ create_bd_port -dir I -type clk blp_s_aclk_kernel_01 ] + set_property -dict [ list \ + CONFIG.CLK_DOMAIN {cd_aclk_kernel_01} \ + CONFIG.FREQ_HZ {499994999} \ + CONFIG.FREQ_TOLERANCE_HZ {0} \ + CONFIG.INSERT_VIP {0} \ + CONFIG.PHASE {0.0} \ ] $blp_s_aclk_kernel_01 - set blp_s_aclk_pcie_00 [ create_bd_port -dir I -type clk -freq_hz 249997498 blp_s_aclk_pcie_00 ] - set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {BLP_M_AXI_DATA_C2H_00:BLP_S_AXI_DATA_H2C_00} \ - CONFIG.CLK_DOMAIN {level0_cips_0_pl2_ref_clk} \ - CONFIG.PHASE {0} \ + set_property CONFIG.CLK_DOMAIN.VALUE_SRC STRONG $blp_s_aclk_kernel_01 + set_property CONFIG.FREQ_HZ.VALUE_SRC STRONG $blp_s_aclk_kernel_01 + set_property CONFIG.FREQ_TOLERANCE_HZ.VALUE_SRC STRONG $blp_s_aclk_kernel_01 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aclk_kernel_01 + set_property CONFIG.PHASE.VALUE_SRC STRONG $blp_s_aclk_kernel_01 + + set blp_s_aclk_pcie_00 [ create_bd_port -dir I -type clk blp_s_aclk_pcie_00 ] + set_property -dict [ list \ + CONFIG.CLK_DOMAIN {bd_4885_pspmc_0_0_pl2_ref_clk} \ + CONFIG.FREQ_HZ {249999985} \ + CONFIG.FREQ_TOLERANCE_HZ {0} \ + CONFIG.INSERT_VIP {0} \ + CONFIG.PHASE {0.0} \ ] $blp_s_aclk_pcie_00 + set_property CONFIG.CLK_DOMAIN.VALUE_SRC STRONG $blp_s_aclk_pcie_00 + set_property CONFIG.FREQ_HZ.VALUE_SRC STRONG $blp_s_aclk_pcie_00 + set_property CONFIG.FREQ_TOLERANCE_HZ.VALUE_SRC STRONG $blp_s_aclk_pcie_00 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aclk_pcie_00 + set_property CONFIG.PHASE.VALUE_SRC STRONG $blp_s_aclk_pcie_00 + set blp_s_aresetn_pcie_reset_00 [ create_bd_port -dir I -from 0 -to 0 -type rst blp_s_aresetn_pcie_reset_00 ] + set_property -dict [ list \ + CONFIG.INSERT_VIP {0} \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $blp_s_aresetn_pcie_reset_00 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aresetn_pcie_reset_00 + set_property CONFIG.POLARITY.VALUE_SRC STRONG $blp_s_aresetn_pcie_reset_00 + set blp_s_aresetn_pr_reset_00 [ create_bd_port -dir I -from 0 -to 0 -type rst blp_s_aresetn_pr_reset_00 ] + set_property -dict [ list \ + CONFIG.INSERT_VIP {0} \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $blp_s_aresetn_pr_reset_00 + set_property CONFIG.INSERT_VIP.VALUE_SRC STRONG $blp_s_aresetn_pr_reset_00 + set_property CONFIG.POLARITY.VALUE_SRC STRONG $blp_s_aresetn_pr_reset_00 + + set blp_s_ext_tog_ctrl_kernel_00_out [ create_bd_port -dir I blp_s_ext_tog_ctrl_kernel_00_out ] + set blp_s_ext_tog_ctrl_kernel_01_out [ create_bd_port -dir I blp_s_ext_tog_ctrl_kernel_01_out ] # Create instance: ai_engine_0, and set properties set ai_engine_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ai_engine:2.0 ai_engine_0 ] - set_property -dict [ list \ - CONFIG.AIE_CORE_REF_CTRL_FREQMHZ {1250} \ - CONFIG.NUM_CLKS {1} \ - CONFIG.NUM_MI_AXI {16} \ - ] $ai_engine_0 + set_property -dict [list \ + CONFIG.AIE_CORE_REF_CTRL_FREQMHZ {1250} \ + CONFIG.CLK_NAMES {aclk0,} \ + CONFIG.NAME_MI_AXI {} \ + CONFIG.NAME_MI_AXIS {} \ + CONFIG.NAME_SI_AXIS {} \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI_AXI {16} \ + CONFIG.NUM_MI_AXIS {0} \ + CONFIG.NUM_SI_AXIS {0} \ + ] $ai_engine_0 + set_property -dict [ list \ CONFIG.CATEGORY {NOC} \ @@ -631,469 +687,564 @@ proc create_root_design { parentCell kernel } { # Create instance: axi_bram_ctrl_0, and set properties set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - ] $axi_bram_ctrl_0 - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + # Create instance: axi_dbg_fw, and set properties + set axi_dbg_fw [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_firewall:1.2 axi_dbg_fw ] + set_property CONFIG.MASK_ERR_RESP {1} $axi_dbg_fw - # Create instance: axi_noc_0, and set properties - set axi_noc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 axi_noc_0 ] - set_property -dict [ list \ - CONFIG.NUM_MI {0} \ - CONFIG.NUM_NMI {2} \ - CONFIG.NUM_SI {1} \ - ] $axi_noc_0 - set_property -dict [ list \ - CONFIG.INI_STRATEGY {load} \ - ] [get_bd_intf_pins /axi_noc_0/M00_INI] + # Create instance: axi_dbg_hub, and set properties + set axi_dbg_hub [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dbg_hub:2.0 axi_dbg_hub ] + set_property -dict [list \ + CONFIG.C_AXI_DATA_WIDTH {128} \ + CONFIG.C_NUM_DEBUG_CORES {0} \ + ] $axi_dbg_hub - set_property -dict [ list \ - CONFIG.INI_STRATEGY {load} \ - ] [get_bd_intf_pins /axi_noc_0/M01_INI] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M00_INI { read_bw {5} write_bw {5}} } \ - CONFIG.CATEGORY {pl} \ - ] [get_bd_intf_pins /axi_noc_0/S00_AXI] + # Create instance: axi_gpio_null_user, and set properties + set axi_gpio_null_user [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_null_user ] + set_property CONFIG.C_GPIO_WIDTH {1} $axi_gpio_null_user - set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ - ] [get_bd_pins /axi_noc_0/aclk0] - # Create instance: axi_noc_1, and set properties - set axi_noc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 axi_noc_1 ] - set_property -dict [ list \ - CONFIG.NUM_CLKS {18} \ - CONFIG.NUM_MI {2} \ - CONFIG.NUM_NSI {1} \ - CONFIG.NUM_SI {17} \ - ] $axi_noc_1 + # Create instance: axi_ic_user, and set properties + set axi_ic_user [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_ic_user ] + set_property -dict [list \ + CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {__enable_axi4lite_64_mi__ 1}} \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $axi_ic_user + + set_property HDL_ATTRIBUTE.DPA_AXILITE_MASTER {primary} [get_bd_cells axi_ic_user] + + # Create instance: axi_ic_user_extend, and set properties + set axi_ic_user_extend [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_ic_user_extend ] + set_property -dict [list \ + CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {__enable_axi4lite_64_mi__ 1}} \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_ic_user_extend + + + # Create instance: axi_noc_aie_prog, and set properties + set axi_noc_aie_prog [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 axi_noc_aie_prog ] + set_property -dict [list \ + CONFIG.NUM_CLKS {18} \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_NSI {1} \ + CONFIG.NUM_SI {17} \ + CONFIG.SI_SIDEBAND_PINS {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} \ + ] $axi_noc_aie_prog + set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/M00_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/M00_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ CONFIG.APERTURES {{0x201_0000_0000 1G}} \ CONFIG.CATEGORY {pl} \ - ] [get_bd_intf_pins /axi_noc_1/M01_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/M01_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S00_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S00_AXI] set_property -dict [ list \ CONFIG.INI_STRATEGY {load} \ - CONFIG.CONNECTIONS {M00_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ - ] [get_bd_intf_pins /axi_noc_1/S00_INI] + CONFIG.CONNECTIONS {M00_AXI { read_bw {5} write_bw {5} read_avg_burst {64} write_avg_burst {64}} } \ + ] [get_bd_intf_pins /axi_noc_aie_prog/S00_INI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S01_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S01_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S02_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S02_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S03_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S03_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S04_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S04_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S05_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S05_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S06_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S06_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S07_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S07_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S08_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S08_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S09_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S09_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S10_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S10_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S11_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S11_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S12_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S12_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S13_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S13_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S14_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S14_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M01_AXI:0x40} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {aie} \ - ] [get_bd_intf_pins /axi_noc_1/S15_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S15_AXI] set_property -dict [ list \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.CONNECTIONS {M00_AXI { read_bw {1720} write_bw {1720} read_avg_burst {4} write_avg_burst {4}} } \ + CONFIG.CONNECTIONS {M00_AXI { read_bw {1720} write_bw {1720} read_avg_burst {4} write_avg_burst {4}}} \ CONFIG.DEST_IDS {M00_AXI:0x240} \ + CONFIG.NOC_PARAMS {} \ CONFIG.CATEGORY {pl} \ - ] [get_bd_intf_pins /axi_noc_1/S16_AXI] + ] [get_bd_intf_pins /axi_noc_aie_prog/S16_AXI] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk0] + ] [get_bd_pins /axi_noc_aie_prog/aclk0] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {M01_AXI:S16_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk1] + ] [get_bd_pins /axi_noc_aie_prog/aclk1] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk2] + ] [get_bd_pins /axi_noc_aie_prog/aclk2] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S01_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk3] + ] [get_bd_pins /axi_noc_aie_prog/aclk3] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S02_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk4] + ] [get_bd_pins /axi_noc_aie_prog/aclk4] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S03_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk5] + ] [get_bd_pins /axi_noc_aie_prog/aclk5] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S04_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk6] + ] [get_bd_pins /axi_noc_aie_prog/aclk6] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S05_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk7] + ] [get_bd_pins /axi_noc_aie_prog/aclk7] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S06_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk8] + ] [get_bd_pins /axi_noc_aie_prog/aclk8] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S07_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk9] + ] [get_bd_pins /axi_noc_aie_prog/aclk9] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S08_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk10] + ] [get_bd_pins /axi_noc_aie_prog/aclk10] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S09_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk11] + ] [get_bd_pins /axi_noc_aie_prog/aclk11] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S10_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk12] + ] [get_bd_pins /axi_noc_aie_prog/aclk12] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S11_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk13] + ] [get_bd_pins /axi_noc_aie_prog/aclk13] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S12_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk14] + ] [get_bd_pins /axi_noc_aie_prog/aclk14] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S13_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk15] + ] [get_bd_pins /axi_noc_aie_prog/aclk15] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S14_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk16] + ] [get_bd_pins /axi_noc_aie_prog/aclk16] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S15_AXI} \ - ] [get_bd_pins /axi_noc_1/aclk17] + ] [get_bd_pins /axi_noc_aie_prog/aclk17] + + # Create instance: axi_noc_h2c, and set properties + set axi_noc_h2c [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 axi_noc_h2c ] + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_NMI {0} \ + CONFIG.NUM_NSI {2} \ + CONFIG.NUM_SI {0} \ + ] $axi_noc_h2c + - # Create instance: emb_mem_gen_0, and set properties - set emb_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:emb_mem_gen:1.0 emb_mem_gen_0 ] set_property -dict [ list \ - CONFIG.MEMORY_TYPE {True_Dual_Port_RAM} \ - ] $emb_mem_gen_0 + CONFIG.APERTURES {{0x202_0580_0000 2M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_h2c/M00_AXI] - # Create instance: freq_counter0, and set properties - set freq_counter0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:shell_utils_frequency_counter:1.0 freq_counter0 ] set_property -dict [ list \ - CONFIG.REF_CLK_FREQ_HZ {100000} \ - ] $freq_counter0 + CONFIG.APERTURES {{0x202_0400_0000 16M}} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_h2c/M01_AXI] - # Create instance: freq_counter1, and set properties - set freq_counter1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:shell_utils_frequency_counter:1.0 freq_counter1 ] set_property -dict [ list \ - CONFIG.REF_CLK_FREQ_HZ {100000} \ - ] $freq_counter1 + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M00_AXI { read_bw {1720} write_bw {1720} read_avg_burst {64} write_avg_burst {64}} } \ + ] [get_bd_intf_pins /axi_noc_h2c/S00_INI] - # Create instance: gt0_refclk_buf, and set properties - set gt0_refclk_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 gt0_refclk_buf ] set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDSGTE} \ - ] $gt0_refclk_buf + CONFIG.INI_STRATEGY {load} \ + CONFIG.CONNECTIONS {M01_AXI { read_bw {1720} write_bw {1720} read_avg_burst {64} write_avg_burst {64}} } \ + ] [get_bd_intf_pins /axi_noc_h2c/S01_INI] - # Create instance: gt1_refclk_buf, and set properties - set gt1_refclk_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 gt1_refclk_buf ] set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDSGTE} \ - ] $gt1_refclk_buf + CONFIG.ASSOCIATED_BUSIF {M00_AXI:M01_AXI} \ + ] [get_bd_pins /axi_noc_h2c/aclk0] - # Create instance: gt_null0 - create_hier_cell_gt_null0 [current_bd_instance .] gt_null0 + # Create instance: axi_noc_kernel0, and set properties + set axi_noc_kernel0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 axi_noc_kernel0 ] + set_property -dict [list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_MI {0} \ + CONFIG.NUM_NMI {3} \ + CONFIG.NUM_NSI {0} \ + CONFIG.NUM_SI {1} \ + ] $axi_noc_kernel0 - # Create instance: gt_null1 - create_hier_cell_gt_null1 [current_bd_instance .] gt_null1 + set_property HDL_ATTRIBUTE.DPA_TRACE_SLAVE {true} [get_bd_cells axi_noc_kernel0] - # Create instance: ii_level0_wire_0, and set properties - set ii_level0_wire_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ii_level0_wire:1.0 ii_level0_wire_0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /axi_noc_kernel0/M00_INI] - # Create instance: ${kernel}_0, and set properties - set kernel_0 [ create_bd_cell -type ip -vlnv xilinx.com:RTLKernel:${kernel}:1.0 ${kernel}_0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /axi_noc_kernel0/M01_INI] - # Create instance: pipeline_reg_0, and set properties - set pipeline_reg_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:pipeline_reg:1.0 pipeline_reg_0 ] + set_property -dict [ list \ + CONFIG.INI_STRATEGY {load} \ + ] [get_bd_intf_pins /axi_noc_kernel0/M02_INI] - # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIONS {M00_INI {read_bw {778} write_bw {389} read_avg_burst {4} write_avg_burst {4}}} \ + CONFIG.NOC_PARAMS {} \ + CONFIG.CATEGORY {pl} \ + ] [get_bd_intf_pins /axi_noc_kernel0/S00_AXI] + + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + ] [get_bd_pins /axi_noc_kernel0/aclk0] + + # Create instance: axi_sc_plram, and set properties + set axi_sc_plram [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_sc_plram ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_sc_plram + + + # Create instance: const_1, and set properties + set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] + + # Create instance: data_mover_mm2mm_0, and set properties + set data_mover_mm2mm_0 [ create_bd_cell -type ip -vlnv xilinx.com:RTLKernel:data_mover_mm2mm:1.0 data_mover_mm2mm_0 ] + + # Create instance: emb_mem_gen_0, and set properties + set emb_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:emb_mem_gen:1.0 emb_mem_gen_0 ] + set_property CONFIG.MEMORY_TYPE {True_Dual_Port_RAM} $emb_mem_gen_0 + + + # Create instance: gate_dbgfw_or, and set properties + set gate_dbgfw_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 gate_dbgfw_or ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $gate_dbgfw_or + + + # Create instance: ip_gnd_ext_tog_kernel_00_null, and set properties + set ip_gnd_ext_tog_kernel_00_null [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 ip_gnd_ext_tog_kernel_00_null ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $ip_gnd_ext_tog_kernel_00_null + + + # Create instance: ip_gnd_ext_tog_kernel_01_null, and set properties + set ip_gnd_ext_tog_kernel_01_null [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 ip_gnd_ext_tog_kernel_01_null ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $ip_gnd_ext_tog_kernel_01_null + + + # Create instance: ip_pipe_dbg_hub_fw_00, and set properties + set ip_pipe_dbg_hub_fw_00 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 ip_pipe_dbg_hub_fw_00 ] + set_property CONFIG.C_R_INVERTED {0} $ip_pipe_dbg_hub_fw_00 + + + # Create instance: ip_pipe_ext_tog_kernel_00_null, and set properties + set ip_pipe_ext_tog_kernel_00_null [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 ip_pipe_ext_tog_kernel_00_null ] + set_property CONFIG.C_R_INVERTED {0} $ip_pipe_ext_tog_kernel_00_null + + + # Create instance: ip_pipe_ext_tog_kernel_01_null, and set properties + set ip_pipe_ext_tog_kernel_01_null [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ff:1.0 ip_pipe_ext_tog_kernel_01_null ] + set_property CONFIG.C_R_INVERTED {0} $ip_pipe_ext_tog_kernel_01_null + + + # Create instance: irq_const_tieoff, and set properties + set irq_const_tieoff [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 irq_const_tieoff ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $irq_const_tieoff + + + # Create instance: kernel_interrupt + create_hier_cell_kernel_interrupt [current_bd_instance .] kernel_interrupt + + # Create instance: kernel_interrupt_xlconcat_0_In0_1_interrupt_concat, and set properties + set kernel_interrupt_xlconcat_0_In0_1_interrupt_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 kernel_interrupt_xlconcat_0_In0_1_interrupt_concat ] + set_property CONFIG.NUM_PORTS {32} $kernel_interrupt_xlconcat_0_In0_1_interrupt_concat + + + # Create instance: plram_ctrl, and set properties + set plram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 plram_ctrl ] + set_property -dict [list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $plram_ctrl + + + # Create instance: plram_ctrl_bram, and set properties + set plram_ctrl_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:emb_mem_gen:1.0 plram_ctrl_bram ] + + # Create instance: reset_controllers + create_hier_cell_reset_controllers [current_bd_instance .] reset_controllers # Create instance: smartconnect_0, and set properties set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] - set_property -dict [ list \ - CONFIG.NUM_CLKS {2} \ - CONFIG.NUM_SI {1} \ - ] $smartconnect_0 + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + # Create instance: smartconnect_1, and set properties set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ] - set_property -dict [ list \ - CONFIG.NUM_MI {3} \ - CONFIG.NUM_SI {1} \ - ] $smartconnect_1 - - # Create instance: smartconnect_2, and set properties - set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ] - - # Create instance: smartconnect_3, and set properties - set smartconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_3 ] - set_property -dict [ list \ - CONFIG.NUM_MI {2} \ - CONFIG.NUM_SI {1} \ - ] $smartconnect_3 # Create instance: xlconstant_0, and set properties set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {128} \ - ] $xlconstant_0 - - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1} \ - ] $xlconstant_1 + set_property CONFIG.CONST_VAL {0} $xlconstant_0 - # Create instance: xlconstant_2, and set properties - set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {32} \ - ] $xlconstant_2 - - # Create instance: xlconstant_3, and set properties - set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - ] $xlconstant_3 # Create interface connections - connect_bd_intf_net -intf_net BLP_S_AXI_CTRL_MGMT_00_0_1 [get_bd_intf_ports BLP_S_AXI_CTRL_MGMT_00] [get_bd_intf_pins ii_level0_wire_0/BLP_S_AXI_CTRL_MGMT_00] - connect_bd_intf_net -intf_net BLP_S_AXI_CTRL_USER_00_0_1 [get_bd_intf_ports BLP_S_AXI_CTRL_USER_00] [get_bd_intf_pins ii_level0_wire_0/BLP_S_AXI_CTRL_USER_00] - connect_bd_intf_net -intf_net BLP_S_AXI_DATA_H2C_00_0_1 [get_bd_intf_ports BLP_S_AXI_DATA_H2C_00] [get_bd_intf_pins ii_level0_wire_0/BLP_S_AXI_DATA_H2C_00] - connect_bd_intf_net -intf_net CLK_IN_D_0_1 [get_bd_intf_ports gt0_refclk] [get_bd_intf_pins gt0_refclk_buf/CLK_IN_D] - connect_bd_intf_net -intf_net CLK_IN_D_1_1 [get_bd_intf_ports gt1_refclk] [get_bd_intf_pins gt1_refclk_buf/CLK_IN_D] - connect_bd_intf_net -intf_net S00_INI_0_1 [get_bd_intf_ports BLP_S_INI_AIE_00] [get_bd_intf_pins axi_noc_1/S00_INI] - connect_bd_intf_net -intf_net ai_engine_0_M00_AXI [get_bd_intf_pins ai_engine_0/M00_AXI] [get_bd_intf_pins axi_noc_1/S00_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M01_AXI [get_bd_intf_pins ai_engine_0/M01_AXI] [get_bd_intf_pins axi_noc_1/S01_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M02_AXI [get_bd_intf_pins ai_engine_0/M02_AXI] [get_bd_intf_pins axi_noc_1/S02_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M03_AXI [get_bd_intf_pins ai_engine_0/M03_AXI] [get_bd_intf_pins axi_noc_1/S03_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M04_AXI [get_bd_intf_pins ai_engine_0/M04_AXI] [get_bd_intf_pins axi_noc_1/S04_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M05_AXI [get_bd_intf_pins ai_engine_0/M05_AXI] [get_bd_intf_pins axi_noc_1/S05_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M06_AXI [get_bd_intf_pins ai_engine_0/M06_AXI] [get_bd_intf_pins axi_noc_1/S06_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M07_AXI [get_bd_intf_pins ai_engine_0/M07_AXI] [get_bd_intf_pins axi_noc_1/S07_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M08_AXI [get_bd_intf_pins ai_engine_0/M08_AXI] [get_bd_intf_pins axi_noc_1/S08_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M09_AXI [get_bd_intf_pins ai_engine_0/M09_AXI] [get_bd_intf_pins axi_noc_1/S09_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M10_AXI [get_bd_intf_pins ai_engine_0/M10_AXI] [get_bd_intf_pins axi_noc_1/S10_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M11_AXI [get_bd_intf_pins ai_engine_0/M11_AXI] [get_bd_intf_pins axi_noc_1/S11_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M12_AXI [get_bd_intf_pins ai_engine_0/M12_AXI] [get_bd_intf_pins axi_noc_1/S12_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M13_AXI [get_bd_intf_pins ai_engine_0/M13_AXI] [get_bd_intf_pins axi_noc_1/S13_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M14_AXI [get_bd_intf_pins ai_engine_0/M14_AXI] [get_bd_intf_pins axi_noc_1/S14_AXI] - connect_bd_intf_net -intf_net ai_engine_0_M15_AXI [get_bd_intf_pins ai_engine_0/M15_AXI] [get_bd_intf_pins axi_noc_1/S15_AXI] + connect_bd_intf_net -intf_net BLP_S_AXI_CTRL_USER_00_1 [get_bd_intf_ports BLP_S_AXI_CTRL_USER_00] [get_bd_intf_pins axi_ic_user/S00_AXI] + connect_bd_intf_net -intf_net BLP_S_INI_AIE_00_1 [get_bd_intf_ports BLP_S_INI_AIE_00] [get_bd_intf_pins axi_noc_aie_prog/S00_INI] + connect_bd_intf_net -intf_net M00_INI_0 [get_bd_intf_ports BLP_M_M00_INI_0] [get_bd_intf_pins axi_noc_kernel0/M00_INI] + connect_bd_intf_net -intf_net M01_INI_0 [get_bd_intf_ports BLP_M_M01_INI_0] [get_bd_intf_pins axi_noc_kernel0/M01_INI] + connect_bd_intf_net -intf_net M02_INI_0 [get_bd_intf_ports BLP_M_M02_INI_0] [get_bd_intf_pins axi_noc_kernel0/M02_INI] + connect_bd_intf_net -intf_net ai_engine_0_M00_AXI [get_bd_intf_pins ai_engine_0/M00_AXI] [get_bd_intf_pins axi_noc_aie_prog/S00_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M01_AXI [get_bd_intf_pins ai_engine_0/M01_AXI] [get_bd_intf_pins axi_noc_aie_prog/S01_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M02_AXI [get_bd_intf_pins ai_engine_0/M02_AXI] [get_bd_intf_pins axi_noc_aie_prog/S02_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M03_AXI [get_bd_intf_pins ai_engine_0/M03_AXI] [get_bd_intf_pins axi_noc_aie_prog/S03_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M04_AXI [get_bd_intf_pins ai_engine_0/M04_AXI] [get_bd_intf_pins axi_noc_aie_prog/S04_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M05_AXI [get_bd_intf_pins ai_engine_0/M05_AXI] [get_bd_intf_pins axi_noc_aie_prog/S05_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M06_AXI [get_bd_intf_pins ai_engine_0/M06_AXI] [get_bd_intf_pins axi_noc_aie_prog/S06_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M07_AXI [get_bd_intf_pins ai_engine_0/M07_AXI] [get_bd_intf_pins axi_noc_aie_prog/S07_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M08_AXI [get_bd_intf_pins ai_engine_0/M08_AXI] [get_bd_intf_pins axi_noc_aie_prog/S08_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M09_AXI [get_bd_intf_pins ai_engine_0/M09_AXI] [get_bd_intf_pins axi_noc_aie_prog/S09_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M10_AXI [get_bd_intf_pins ai_engine_0/M10_AXI] [get_bd_intf_pins axi_noc_aie_prog/S10_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M11_AXI [get_bd_intf_pins ai_engine_0/M11_AXI] [get_bd_intf_pins axi_noc_aie_prog/S11_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M12_AXI [get_bd_intf_pins ai_engine_0/M12_AXI] [get_bd_intf_pins axi_noc_aie_prog/S12_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M13_AXI [get_bd_intf_pins ai_engine_0/M13_AXI] [get_bd_intf_pins axi_noc_aie_prog/S13_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M14_AXI [get_bd_intf_pins ai_engine_0/M14_AXI] [get_bd_intf_pins axi_noc_aie_prog/S14_AXI] + connect_bd_intf_net -intf_net ai_engine_0_M15_AXI [get_bd_intf_pins ai_engine_0/M15_AXI] [get_bd_intf_pins axi_noc_aie_prog/S15_AXI] connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins emb_mem_gen_0/BRAM_PORTA] connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins emb_mem_gen_0/BRAM_PORTB] - connect_bd_intf_net -intf_net axi_noc_0_M00_INI [get_bd_intf_ports BLP_M_INI_MC_00] [get_bd_intf_pins axi_noc_0/M00_INI] - connect_bd_intf_net -intf_net axi_noc_0_M01_INI [get_bd_intf_ports BLP_M_INI_MC_01] [get_bd_intf_pins axi_noc_0/M01_INI] - connect_bd_intf_net -intf_net axi_noc_1_M00_AXI [get_bd_intf_pins ai_engine_0/S00_AXI] [get_bd_intf_pins axi_noc_1/M00_AXI] - connect_bd_intf_net -intf_net axi_noc_1_M01_AXI [get_bd_intf_pins axi_noc_1/M01_AXI] [get_bd_intf_pins smartconnect_2/S01_AXI] - connect_bd_intf_net -intf_net gt_null0_GT_Serial_0 [get_bd_intf_ports gt0_serial] [get_bd_intf_pins gt_null0/GT_Serial] - connect_bd_intf_net -intf_net gt_null1_GT_Serial_1 [get_bd_intf_ports gt1_serial] [get_bd_intf_pins gt_null1/GT_Serial] - connect_bd_intf_net -intf_net ii_level0_wire_0_BLP_M_AXI_DATA_C2H_00 [get_bd_intf_ports BLP_M_AXI_DATA_C2H_00] [get_bd_intf_pins ii_level0_wire_0/BLP_M_AXI_DATA_C2H_00] - connect_bd_intf_net -intf_net ii_level0_wire_0_ULP_M_AXI_CTRL_MGMT_00 [get_bd_intf_pins ii_level0_wire_0/ULP_M_AXI_CTRL_MGMT_00] [get_bd_intf_pins smartconnect_1/S00_AXI] - connect_bd_intf_net -intf_net ii_level0_wire_0_ULP_M_AXI_CTRL_USER_00 [get_bd_intf_pins ii_level0_wire_0/ULP_M_AXI_CTRL_USER_00] [get_bd_intf_pins smartconnect_0/S00_AXI] - connect_bd_intf_net -intf_net ${kernel}_0_m_axi_data_int [get_bd_intf_pins ${kernel}_0/m_axi_data_int] [get_bd_intf_pins smartconnect_3/S00_AXI] - connect_bd_intf_net -intf_net ${kernel}_0_m_axi_data_out [get_bd_intf_pins axi_noc_0/S00_AXI] [get_bd_intf_pins ${kernel}_0/m_axi_data_ext] - connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ${kernel}_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins freq_counter0/S_AXI] [get_bd_intf_pins smartconnect_1/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_1_M01_AXI [get_bd_intf_pins freq_counter1/S_AXI] [get_bd_intf_pins smartconnect_1/M01_AXI] - connect_bd_intf_net -intf_net smartconnect_1_M02_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_1/M02_AXI] - connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins smartconnect_2/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_3_M00_AXI [get_bd_intf_pins smartconnect_2/S00_AXI] [get_bd_intf_pins smartconnect_3/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_3_M01_AXI [get_bd_intf_pins axi_noc_1/S16_AXI] [get_bd_intf_pins smartconnect_3/M01_AXI] + connect_bd_intf_net -intf_net axi_ic_user_M00_AXI [get_bd_intf_pins axi_ic_user/M00_AXI] [get_bd_intf_pins axi_ic_user_extend/S00_AXI] + connect_bd_intf_net -intf_net axi_ic_user_M01_AXI [get_bd_intf_pins axi_ic_user/M01_AXI] [get_bd_intf_pins data_mover_mm2mm_0/s_axi_control] + connect_bd_intf_net -intf_net axi_ic_user_extend_M00_AXI [get_bd_intf_pins axi_gpio_null_user/S_AXI] [get_bd_intf_pins axi_ic_user_extend/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_aie_prog_M00_AXI [get_bd_intf_pins ai_engine_0/S00_AXI] [get_bd_intf_pins axi_noc_aie_prog/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_aie_prog_M01_AXI [get_bd_intf_pins axi_noc_aie_prog/M01_AXI] [get_bd_intf_pins smartconnect_1/S01_AXI] + connect_bd_intf_net -intf_net axi_noc_h2c_M00_AXI [get_bd_intf_pins axi_dbg_fw/S_AXI] [get_bd_intf_pins axi_noc_h2c/M00_AXI] + connect_bd_intf_net -intf_net axi_noc_h2c_M00_AXI_fw [get_bd_intf_pins axi_dbg_fw/M_AXI] [get_bd_intf_pins axi_dbg_hub/S_AXI] + connect_bd_intf_net -intf_net axi_noc_h2c_M01_AXI [get_bd_intf_pins axi_noc_h2c/M01_AXI] [get_bd_intf_pins axi_sc_plram/S00_AXI] + connect_bd_intf_net -intf_net axi_noc_h2c_S00_INI [get_bd_intf_ports BLP_S_INI_DBG_00] [get_bd_intf_pins axi_noc_h2c/S00_INI] + connect_bd_intf_net -intf_net axi_noc_h2c_S01_INI [get_bd_intf_ports BLP_S_INI_PLRAM_00] [get_bd_intf_pins axi_noc_h2c/S01_INI] + connect_bd_intf_net -intf_net axi_sc_plram_M00_AXI [get_bd_intf_pins axi_sc_plram/M00_AXI] [get_bd_intf_pins plram_ctrl/S_AXI] + connect_bd_intf_net -intf_net data_mover_mm2mm_0_m_axi_data_ext [get_bd_intf_pins axi_noc_kernel0/S00_AXI] [get_bd_intf_pins data_mover_mm2mm_0/m_axi_data_ext] + connect_bd_intf_net -intf_net data_mover_mm2mm_0_m_axi_data_int [get_bd_intf_pins data_mover_mm2mm_0/m_axi_data_int] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net plram_ctrl_BRAM_PORTA [get_bd_intf_pins plram_ctrl/BRAM_PORTA] [get_bd_intf_pins plram_ctrl_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins smartconnect_1/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_noc_aie_prog/S16_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins smartconnect_1/M00_AXI] # Create port connections - connect_bd_net -net Net [get_bd_ports blp_s_aclk_kernel_00] [get_bd_pins ai_engine_0/aclk0] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_noc_0/aclk0] [get_bd_pins axi_noc_1/aclk1] [get_bd_pins ii_level0_wire_0/blp_s_aclk_kernel_00] [get_bd_pins ${kernel}_0/ap_clk] [get_bd_pins smartconnect_0/aclk1] [get_bd_pins smartconnect_2/aclk] [get_bd_pins smartconnect_3/aclk] - connect_bd_net -net ai_engine_0_m00_axi_aclk [get_bd_pins ai_engine_0/m00_axi_aclk] [get_bd_pins axi_noc_1/aclk2] - connect_bd_net -net ai_engine_0_m01_axi_aclk [get_bd_pins ai_engine_0/m01_axi_aclk] [get_bd_pins axi_noc_1/aclk3] - connect_bd_net -net ai_engine_0_m02_axi_aclk [get_bd_pins ai_engine_0/m02_axi_aclk] [get_bd_pins axi_noc_1/aclk4] - connect_bd_net -net ai_engine_0_m03_axi_aclk [get_bd_pins ai_engine_0/m03_axi_aclk] [get_bd_pins axi_noc_1/aclk5] - connect_bd_net -net ai_engine_0_m04_axi_aclk [get_bd_pins ai_engine_0/m04_axi_aclk] [get_bd_pins axi_noc_1/aclk6] - connect_bd_net -net ai_engine_0_m05_axi_aclk [get_bd_pins ai_engine_0/m05_axi_aclk] [get_bd_pins axi_noc_1/aclk7] - connect_bd_net -net ai_engine_0_m06_axi_aclk [get_bd_pins ai_engine_0/m06_axi_aclk] [get_bd_pins axi_noc_1/aclk8] - connect_bd_net -net ai_engine_0_m07_axi_aclk [get_bd_pins ai_engine_0/m07_axi_aclk] [get_bd_pins axi_noc_1/aclk9] - connect_bd_net -net ai_engine_0_m08_axi_aclk [get_bd_pins ai_engine_0/m08_axi_aclk] [get_bd_pins axi_noc_1/aclk10] - connect_bd_net -net ai_engine_0_m09_axi_aclk [get_bd_pins ai_engine_0/m09_axi_aclk] [get_bd_pins axi_noc_1/aclk11] - connect_bd_net -net ai_engine_0_m10_axi_aclk [get_bd_pins ai_engine_0/m10_axi_aclk] [get_bd_pins axi_noc_1/aclk12] - connect_bd_net -net ai_engine_0_m11_axi_aclk [get_bd_pins ai_engine_0/m11_axi_aclk] [get_bd_pins axi_noc_1/aclk13] - connect_bd_net -net ai_engine_0_m12_axi_aclk [get_bd_pins ai_engine_0/m12_axi_aclk] [get_bd_pins axi_noc_1/aclk14] - connect_bd_net -net ai_engine_0_m13_axi_aclk [get_bd_pins ai_engine_0/m13_axi_aclk] [get_bd_pins axi_noc_1/aclk15] - connect_bd_net -net ai_engine_0_m14_axi_aclk [get_bd_pins ai_engine_0/m14_axi_aclk] [get_bd_pins axi_noc_1/aclk16] - connect_bd_net -net ai_engine_0_m15_axi_aclk [get_bd_pins ai_engine_0/m15_axi_aclk] [get_bd_pins axi_noc_1/aclk17] - connect_bd_net -net ai_engine_0_s00_axi_aclk [get_bd_pins ai_engine_0/s00_axi_aclk] [get_bd_pins axi_noc_1/aclk0] - connect_bd_net -net blp_s_aclk_ctrl_00_0_1 [get_bd_ports blp_s_aclk_ctrl_00] [get_bd_pins ii_level0_wire_0/blp_s_aclk_ctrl_00] - connect_bd_net -net blp_s_aclk_kernel_01_0_1 [get_bd_ports blp_s_aclk_kernel_01] [get_bd_pins ii_level0_wire_0/blp_s_aclk_kernel_01] - connect_bd_net -net blp_s_aclk_pcie_00_0_1 [get_bd_ports blp_s_aclk_pcie_00] [get_bd_pins ii_level0_wire_0/blp_s_aclk_pcie_00] - connect_bd_net -net blp_s_aresetn_pcie_reset_00_0_1 [get_bd_ports blp_s_aresetn_pcie_reset_00] [get_bd_pins ii_level0_wire_0/blp_s_aresetn_pcie_reset_00] - connect_bd_net -net blp_s_aresetn_pr_reset_00_0_1 [get_bd_ports blp_s_aresetn_pr_reset_00] [get_bd_pins ii_level0_wire_0/blp_s_aresetn_pr_reset_00] - connect_bd_net -net gt0_refclk_buf_IBUF_OUT [get_bd_pins gt0_refclk_buf/IBUF_OUT] [get_bd_pins gt_null0/gt_refclk] - connect_bd_net -net gt1_refclk_buf_IBUF_OUT [get_bd_pins gt1_refclk_buf/IBUF_OUT] [get_bd_pins gt_null1/gt_refclk] - connect_bd_net -net ii_level0_wire_0_blp_m_irq_kernel_00 [get_bd_ports blp_m_irq_kernel_00] [get_bd_pins ii_level0_wire_0/blp_m_irq_kernel_00] - connect_bd_net -net ii_level0_wire_0_ulp_m_aclk_ctrl_00 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins freq_counter0/s_axi_aclk] [get_bd_pins freq_counter1/s_axi_aclk] [get_bd_pins ii_level0_wire_0/ulp_m_aclk_ctrl_00] [get_bd_pins pipeline_reg_0/clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] - connect_bd_net -net ii_level0_wire_0_ulp_m_aclk_kernel_00 [get_bd_pins freq_counter0/test_clk0] [get_bd_pins ii_level0_wire_0/ulp_m_aclk_kernel_00] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] - connect_bd_net -net ii_level0_wire_0_ulp_m_aclk_kernel_01 [get_bd_pins freq_counter1/test_clk0] [get_bd_pins ii_level0_wire_0/ulp_m_aclk_kernel_01] - connect_bd_net -net ii_level0_wire_0_ulp_m_aresetn_pr_reset_00 [get_bd_pins ii_level0_wire_0/ulp_m_aresetn_pr_reset_00] [get_bd_pins pipeline_reg_0/d] [get_bd_pins proc_sys_reset_0/ext_reset_in] - connect_bd_net -net pipeline_reg_0_q [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins freq_counter0/s_axi_aresetn] [get_bd_pins freq_counter1/s_axi_aresetn] [get_bd_pins pipeline_reg_0/q] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins ${kernel}_0/ap_rst_n] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins smartconnect_2/aresetn] [get_bd_pins smartconnect_3/aresetn] - connect_bd_net -net xlconstant_0_dout [get_bd_pins ii_level0_wire_0/ulp_s_irq_kernel_00] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlconstant_1_dout [get_bd_pins pipeline_reg_0/resetn] [get_bd_pins xlconstant_1/dout] - connect_bd_net -net xlconstant_2_dout [get_bd_pins axi_gpio_0/gpio_io_i] [get_bd_pins xlconstant_2/dout] - connect_bd_net -net xlconstant_3_dout [get_bd_pins emb_mem_gen_0/regcea] [get_bd_pins emb_mem_gen_0/regceb] [get_bd_pins xlconstant_3/dout] + connect_bd_net -net ai_engine_0_m00_axi_aclk [get_bd_pins ai_engine_0/m00_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk2] + connect_bd_net -net ai_engine_0_m01_axi_aclk [get_bd_pins ai_engine_0/m01_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk3] + connect_bd_net -net ai_engine_0_m02_axi_aclk [get_bd_pins ai_engine_0/m02_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk4] + connect_bd_net -net ai_engine_0_m03_axi_aclk [get_bd_pins ai_engine_0/m03_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk5] + connect_bd_net -net ai_engine_0_m04_axi_aclk [get_bd_pins ai_engine_0/m04_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk6] + connect_bd_net -net ai_engine_0_m05_axi_aclk [get_bd_pins ai_engine_0/m05_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk7] + connect_bd_net -net ai_engine_0_m06_axi_aclk [get_bd_pins ai_engine_0/m06_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk8] + connect_bd_net -net ai_engine_0_m07_axi_aclk [get_bd_pins ai_engine_0/m07_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk9] + connect_bd_net -net ai_engine_0_m08_axi_aclk [get_bd_pins ai_engine_0/m08_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk10] + connect_bd_net -net ai_engine_0_m09_axi_aclk [get_bd_pins ai_engine_0/m09_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk11] + connect_bd_net -net ai_engine_0_m10_axi_aclk [get_bd_pins ai_engine_0/m10_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk12] + connect_bd_net -net ai_engine_0_m11_axi_aclk [get_bd_pins ai_engine_0/m11_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk13] + connect_bd_net -net ai_engine_0_m12_axi_aclk [get_bd_pins ai_engine_0/m12_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk14] + connect_bd_net -net ai_engine_0_m13_axi_aclk [get_bd_pins ai_engine_0/m13_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk15] + connect_bd_net -net ai_engine_0_m14_axi_aclk [get_bd_pins ai_engine_0/m14_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk16] + connect_bd_net -net ai_engine_0_m15_axi_aclk [get_bd_pins ai_engine_0/m15_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk17] + connect_bd_net -net ai_engine_0_s00_axi_aclk [get_bd_pins ai_engine_0/s00_axi_aclk] [get_bd_pins axi_noc_aie_prog/aclk0] + connect_bd_net -net axi_dbg_fw_mi_r_error [get_bd_pins axi_dbg_fw/mi_r_error] [get_bd_pins gate_dbgfw_or/Op2] + connect_bd_net -net axi_dbg_fw_mi_w_error [get_bd_pins axi_dbg_fw/mi_w_error] [get_bd_pins gate_dbgfw_or/Op1] + connect_bd_net -net blp_m_ext_tog_ctrl_kernel_00_enable_net [get_bd_ports blp_m_ext_tog_ctrl_kernel_00_enable] [get_bd_pins ip_gnd_ext_tog_kernel_00_null/dout] + connect_bd_net -net blp_m_ext_tog_ctrl_kernel_01_enable_net [get_bd_ports blp_m_ext_tog_ctrl_kernel_01_enable] [get_bd_pins ip_gnd_ext_tog_kernel_01_null/dout] + connect_bd_net -net blp_s_aclk_ctrl_00_1 [get_bd_ports blp_s_aclk_ctrl_00] [get_bd_pins axi_gpio_null_user/s_axi_aclk] [get_bd_pins axi_ic_user/aclk] [get_bd_pins axi_ic_user_extend/aclk] [get_bd_pins reset_controllers/clk_pl_axi] + connect_bd_net -net blp_s_aclk_ext_tog_kernel_00_net [get_bd_ports blp_s_aclk_ext_tog_kernel_00] [get_bd_pins ip_pipe_ext_tog_kernel_00_null/clk] + connect_bd_net -net blp_s_aclk_ext_tog_kernel_01_net [get_bd_ports blp_s_aclk_ext_tog_kernel_01] [get_bd_pins ip_pipe_ext_tog_kernel_01_null/clk] + connect_bd_net -net blp_s_aclk_kernel_00_1 [get_bd_ports blp_s_aclk_kernel_00] [get_bd_pins ai_engine_0/aclk0] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_ic_user/aclk1] [get_bd_pins axi_noc_aie_prog/aclk1] [get_bd_pins axi_noc_kernel0/aclk0] [get_bd_pins axi_sc_plram/aclk1] [get_bd_pins data_mover_mm2mm_0/ap_clk] [get_bd_pins plram_ctrl/s_axi_aclk] [get_bd_pins reset_controllers/clk_kernel0] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] + connect_bd_net -net blp_s_aclk_kernel_01_1 [get_bd_ports blp_s_aclk_kernel_01] [get_bd_pins reset_controllers/clk_kernel1] + connect_bd_net -net blp_s_aclk_pcie_00_1 [get_bd_ports blp_s_aclk_pcie_00] [get_bd_pins axi_dbg_fw/aclk] [get_bd_pins axi_dbg_hub/aclk] [get_bd_pins axi_noc_h2c/aclk0] [get_bd_pins axi_sc_plram/aclk] [get_bd_pins ip_pipe_dbg_hub_fw_00/clk] [get_bd_pins reset_controllers/clk_pcie] + connect_bd_net -net blp_s_aresetn_pcie_reset_00_1 [get_bd_ports blp_s_aresetn_pcie_reset_00] [get_bd_pins reset_controllers/resetn_pcie] + connect_bd_net -net blp_s_aresetn_pr_reset_00_1 [get_bd_ports blp_s_aresetn_pr_reset_00] [get_bd_pins reset_controllers/resetn_ulp] + connect_bd_net -net blp_s_ext_tog_ctrl_kernel_00_out_net [get_bd_ports blp_s_ext_tog_ctrl_kernel_00_out] [get_bd_pins ip_pipe_ext_tog_kernel_00_null/D] + connect_bd_net -net blp_s_ext_tog_ctrl_kernel_01_out_net [get_bd_ports blp_s_ext_tog_ctrl_kernel_01_out] [get_bd_pins ip_pipe_ext_tog_kernel_01_null/D] + connect_bd_net -net const_1_dout [get_bd_pins axi_dbg_fw/aresetn] [get_bd_pins const_1/dout] + connect_bd_net -net gate_dbgfw_or_Res [get_bd_pins gate_dbgfw_or/Res] [get_bd_pins ip_pipe_dbg_hub_fw_00/D] + connect_bd_net -net ip_pipe_dbg_hub_fw_00 [get_bd_ports blp_m_dbg_hub_fw_00] [get_bd_pins ip_pipe_dbg_hub_fw_00/Q] + connect_bd_net -net ip_pipe_ext_tog_kernel_00_null_q [get_bd_ports blp_m_ext_tog_ctrl_kernel_00_in] [get_bd_pins ip_pipe_ext_tog_kernel_00_null/Q] + connect_bd_net -net ip_pipe_ext_tog_kernel_01_null_q [get_bd_ports blp_m_ext_tog_ctrl_kernel_01_in] [get_bd_pins ip_pipe_ext_tog_kernel_01_null/Q] + connect_bd_net -net irq_const_tieoff_dout [get_bd_pins irq_const_tieoff/dout] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In0] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In2] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In3] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In4] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In5] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In6] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In7] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In8] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In9] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In10] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In11] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In12] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In13] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In14] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In15] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In16] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In17] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In18] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In19] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In20] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In21] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In22] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In23] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In24] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In25] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In26] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In27] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In28] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In29] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In30] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/In31] + connect_bd_net -net kernel_interrupt_xlconcat_0_In0_1_interrupt_concat_dout [get_bd_pins kernel_interrupt/In0] [get_bd_pins kernel_interrupt_xlconcat_0_In0_1_interrupt_concat/dout] + connect_bd_net -net kernel_interrupt_xlconcat_interrupt_dout [get_bd_ports blp_m_irq_kernel_00] [get_bd_pins kernel_interrupt/xlconcat_interrupt_dout] + connect_bd_net -net reset_controllers_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins data_mover_mm2mm_0/ap_rst_n] [get_bd_pins reset_controllers/peripheral_aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] + connect_bd_net -net reset_controllers_resetn_kernel0_ic [get_bd_pins axi_sc_plram/aresetn] [get_bd_pins plram_ctrl/s_axi_aresetn] [get_bd_pins reset_controllers/resetn_kernel0_ic] + connect_bd_net -net resetn_pcie_axi_net [get_bd_pins axi_dbg_hub/aresetn] [get_bd_pins reset_controllers/resetn_pcie_axi] + connect_bd_net -net resetn_pl_axi_net [get_bd_pins axi_gpio_null_user/s_axi_aresetn] [get_bd_pins axi_ic_user/aresetn] [get_bd_pins axi_ic_user_extend/aresetn] [get_bd_pins reset_controllers/resetn_pl_axi] + connect_bd_net -net xlconstant_0_dout [get_bd_pins emb_mem_gen_0/regcea] [get_bd_pins emb_mem_gen_0/regceb] [get_bd_pins xlconstant_0/dout] # Create address segments - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M00_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M01_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M02_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M03_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M04_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M05_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M06_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M07_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M08_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M09_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M10_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M11_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M12_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M13_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M14_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ai_engine_0/M15_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x008000000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ii_level0_wire_0/blp_m_axi_data_c2h_00] [get_bd_addr_segs BLP_M_AXI_DATA_C2H_00/Reg] -force - assign_bd_address -offset 0x00EFF000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ii_level0_wire_0/ulp_m_axi_ctrl_mgmt_00] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force - assign_bd_address -offset 0x00F00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ii_level0_wire_0/ulp_m_axi_ctrl_mgmt_00] [get_bd_addr_segs freq_counter0/S_AXI/reg0] -force - assign_bd_address -offset 0x00F01000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ii_level0_wire_0/ulp_m_axi_ctrl_mgmt_00] [get_bd_addr_segs freq_counter1/S_AXI/reg0] -force - assign_bd_address -offset 0x00000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ii_level0_wire_0/ulp_m_axi_ctrl_user_00] [get_bd_addr_segs ${kernel}_0/s_axi_control/reg0] -force - assign_bd_address -offset 0x00C0000000000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ${kernel}_0/m_axi_data_ext] [get_bd_addr_segs BLP_M_INI_MC_00/Reg] -force - assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces ${kernel}_0/m_axi_data_int] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force - assign_bd_address -offset 0x020100000000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ${kernel}_0/m_axi_data_int] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M00_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M01_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M02_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M03_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M04_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M05_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M06_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M07_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M08_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M09_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M10_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M11_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M12_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M13_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M14_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces ai_engine_0/M15_AXI] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x00C100000000 -range 0x000300000000 -target_address_space [get_bd_addr_spaces data_mover_mm2mm_0/m_axi_data_ext] [get_bd_addr_segs BLP_M_M00_INI_0/Reg] -force + assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces data_mover_mm2mm_0/m_axi_data_int] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force + assign_bd_address -offset 0x020100000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces data_mover_mm2mm_0/m_axi_data_int] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x020200000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces BLP_S_AXI_CTRL_USER_00] [get_bd_addr_segs axi_gpio_null_user/S_AXI/Reg] -force + assign_bd_address -offset 0x020200001000 -range 0x00001000 -target_address_space [get_bd_addr_spaces BLP_S_AXI_CTRL_USER_00] [get_bd_addr_segs data_mover_mm2mm_0/s_axi_control/reg0] -force assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces BLP_S_INI_AIE_00] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force - assign_bd_address -offset 0x00000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces BLP_S_AXI_CTRL_MGMT_00] [get_bd_addr_segs ii_level0_wire_0/blp_s_axi_ctrl_mgmt_00/CTRL_MGMT_00] -force - assign_bd_address -offset 0x00000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces BLP_S_AXI_CTRL_USER_00] [get_bd_addr_segs ii_level0_wire_0/blp_s_axi_ctrl_user_00/CTRL_USER_00] -force - assign_bd_address -offset 0x020204000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces BLP_S_AXI_DATA_H2C_00] [get_bd_addr_segs ii_level0_wire_0/blp_s_axi_data_h2c_00/UNKNOWN_SEGMENTS_00] -force + assign_bd_address -offset 0x020205800000 -range 0x00200000 -target_address_space [get_bd_addr_spaces BLP_S_INI_DBG_00] [get_bd_addr_segs axi_dbg_hub/S_AXI_DBG_HUB/Mem0] -force + assign_bd_address -offset 0x020204000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces BLP_S_INI_PLRAM_00] [get_bd_addr_segs plram_ctrl/S_AXI/Mem0] -force # Restore current instance current_bd_instance $oldCurInst + # Create PFM attributes + set_property PFM_NAME {xilinx:vck5000:gen4x8_qdma_2:202220.1} [get_files [current_bd_design].bd] + set_property PFM.CLOCK { clk_100m {id "2" is_default "false" proc_sys_reset "reset_controllers/reset_sync_fixed" status "fixed" freq_hz "100000000"} } [get_bd_ports /blp_s_aclk_ctrl_00] + set_property PFM.CLOCK { clk_out0 {id "0" is_default "true" proc_sys_reset "reset_controllers/reset_sync_kernel0"} } [get_bd_ports /blp_s_aclk_kernel_00] + set_property PFM.CLOCK { clk_out1 {id "1" is_default "false" proc_sys_reset "reset_controllers/reset_sync_kernel1"} } [get_bd_ports /blp_s_aclk_kernel_01] + set_property PFM.AXI_PORT {M02_AXI { memport "M_AXI_GP" } M03_AXI { memport "M_AXI_GP" } M04_AXI { memport "M_AXI_GP" } M05_AXI { memport "M_AXI_GP" } M06_AXI { memport "M_AXI_GP" } M07_AXI { memport "M_AXI_GP" } M08_AXI { memport "M_AXI_GP" } M09_AXI { memport "M_AXI_GP" } M10_AXI { memport "M_AXI_GP" } M11_AXI { memport "M_AXI_GP" } M12_AXI { memport "M_AXI_GP" } M13_AXI { memport "M_AXI_GP" } M14_AXI { memport "M_AXI_GP" } M15_AXI { memport "M_AXI_GP" } } [get_bd_cells /axi_ic_user] + set_property PFM.AXI_PORT {M01_AXI {memport "M_AXI_GP"} M02_AXI {memport "M_AXI_GP"} M03_AXI {memport "M_AXI_GP"} M04_AXI {memport "M_AXI_GP"} M05_AXI {memport "M_AXI_GP"} M06_AXI {memport "M_AXI_GP"} M07_AXI {memport "M_AXI_GP"} M08_AXI {memport "M_AXI_GP"} M09_AXI {memport "M_AXI_GP"} M10_AXI {memport "M_AXI_GP"} M11_AXI {memport "M_AXI_GP"} M12_AXI {memport "M_AXI_GP"} M13_AXI {memport "M_AXI_GP"} M14_AXI {memport "M_AXI_GP"} M15_AXI {memport "M_AXI_GP"}} [get_bd_cells /axi_ic_user_extend] + set_property PFM.AXI_PORT {S03_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S04_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S05_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S06_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S07_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S08_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S09_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S10_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S11_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S12_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S13_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S14_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S15_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S16_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S17_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S18_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S19_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S20_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S21_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S22_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S23_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S24_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } S25_AXI { memport "S_AXI_NOC" sptag "MC_NOC0" } } [get_bd_cells /axi_noc_kernel0] + set_property PFM.AXI_PORT {S01_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S02_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S03_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S04_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S05_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S06_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S07_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S08_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S09_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S10_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S11_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S12_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S13_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S14_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"} S15_AXI {memport "S_AXI_HP" sptag "BRAM" memory "plram_ctrl Mem0" auto "false"}} [get_bd_cells /axi_sc_plram] + + validate_bd_design save_bd_design } @@ -1104,6 +1255,6 @@ proc create_root_design { parentCell kernel } { # MAIN FLOW ################################################################## -create_root_design "" $kernel +create_root_design "" diff --git a/xclbin_generator/boot_image.bif b/xclbin_generator/boot_image.bif index a5f1da1..fd46907 100644 --- a/xclbin_generator/boot_image.bif +++ b/xclbin_generator/boot_image.bif @@ -2,7 +2,7 @@ all: { image { - { type=bootimage, file=level0_i_ulp_my_rm_partial.pdi } + { type=bootimage, file=top_i_ulp_my_rm_partial.pdi } } image { diff --git a/xclbin_generator/embedded_metadata_data_mover_mm2mm.xml b/xclbin_generator/embedded_metadata_data_mover_mm2mm.xml index 37a605a..8c8c441 100644 --- a/xclbin_generator/embedded_metadata_data_mover_mm2mm.xml +++ b/xclbin_generator/embedded_metadata_data_mover_mm2mm.xml @@ -1,11 +1,11 @@ - + - + diff --git a/xclbin_generator/ip_layout_data_mover_mm2mm.json b/xclbin_generator/ip_layout_data_mover_mm2mm.json new file mode 100644 index 0000000..3ded553 --- /dev/null +++ b/xclbin_generator/ip_layout_data_mover_mm2mm.json @@ -0,0 +1,15 @@ +{ + "ip_layout": { + "m_count": "1", + "m_ip_data": [ + { + "m_type": "IP_KERNEL", + "m_int_enable": "1", + "m_interrupt_id": "1", + "m_ip_control": "AP_CTRL_HS", + "m_base_address": "0x20200001000", + "m_name": "data_mover_mm2mm:data_mover_mm2mm" + } + ] + } +} diff --git a/xclbin_generator/ip_layout.json b/xclbin_generator/ip_layout_vecadd.json similarity index 100% rename from xclbin_generator/ip_layout.json rename to xclbin_generator/ip_layout_vecadd.json diff --git a/xclbin_generator/xclbin_gen.sh b/xclbin_generator/xclbin_gen.sh index b3da01d..2380d70 100755 --- a/xclbin_generator/xclbin_gen.sh +++ b/xclbin_generator/xclbin_gen.sh @@ -1,6 +1,6 @@ #!/bin/bash rm -f ulp.xclbin -xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:top_i_ulp_my_rm_partial.pdi --force --target hw --key-value SYS:dfx_enable:true --add-section IP_LAYOUT:JSON:ip_layout.json --add-section MEM_TOPOLOGY:JSON:mem_topology.json --add-section PARTITION_METADATA:JSON:partition_metadata.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_vecadd.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen4x8_qdma_2_202220_1 --output ulp.xclbin +xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:top_i_ulp_my_rm_partial.pdi --force --target hw --key-value SYS:dfx_enable:true --add-section IP_LAYOUT:JSON:ip_layout_vecadd.json --add-section MEM_TOPOLOGY:JSON:mem_topology.json --add-section PARTITION_METADATA:JSON:partition_metadata.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_vecadd.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen4x8_qdma_2_202220_1 --output ulp.xclbin xclbinutil --quiet --force --info ulp.xclbin.info --input ulp.xclbin diff --git a/xclbin_generator/xclbin_gen_with_aie.sh b/xclbin_generator/xclbin_gen_with_aie.sh index 8116a1e..4776a2b 100755 --- a/xclbin_generator/xclbin_gen_with_aie.sh +++ b/xclbin_generator/xclbin_gen_with_aie.sh @@ -3,6 +3,6 @@ rm -f boot.bin ulp.xclbin bootgen -arch versal -image boot_image.bif -w -o boot.bin -xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:boot.bin --force --target hw --key-value SYS:dfx_enable:true --add-section :JSON:kernel_data_mover_mm2mm.json --append-section :JSON:appendSection.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_data_mover_mm2mm.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen3x16_xdma_1_202120_1 --output ulp.xclbin +xclbinutil --add-section BITSTREAM_PARTIAL_PDI:raw:boot.bin --force --target hw --key-value SYS:dfx_enable:true --add-section IP_LAYOUT:JSON:ip_layout_data_mover_mm2mm.json --add-section MEM_TOPOLOGY:JSON:mem_topology.json --add-section PARTITION_METADATA:JSON:partition_metadata.json --add-section CLOCK_FREQ_TOPOLOGY:JSON:clock_freq_topology.json --add-section EMBEDDED_METADATA:RAW:embedded_metadata_data_mover_mm2mm.xml --key-value SYS:PlatformVBNV:xilinx_vck5000_gen4x8_qdma_2_202220_1 --output ulp.xclbin xclbinutil --quiet --force --info ulp.xclbin.info --input ulp.xclbin