-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathEDA_Routing_multipath.cpp
More file actions
4315 lines (3703 loc) · 127 KB
/
EDA_Routing_multipath.cpp
File metadata and controls
4315 lines (3703 loc) · 127 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#define _CRT_SECURE_NO_WARNINGS
#include <iostream>
#include <stdlib.h>
#include <fstream>
#include <string.h>
#include <math.h>
#include<algorithm>
#include <string>
#include <cmath>
#include <ctime>
#include <sstream>
#include <vector>
#include <unordered_set>
#include <unordered_map>
#include <utility>
#include <functional>
#include <iomanip>
#include <numeric>
#include<random>
#include <iterator>
#include <cassert>
#include<queue>
using namespace std;
#define MININT -2147483648
#define MAXINT 2147483647
#define RANDMAX 999
#define SDF_MAX(a,b) ((a)>(b)?(a):(b))
#define SDF_MIN(a,b) ((a)<(b)?(a):(b))
#define BEAMWIDTH 3//邻域1参数
#define RATIO 0.1 // 邻域1 topk的保留范围
#define Max_kdepth 5//邻域1参数
#define SHORTESTROB 0.8//邻域2参数
#define ADJUSTRATIO 0.5//邻域3参数
#define TRMPLAYER 20 //每个温度尝试次数
//***********************************************************//
char* rep;
char nameFinalResult[256];
char nameSchedule[256];
char cutname[256];
char outRoute[256];
char outTopo[256];
//***********************************************************//
char* caseName;
char* designInfo;
char* designNet;
char* designTopo;
char* designFpgaOut;
int seed;
double maxRunTime;
double beginTime;
double bestTime;
int nonImproved;
int maxnoImproved;
int numFPGA; //FPGA数量
int numNet; //Net数量
int numNode; //逻辑节点数量
int numTunnel; //原有通道数量
int numAddedTunnel; //增加的通道数量
int R_max; //最大TDM比率
double T; //温度
double T0;
int** weight_matrix; //FPGA间的连接通道矩阵
int** delta_weight_matrix; //FPGA间变动的通道数量矩阵
int** global_delta_weight_matrix; //搜索到的最优:FPGA间变动的通道数量矩阵
int** nets_count_matrix; //跨越各FPGA之间通道的net数量
int* FPGA_max_weight; //各FPGA最大对外的连接通道数量
int* FPGA_weight; // 各FPGA当前的对外连接通道数量
int* nodes_FPGA; //各逻辑节点对应的FPGA编号
int* length_FPGA_nodes; //各FPGA对应的逻辑节点数量
int** FPGA_nodes; // 各FPGA对应的逻辑节点列表
vector<pair<int, int>> added_arc_record; //增加的通道位置记录
struct PairHash
{
size_t operator()(const std::pair<int, int>& p) const noexcept
{
// 常见的组合哈希写法:避免简单拼接带来的冲突
return std::hash<int>{}(p.first) ^ (std::hash<int>{}(p.second) << 1);
}
};
/*net的结构体*/
typedef struct
{
int source_node; //net的起点
int sink_num; // net的终点数量
vector<int> sink_nodes; //net的终点
vector<vector<pair<int, int>>> path; //路径,0-1三维矩阵:起点到每个终点选择的边,第一维标记终点序号,后两维度是0-1矩阵表示选择的边
unordered_map<pair<int, int>, int, PairHash> path_map; // 所有路径中边与其对应的使用数量
vector<double> path_delay; //每条路径的延时
}Net;
vector<Net> Global, Current; // 所有net的数组,Global记录找到的最优解,Cureent记录搜索过程中变化的解
double* net_delay; // 每个net的延时,用于存储找到的全局最优
double* Global_net_delay; // Global_delay对应的net_delay;
double Global_delay;//Global对应的延迟
//快速排序
void qsort_double(double* s, int* address, int l, int r)//降序
{
if (l >= r) { return; }
if (l < r)
{
int i = l, j = r;
double x = s[l];
int y = address[l];
while (i < j)
{
while (i < j && s[j] <= x)
j--;
if (i < j)
{
s[i] = s[j];
address[i] = address[j];
i++;
}
while (i < j && s[i] > x)
i++;
if (i < j)
{
s[j] = s[i];
address[j] = address[i];
j--;
}
}
s[i] = x;
address[i] = y;
qsort_double(s, address, l, i - 1);
qsort_double(s, address, i + 1, r);
}
}
//快速排序
void qsort_vector(vector<double>& s, vector<int>& address, int l, int r)//升序
{
if (l >= r) { return; }
if (l < r)
{
int i = l, j = r;
//double x = s[l + ((r - l) >> 1)];
//int y = address[l + ((r - l) >> 1)];
double x = s[l];
int y = address[l];
while (i < j)
{
while (i < j && s[j] >= x)
j--;
if (i < j)
{
s[i] = s[j];
address[i] = address[j];
i++;
}
while (i < j && s[i] < x)
i++;
if (i < j)
{
s[j] = s[i];
address[j] = address[i];
j--;
}
}
s[i] = x;
address[i] = y;
qsort_vector(s, address, l, i - 1);
qsort_vector(s, address, i + 1, r);
}
}
// ---------- 2) 向量版本:保留升序前 k 小 ----------
void topk_asc_vector(vector<double>& s, vector<int>& address, int k)
{
int n = (int)s.size();
assert((int)address.size() == n);
if (n <= 0 || k <= 0)
{
return;
}
if (k > n)
{
k = n;
}
struct Node
{
double v;
int id;
// 默认优先队列是大根堆;为了“保留最小的 k 个”,我们让堆顶是当前 top-k 中最大的
bool operator<(const Node& o) const { return v < o.v; } // v 大的更“优先”
};
priority_queue<Node> heap; // 大根堆(堆顶是最大)
for (int i = 0; i < n; ++i)
{
if ((int)heap.size() < k)
{
heap.push(Node{ s[i], address[i] });
}
else if (s[i] < heap.top().v)
{
heap.pop();
heap.push(Node{ s[i], address[i] });
}
}
vector<Node> topk;
topk.reserve(k);
while (!heap.empty())
{
topk.push_back(heap.top());
heap.pop();
}
sort(topk.begin(), topk.end(), [](const Node& a, const Node& b)
{
return a.v < b.v; // 升序
});
for (int i = 0; i < k; ++i)
{
s[i] = topk[i].v;
address[i] = topk[i].id;
}
}
void read_instance()
{
char temp_caseName[50];
char designInfoName[50];
char designNetName[50];
char designTopoName[50];
char designFpgaOutName[50];
//strcpy_s(temp_caseName, caseName);
//strcat_s(temp_caseName, sizeof(temp_caseName), "/");
//strcpy_s(designInfoName, temp_caseName);
//strcpy_s(designNetName, temp_caseName);
//strcpy_s(designTopoName, temp_caseName);
//strcpy_s(designFpgaOutName, temp_caseName);
//strcat_s(designInfoName, sizeof(designInfoName), designInfo);
//strcat_s(designNetName, sizeof(designNetName), designNet);
//strcat_s(designTopoName, sizeof(designTopoName), designTopo);
//strcat_s(designFpgaOutName, sizeof(designFpgaOutName), designFpgaOut);
std::snprintf(temp_caseName, sizeof temp_caseName, "%s/", caseName);
std::snprintf(designInfoName, sizeof designInfoName, "%s%s", temp_caseName, designInfo);
std::snprintf(designNetName, sizeof designNetName, "%s%s", temp_caseName, designNet);
std::snprintf(designTopoName, sizeof designTopoName, "%s%s", temp_caseName, designTopo);
std::snprintf(designFpgaOutName, sizeof designFpgaOutName, "%s%s", temp_caseName, designFpgaOut);
R_max = 512; //最大TDM比率
T = 500.0;
ifstream FIC;
FIC.open(designInfoName);
if (FIC.fail())
{
cout << "1-can not open the file " << designInfoName << endl;
exit(0);
}
if (FIC.eof())
{
cout << "2-can not open the file " << designInfoName << endl;
}
char str_reading[100];
numFPGA = 0;
while (!FIC.eof())
{
FIC >> str_reading;
numFPGA++;
}
numFPGA = numFPGA / 2;
FIC.close();
FPGA_max_weight = new int[numFPGA + 1];
FPGA_weight = new int[numFPGA + 1];
FIC.open(designInfoName);
if (FIC.fail())
{
cout << "1-can not open the file " << designInfoName << endl;
exit(0);
}
if (FIC.eof())
{
cout << "2-can not open the file " << designInfoName << endl;
}
int FPGA_index = 1;
for (int x = 0; x < numFPGA * 2; x++)
{
FIC >> str_reading;
if (x % 2 != 0)
{
FPGA_max_weight[FPGA_index] = atoi(str_reading);
FPGA_weight[FPGA_index] = 0;
FPGA_index++;
}
}
FIC.close();
FPGA_max_weight[0] = 0;
std::string net_line;
numNet = 0;
int net_index = 0;
int max_node_index = MININT;
FIC.open(designNetName);
if (FIC.fail())
{
cout << "1-can not open the file " << designNetName << endl;
exit(0);
}
if (FIC.eof())
{
cout << "2-can not open the file " << designNetName << endl;
}
while (std::getline(FIC, net_line))
{
Net read_net;
std::istringstream iss(net_line);
std::string token;
int node_count = 0;
int token_count = 0;
int sink_count = 0;
while (iss >> token)
{
if (token[0] == 'g')
{
if (token_count == 0)
{
read_net.source_node = std::stoi(token.substr(1));
if (read_net.source_node > max_node_index)
max_node_index = read_net.source_node;
token_count++;
}
else
{
read_net.sink_nodes.push_back(std::stoi(token.substr(1)));
if (std::stoi(token.substr(1)) > max_node_index)
max_node_index = std::stoi(token.substr(1));
sink_count++;
token_count++;
}
}
}
read_net.sink_num = (int)read_net.sink_nodes.size();
Global.push_back(read_net);
Current.push_back(read_net);
numNet++;
}
net_delay = new double[numNet];
Global_net_delay = new double[numNet];
for (int x = 0; x < numNet; x++)
{
net_delay[x] = (double)MAXINT;
Global_net_delay[x] = (double)MAXINT;
}
numNode = max_node_index;
FIC.close();
weight_matrix = new int* [numFPGA + 1];
delta_weight_matrix = new int* [numFPGA + 1];
global_delta_weight_matrix = new int* [numFPGA + 1];
nets_count_matrix = new int* [numFPGA + 1];
for (int i = 0; i < numFPGA + 1; i++)
{
weight_matrix[i] = new int[numFPGA + 1];
delta_weight_matrix[i] = new int[numFPGA + 1];
global_delta_weight_matrix[i] = new int[numFPGA + 1];
nets_count_matrix[i] = new int[numFPGA + 1];
for (int j = 0; j < numFPGA + 1; j++)
{
weight_matrix[i][j] = 0;
delta_weight_matrix[i][j] = 0;
global_delta_weight_matrix[i][j] = 0;
nets_count_matrix[i][j] = 0;
}
}
std::string topo_line;
FIC.open(designTopoName);
if (FIC.fail())
{
cout << "1-can not open the file " << designTopoName << endl;
exit(0);
}
if (FIC.eof())
{
cout << "2-can not open the file " << designTopoName << endl;
}
for (int i = 0; i <= numFPGA; i++)
{
if (i == 0)
continue;
FIC >> topo_line;
FIC >> topo_line;
std::stringstream ss(topo_line);
std::string token;
int index = 1;
while (std::getline(ss, token, ','))
{
if (index <= numFPGA)
{
weight_matrix[i][index] = std::stoi(token);
index++;
}
}
if (index != numFPGA + 1)
{
cout << "weight_matrix size error! should be " << numFPGA << " actual " << index;
exit(-1);
}
}
FIC.close();
numTunnel = 0;
numAddedTunnel = 0;
for (int i = 0; i < numFPGA + 1; i++)
{
int sum_tunnel = 0;
for (int j = 0; j < numFPGA + 1; j++)
{
if (weight_matrix[i][j] > 0)
{
if (i < j)
numTunnel += weight_matrix[i][j];
sum_tunnel += weight_matrix[i][j];
}
}
FPGA_weight[i] = sum_tunnel;
}
nodes_FPGA = new int[numNode + 1];
for (int x = 0; x < numNode + 1; x++)
nodes_FPGA[x] = 0;
length_FPGA_nodes = new int[numFPGA + 1];
FPGA_nodes = new int* [numFPGA + 1];
for (int i = 0; i < numFPGA + 1; i++)
{
length_FPGA_nodes[i] = 0;
FPGA_nodes[i] = new int[numNode + 1];
for (int j = 0; j < numNode + 1; j++)
FPGA_nodes[i][j] = -1;
}
std::string fpga_out_line;
FIC.open(designFpgaOutName);
if (FIC.fail())
{
cout << "1-can not open the file " << designFpgaOutName << endl;
exit(0);
}
if (FIC.eof())
{
cout << "2-can not open the file " << designFpgaOutName << endl;
}
int fpga_index = 1;
while (std::getline(FIC, fpga_out_line))
{
std::istringstream iss(fpga_out_line);
std::string token;
int nodes_count = 1;
while (iss >> token)
{
if (token[0] == 'g' && fpga_index < numFPGA + 1 && nodes_count < numNode + 1)
{
FPGA_nodes[fpga_index][nodes_count] = std::stoi(token.substr(1));
if (FPGA_nodes[fpga_index][nodes_count] < numNode + 1)
nodes_FPGA[FPGA_nodes[fpga_index][nodes_count]] = fpga_index;
nodes_count++;
}
}
if (fpga_index < numFPGA + 1)
length_FPGA_nodes[fpga_index] = nodes_count - 1;
fpga_index++;
}
FIC.close();
cout << "Successfully read and load all the data!" << endl;
}
void check_read_instance() {
cout << numFPGA << ' ' << numNet << ' ' << numNode << endl;
cout << "FPGA_max_weight: "; for (int i = 1; i <= numFPGA; i++) { cout << FPGA_max_weight[i] << ' '; }cout << endl;
cout << "weight_matrix: " << endl;
for (int i = 1; i <= numFPGA; i++) {
for (int j = 1; j <= numFPGA; j++) {
cout << weight_matrix[i][j] << ' ';
}
cout << endl;
}
cout << "delta_weight_matrix:" << endl;
for (int i = 1; i <= numFPGA; i++)
{
for (int j = 1; j <= numFPGA; j++)
{
cout << delta_weight_matrix[i][j] << ' ';
}
cout << endl;
}
cout << "nets_count_matrix: " << endl;
for (int i = 1; i <= numFPGA; i++)
{
for (int j = 1; j <= numFPGA; j++)
{
cout << nets_count_matrix[i][j] << ' ';
}
cout << endl;
}
cout << "nodes_FPGA: ";
for (int i = 1; i <= numNode; i++)
{
cout << nodes_FPGA[i] << ' ';
}
cout << endl;
cout << "length_FPGA_nodes: ";
for (int i = 1; i <= numFPGA; i++)
{
cout << length_FPGA_nodes[i] << ' ';
}
cout << endl;
cout << "FPGA_nodes: " << endl;
for (int i = 1; i <= numFPGA; i++)
{
for (int j = 1; j <= length_FPGA_nodes[i]; j++)
{
cout << FPGA_nodes[i][j] << ' ';
}
cout << endl;
}
}
inline int ceil8(double x) { return static_cast<int>(std::ceil(x / 8.0) * 8.0); } // 取8的倍数
bool check_result(vector<Net>& Input_Netgroup, int** delta_weight_M)
{
//cout << "There is no new topo file" << endl;
// 2) 从零统计每对 (u,v) 的 nets_count(无向 + 每 net 只计一次)
std::vector<std::vector<int>> nets_count(numFPGA + 1, std::vector<int>(numFPGA + 1, 0));
for (int k = 0; k < (int)Input_Netgroup.size(); ++k) {
// 无向去重:同一 net 中,同一无向通道只计一次
std::unordered_set<long long> used_once_undirected;
used_once_undirected.reserve(512);
for (int j = 0; j < (int)Input_Netgroup[k].path.size(); ++j) {
const auto& edges = Input_Netgroup[k].path[j];
for (int m = 0; m < (int)edges.size(); ++m) {
int u = edges[m].first;
int v = edges[m].second;
if (u == v) continue;
// 规范为无向 (a<b)
int a = (u < v) ? u : v;
int b = (u < v) ? v : u;
long long key = ((long long)a << 32) | (unsigned int)b;
if (used_once_undirected.insert(key).second) {
// 对称计数,保证矩阵对称
nets_count[a][b] += 1;
nets_count[b][a] += 1;
}
}
}
}
// ---------- (A) 单次(i<j)循环合并:改动规模 + TDM + 容量累计 ----------
int total_physical_links = 0; // Σ weight(i,j)
int delta_sum = 0; // Σ |delta(i,j)|
vector<int> sum_conn(numFPGA + 1, 0); // 每个FPGA的对外连接数
vector<int> change_per_fpga(numFPGA + 1, 0);//每个FPGA的对外连接变化
//cout << endl << "Check FPGA channel capacity constraint" << endl;
for (int i = 1; i <= numFPGA; ++i) {
for (int j = i + 1; j <= numFPGA; ++j) {
int phys = weight_matrix[i][j] + delta_weight_M[i][j];
total_physical_links += weight_matrix[i][j];
int d_abs = abs(delta_weight_M[i][j]);
delta_sum += d_abs;
change_per_fpga[i] += d_abs;
change_per_fpga[j] += d_abs;
sum_conn[i] += phys;
sum_conn[j] += phys;
// TDM & 物理缺失
int nets_on_pair = nets_count[i][j];
if (nets_on_pair > 0 && phys == 0) {
cout << "[E1] Denominator is zero in ratio calculation: pair(" << i << "," << j
<< ") nets=" << nets_on_pair << ", phys=0\n";//ratio计算中分母为0
return false;
}
else if (phys == 0) {
continue; // nets=0且phys=0,跳过
}
// TDM计算:先 ceil(nets/phys),再 ceil 到8的倍数,≤512
int tdm_q = (((int)ceil((double)nets_on_pair / (double)phys) + 7) & ~7);
if (tdm_q > 512) {
std::cout << "[E2] TDM ratio exceeds limit for pair(" << i << "," << j << "): ceil("
<< nets_on_pair << "/" << phys << ")=" << ceil(nets_on_pair / phys)
<< ", quantized=" << tdm_q << " > 512\n";//TDM 超限
return false;
}
}
}
//cout << "All FPGA channel capacity satisfies the constraint" << endl;
//cout << "Total number of connection is: " << std::fixed << std::setprecision(1)
// << (double)total_physical_links << endl << endl;
// ---------- (B) 改动规模约束 ----------
if (delta_sum > total_physical_links * 0.3) {
std::cout << "[E3] Total delta change exceeds limit: delta_sum=" << delta_sum
<< " > limit=" << total_physical_links * 0.3 << "\n";//改动规模超限
return false;
}
//cout << "Check channel reconfiguration scope constraint" << endl;
//cout << "Detail info of changing connections :" << endl;
//for (int f = 1; f <= numFPGA; ++f)
// cout << "Number of changing connections of FPGA F" << f << " is: "
// << change_per_fpga[f] << endl;
//cout << "Total number of changing connections: " << std::fixed << std::setprecision(1)
// << (double)delta_sum << endl;
//cout << "The variation in connection channels satisfies the constraints" << endl << endl;
// ---------- (C) 通道容量约束 ----------
for (int i = 1; i <= numFPGA; ++i) {
if (sum_conn[i] > FPGA_max_weight[i]) {
std::cout << "[E4] Channel capacity exceeded: FPGA " << i
<< " total=" << sum_conn[i]
<< " > max=" << FPGA_max_weight[i] << "\n";//容量超限
return false;
}
}
//cout << "Check the max ratio constraints:" << endl;
//for (int i = 1; i <= numFPGA; ++i) {
// for (int j = i + 1; j <= numFPGA; ++j) {
// if (nets_count[i][j] <= 0) continue; // 跳过net=0的pair
// int nets_on_pair = nets_count[i][j];
// int phys = weight_matrix[i][j] + delta_weight_M[i][j];
// cout << "FPGA pair (" << i << ", " << j << "): "
// << nets_on_pair << " nets" << endl;
// cout << "FPGA pair (" << i << ", " << j << ") has "
// << phys << " connections, limit is " << 512 * phys << "!" << endl;
// }
//}
//cout << "All FPGA pairs are within the net limit." << endl << endl;
// ---------- (D) 路径检查 ----------
for (int k = 0; k < (int)Input_Netgroup.size(); ++k) {
for (int t = 0; t < (int)Input_Netgroup[k].path.size(); ++t) {
const auto& P = Input_Netgroup[k].path[t];
if (P.empty()) continue;
int s_fpga = nodes_FPGA[Input_Netgroup[k].source_node];
int g_fpga = nodes_FPGA[Input_Netgroup[k].sink_nodes[t]];
int cur = s_fpga;
// 记录已到达过的节点,防环
std::vector<char> visited(numFPGA + 1, 0);
if (cur >= 1 && cur <= numFPGA) visited[cur] = 1;
for (int e = 0; e < (int)P.size(); ++e) {
int u = P[e].first;
int v = P[e].second;
// 1) 有向连续性
if (u != cur) {
std::cout << "[E5] Logical path discontinuity in net " << k
<< " sinkIdx " << t << " cur=" << cur
<< " edge=(" << u << "," << v << ")\n";
return false;
}
// 2) 物理可达性(含 delta)
int phys = weight_matrix[u][v] + delta_weight_M[u][v];
if (phys <= 0) {
std::cout << "[E6] Physical edge missing for net " << k
<< " sinkIdx " << t << " edge=(" << u << "," << v << ")\n";
return false;
}
// 3) 成环检查:不能回到此前访问过的任意节点
if (v >= 1 && v <= numFPGA && visited[v]) {
std::cout << "[E7] Cycle detected in net " << k
<< " sinkIdx " << t << " revisiting node " << v << "\n";
return false;
}
// 前进并标记
cur = v;
if (cur >= 1 && cur <= numFPGA) visited[cur] = 1;
}
// 4) 终点一致性:最后必须到达指定 g_fpga
if (cur != g_fpga) {
std::cout << "[E8] Path does not end at sink for net " << k
<< " sinkIdx " << t << " end=" << cur
<< " expected=" << g_fpga << "\n";
return false;
}
}
}
//cout << "Check whether all nets have routed" << endl;
//cout << "All nets has routed" << endl << endl;
// ---------- (E) 计算得分 ----------
//cout << "Calculate the score of max delay: " << endl;
double score_max_delay = 0.0;
for (int k = 0; k < (int)Input_Netgroup.size(); ++k) {
for (int t = 0; t < (int)Input_Netgroup[k].path_delay.size(); ++t)
score_max_delay = max(score_max_delay, Input_Netgroup[k].path_delay[t]);
}
//cout << "Score of max delay = " << std::fixed << std::setprecision(1)
// << score_max_delay << endl;
//重算版本
// ---------- (E) 计算得分(从零重算 + 仅比较最终结果;使用下标for写法) ----------
//std::cout << "Calculate the score of max delay (from scratch): " << std::endl;
// 3) 按原口径重算所有路径的延迟,并取最大(分母用 weight_matrix,不含 delta)
double recomputed_max_delay = 0.0;
for (int k = 0; k < (int)Input_Netgroup.size(); ++k) {
for (int j = 0; j < (int)Input_Netgroup[k].path.size(); ++j) {
double d = 0.0;
const auto& edges = Input_Netgroup[k].path[j];
for (int m = 0; m < (int)edges.size(); ++m) {
int u = edges[m].first;
int v = edges[m].second;
if (u == v) continue;
// 与 calculate_su 保持一致:30 + 0.7 * ceil8(nets/weight)
d += 30 + 0.7 * ceil8(
(double)nets_count[u][v] / (weight_matrix[u][v] + delta_weight_M[u][v])
);
}
if (d > recomputed_max_delay) {
recomputed_max_delay = d;
}
}
}
//std::cout << "nets_count: " << std::endl;
//for (int i = 1; i <= numFPGA; ++i) {
// for (int j = 1; j <= numFPGA; ++j) {
// std::cout << nets_count[i][j] << ' ';
// }
// std::cout << std::endl;
//}
// 4) 比较最终结果(只比较最大值)
if (recomputed_max_delay != score_max_delay) {
std::cerr << "path_delay计算错误:最大延迟不一致,已有最大延迟="
<< score_max_delay << " 验证计算实际最大延迟=" << recomputed_max_delay << std::endl;
return false;
}
return true;
}
void file_output()//输出design.route.out
{
strcat(outRoute, "design.route.out");
std::ofstream out(outRoute, std::ios::out);
if (!out.is_open())
return;
vector<int> order1(numNet);
iota(order1.begin(), order1.end(), 0);
stable_sort(order1.begin(), order1.end(),
[](int a, int b)
{ return Global_net_delay[a] > Global_net_delay[b]; });
//cout << Global_net_delay[order1[0]] << "j" << endl;
out.setf(std::ios::fixed);
out << std::setprecision(1);
for (int idx : order1)
{
if (Global_net_delay[idx] <= 0.0)
continue;
auto& paths = Global[idx].path;
auto& pdelay = Global[idx].path_delay;
bool printed_header = false;
vector<int> order2(pdelay.size());
iota(order2.begin(), order2.end(), 0);
stable_sort(order2.begin(), order2.end(),
[idx](int a, int b)
{ return Global[idx].path_delay[a] > Global[idx].path_delay[b]; });
for (int j : order2)
{
if (pdelay[j] <= 0.0)
continue;
auto& edges = paths[j];
if (edges.empty())
continue;
if (!printed_header)
{
out << "[net " << (idx + 1) << "]\n";
printed_header = true;
}
out << '[';
out << edges.front().first;
for (int e = 0; e < edges.size(); ++e)
{
out << ',' << edges[e].second;
}
out << "] [" << pdelay[j] << "]\n";
}
}
out.close();
//通道重新组网输出
strcat(outTopo, "design.newtopo");
std::ofstream matrixout(outTopo, std::ios::out);
if (!matrixout.is_open())
return;
for (int x = 1; x <= numFPGA; x++)
{
matrixout << "F" << x << ": ";
for (int y = 1; y < numFPGA; y++)
matrixout << weight_matrix[x][y] + global_delta_weight_matrix[x][y] << ',';
matrixout << weight_matrix[x][numFPGA] + global_delta_weight_matrix[x][numFPGA];
matrixout << "\n";
}
matrixout.close();
}
bool SA_judge(double current_obj, double new_obj)
{
if (new_obj < current_obj)
return true;
else if (new_obj >= current_obj)
{
double prob = exp(-(new_obj - current_obj+0.1) / T);
//cout << "Tem: " << T << ", Prob: " << prob << endl;
//double prob = 1.0 / (1.0 + ((new_obj - current_obj) / T));
double rand_value = rand() / double(RAND_MAX);
if (rand_value <= prob)
return true;
else
return false;
}
return false;
}
vector<vector<double>> current_cost(int** weight_matrix, int** nets_count_matrix) // 当前的成本,也就是选择每条边的成本
{
vector<vector<double>> costn(numFPGA, vector<double>(numFPGA, MAXINT));
for (int i = 0; i < numFPGA; i++) { costn[i][i] = 0; }
for (int i = 1; i <= numFPGA; i++) {//计算下一次使用的成本
for (int j = i; j <= numFPGA; j++) {
if (j == i || weight_matrix[i][j] + delta_weight_matrix[i][j] == 0) { continue; }
int tdm_ratio = ceil8((double)(nets_count_matrix[i][j] + 1) / (weight_matrix[i][j] + delta_weight_matrix[i][j]));
if (tdm_ratio > R_max) continue; // 最大TDM比率约束
costn[i - 1][j - 1] = 30 + 0.7 * ceil8((double)(nets_count_matrix[i][j] + 1) / (weight_matrix[i][j] + delta_weight_matrix[i][j]));
costn[j - 1][i - 1] = costn[i - 1][j - 1];
}
}
return costn;
}
//*****************************************************************************************
// single_dijkstra(求单条路径用)
// 作用:在 net 上求 候选点到终点 的最短路径(用于AF或尾部补全)
// 输入:起点、终点、计算权重依据的跨通道net数量矩阵
// 输出:路径、路径延迟
//*****************************************************************************************
double single_dijkstra(int source_fpga, int sink_fpga, int** net_count_M, double& delay_value)
{
int* best_path = new int[numFPGA]; //新建一条路径,用于存储新找的最优路径
//int source_fpga = nodes_FPGA[source_node];//源点对应的FPGA
//int sink_fpga = nodes_FPGA[sink_node]; //终点对应的FPGA
if (source_fpga == sink_fpga) // 起点终点在相同FPGA里
{
delay_value = 0; //path.clear();
return 0;
}
/*dijkstra*/
double* dist = new double[numFPGA + 1];
bool* visited = new bool[numFPGA + 1];
int* prev = new int[numFPGA + 1];
for (int x = 0; x < numFPGA + 1; x++)
{
if (x == source_fpga)
dist[x] = 0;
else
dist[x] = (double)MAXINT;
visited[x] = false;
prev[x] = -1;
if (x < numFPGA)
best_path[x] = -1;
}
int min_cost_vertic = -1;
for (int iter = 0; iter < numFPGA; iter++)
{
int u = -1;
double min_cost = (double)MAXINT;
for (int x = 1; x <= numFPGA; x++)
{
if (!visited[x] && dist[x] < min_cost)
{
min_cost = dist[x];
u = x;
}
}
if (u == sink_fpga || u == -1)
break;
visited[u] = true;
for (int v = 1; v <= numFPGA; v++)
{
if (weight_matrix[u][v] + delta_weight_matrix[u][v] == 0) continue;
if (visited[v]) continue;
int tmd_ratio = ceil8((double)(net_count_M[u][v] + 1) / (weight_matrix[u][v] + delta_weight_matrix[u][v]));
if (tmd_ratio > R_max) continue; //判断最大TDM比率约束
double delay = 30 + (0.7 * (double)tmd_ratio);
if (dist[v] > dist[u] + delay)
{
dist[v] = dist[u] + delay;
prev[v] = u;
}
}
}