@@ -93,23 +93,27 @@ assign dbuf_rd_ready = ~(|data_left_mask);
9393// : my $t2= "{${kk}{1'b0}}";
9494// : print "$t1"."$t2".";\n";
9595
96+ // layer_end handle
97+ reg dbuf_rd_layer_end_latch;
98+ wire dbuf_rd_layer_end_latch_w = dbuf_rd_layer_end? 1'b1 : ~ (| data_left_mask) ? 1'b0 : dbuf_rd_layer_end_latch;
99+ // : &eperl::flop("-q dbuf_rd_layer_end_latch -d dbuf_rd_layer_end_latch_w -nodeclare");
100+
101+
96102// regout to SDP
97103// : my $kk=CACC_SDP_DATA_WIDTH;
98- // : &eperl::flop("-q dbuf_rd_layer_end_d1 -en \"dbuf_rd_en \" -d \"dbuf_rd_layer_end \" -clk nvdla_core_clk -rst nvdla_core_rstn ");
99104// : &eperl::flop("-q cacc2sdp_valid -d cacc2sdp_valid_w");
100105// : &eperl::flop("-wid ${kk} -q cacc2sdp_pd_data -d cacc2sdp_pd_data_w");
101106wire cacc2sdp_batch_end = 1'b0 ;
102- wire cacc2sdp_layer_end = dbuf_rd_layer_end_d1 ;
107+ wire cacc2sdp_layer_end = dbuf_rd_layer_end_latch && ( ~ ( | data_left_mask)) & cacc2sdp_valid & cacc2sdp_ready; // data_left_mask=0 ;
103108assign cacc2sdp_pd[CACC_SDP_DATA_WIDTH- 1 :0 ] = cacc2sdp_pd_data;
104109assign cacc2sdp_pd[CACC_SDP_WIDTH- 2 ] = cacc2sdp_batch_end;
105- assign cacc2sdp_pd[CACC_SDP_WIDTH- 1 ] = cacc2sdp_layer_end& dbuf_rd_ready ;
110+ assign cacc2sdp_pd[CACC_SDP_WIDTH- 1 ] = cacc2sdp_layer_end;
106111
107112
108113// generate CACC done interrupt
109114wire [1 :0 ] cacc_done_intr_w;
110115reg intr_sel;
111- // assign cacc_done = dbuf_rd_valid & dbuf_rd_ready_d1 & dbuf_rd_layer_end_d1;
112- wire cacc_done = cacc2sdp_valid & cacc2sdp_ready & dbuf_rd_ready& dbuf_rd_layer_end_d1;
116+ wire cacc_done = cacc2sdp_valid & cacc2sdp_ready & cacc2sdp_layer_end;
113117assign cacc_done_intr_w[0 ] = cacc_done & ~ intr_sel;
114118assign cacc_done_intr_w[1 ] = cacc_done & intr_sel;
115119wire intr_sel_w = cacc_done ? ~ intr_sel : intr_sel;
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