DDR3 PHY IP

[ztachip]

I like to port opensource DDR3 controller (from liteDRAM) to 55nm. But it needs the PDK dependent DDR3 PHY IP.
Does icsprout55 PDK provide a DDR3 PHY IP. If so, is it free or licensed?

[myyerrol]

Good! We are discussing with other team to develop DDR3 PHY IP, they plan to open this next year. If everything are ready, we warmly welcome you to port opensource DDR3 controller to 55nm!

[ztachip]

This is great news.
Is the DDR3 IP PHY free or licensed?
Do you also have IP for SRAM block?
We just need basic, few tens of kbytes SRAM block with 1 read port+1 write port.

[myyerrol]

1. The DDR3 PHY IP will be free.
2. Okay, we don't have SRAM blocks at now, but we have contacted thirty-party manufacturer to develop Memory Compiler based on ICsprout55 PDK. According to the latest news, it is expected to be open source by the end of the first quarter of 2026.

[ztachip]

Great.
How about the time line for the release DDR3 PHY IP?
Also my design would require about 60mm2 with 100pins. Is it possible we can do this on MPW run (but with multiple slots if you accept this) or we need to make our own mask.
You have any link about the pricing (MPW and dedicate mask)

[myyerrol]

1. We expect the DDR3 PHY IP to be open-sourced by the end of the half of 2026.
2. Which process you use to get 60mm^2 area? This number looks very large. MPW is the first choice, other ways are pending.
3. The price of ICsprout55 tapeout is RMB 30,000 / mm^2.