Significantly slower run-times after enabling RVFI monitor analysis port

[MikeOpenHWGroup]

After merging #11 we are seeing a 3x slow-down in simulations with DSim. The problem is also certainly related to enabling writes to the analysis port of the RVFI monitor (link).

I suspect a memory leak issue, but it could be a DSim issue.

[Amit-Matth]

Hi @MikeOpenHWGroup ,

I have identified the root cause of the ~3x slowdown observed after enabling the RVFI analysis port.

Root Cause: Redundant Object Allocation

The source of the "memory leak" and slowdown is inside the uvma_rvfi_instr_mon. The monitor was creating new uvma_rvfi_csr_seq_item_c objects for every CSR on every retirement cycle, regardless of whether the CSR was actually accessed or changed.

This impacted DSim performance by:

1. Memory Pressure: Millions of short-lived UVM objects were created per simulation, overwhelming the garbage collector and causing a steady rise in memory usage.
2. CPU Overhead: The time spent in object allocation and initialization dominated the actual simulation progress.

The Fix: Sparse CSR Monitoring

I have implemented Sparse CSR Monitoring. The monitor now only allocates transaction items for CSRs that show activity (non-zero masks or data changes) on the RVFI bus. Additionally, instruction transactions are now only created if the analysis port is actually enabled.

Performance Benchmarks (DSim):

Test Program	Before (Legacy)	After (Optimized)	Speedup
hello-world	1m 26s (86s)	1m 13s (73s)	1.18x
dhrystone	3m 20s (200s)	2m 22s (142s)	1.41x

Note

The speedup becomes more significant as the simulation length increases. For longer regressions, the overhead of the original monitor was the primary driver of the "3x Slowdown" due to memory saturation.

Implementation Strategy:

Because this fix involves a shared UVM agent, I am submitting it across two Pull Requests:

1. PR to core-v-verif: Contains the core optimization in the shared RVFI monitor.
2. PR to cv32e20-dv: Integrates the fix into this environment and adds performance control knobs (like +NO_ISS and +scoreboard_enabled=0).

I will link both PRs here once they are submitted.

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Note: I am still investigating further speedup opportunities. However, given the complexity of the UVM infrastructure and the need to maintain full RVFI compliance, this initial set of changes provides the most significant and safe performance gain while I continue to analyze the deeper architectural interactions.