diff --git a/env/uvme/uvme_cv32e20_cfg.sv b/env/uvme/uvme_cv32e20_cfg.sv
index 1b816a3..77a1e3f 100644
--- a/env/uvme/uvme_cv32e20_cfg.sv
+++ b/env/uvme/uvme_cv32e20_cfg.sv
@@ -321,6 +321,16 @@ function void uvme_cv32e20_cfg_c::pre_randomize();
       max_data_zero_instr_stall = 1;
    end
 
+   // Performance control plusargs
+   if ($test$plusargs("scoreboard_enabled=0")) begin
+      scoreboard_enabled = 0;
+      scoreboard_enabled.rand_mode(0);
+   end
+   if ($test$plusargs("cov_model_enabled=0")) begin
+      cov_model_enabled = 0;
+      cov_model_enabled.rand_mode(0);
+   end
+
 endfunction : pre_randomize
 
 
diff --git a/mk/Common.mk b/mk/Common.mk
index 32f23e1..a06dbd7 100644
--- a/mk/Common.mk
+++ b/mk/Common.mk
@@ -696,13 +696,12 @@ DPI_DASM_INC    = -I$(DPI_DASM_PKG) -I$(DPI_INCLUDE) -I$(DPI_DASM_SPIKE_PKG)/ris
 DPI_DASM_CXX    = g++
 
 dpi_dasm: $(DPI_DASM_SPIKE_PKG)
-	$(CLONE_DPI_DASM_SPIKE_CMD)
 	$(DPI_DASM_CXX) $(DPI_DASM_CFLAGS) $(DPI_DASM_INC) $(DPI_DASM_SRC) -o $(DPI_DASM_LIB)
 
 ###############################################################################
 # Build vendor/riscv-isa-sim into tools/
 
-export SPIKE_PATH  = $(CORE_V_VERIF)/vendor/riscv/riscv-isa-sim
+export SPIKE_PATH  = $(CV_VERIF_PKG)/vendor/riscv/riscv-isa-sim
 export SPIKE_INSTALL_DIR = $(CORE_V_VERIF)/tools/spike/
 SPIKE_LIBS_DIR = $(SPIKE_INSTALL_DIR)/lib/
 SPIKE_FESVR_LIB = $(SPIKE_LIBS_DIR)/libfesvr
@@ -716,8 +715,8 @@ NUM_JOBS ?= 8
 $(SPIKE_FESVR_LIB).so $(SPIKE_RISCV_LIB).so:
 	mkdir -p $(SPIKE_PATH)/build;
 	[ ! -f $(SPIKE_PATH)/build/config.log ] && cd $(SPIKE_PATH)/build && ../configure --prefix=$(SPIKE_INSTALL_DIR) || true
-	make -C $(SPIKE_PATH)/build/ -j $(NUM_JOBS) yaml-cpp-static;
-	make -C $(SPIKE_PATH)/build/ -j $(NUM_JOBS) yaml-cpp;
+	#make -C $(SPIKE_PATH)/build/ -j $(NUM_JOBS) yaml-cpp-static;
+	#make -C $(SPIKE_PATH)/build/ -j $(NUM_JOBS) yaml-cpp;
 	make -C $(SPIKE_PATH)/build/ -j $(NUM_JOBS) install;
 
 spike_lib: $(SPIKE_FESVR_LIB).so $(SPIKE_RISCV_LIB).so
diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk
index 0e1480f..f6198c7 100644
--- a/mk/uvmt/uvmt.mk
+++ b/mk/uvmt/uvmt.mk
@@ -135,6 +135,14 @@ EMB_DEBUG_ARG       = $(if $(filter $(YES_VALS),$(EMB_DEBUG)),YES,NO)
 #DV_UVMT_SRCS                  = $(wildcard $(DV_UVMT_PATH)/*.sv))
 
 # NEW NEW NEW!!!
+# CORE-V-VERIF
+CV_VERIF_PKG        := $(CORE_V_VERIF)/vendor_lib/openhwgroup_core-v-verif
+export CV_VERIF_PKG  = $(CORE_V_VERIF)/vendor_lib/openhwgroup_core-v-verif
+
+# SVLIB
+SVLIB_PKG        := $(CORE_V_VERIF)/vendor_lib/verilab/svlib
+export SVLIB_PKG  = $(CORE_V_VERIF)/vendor_lib/verilab/svlib
+
 export DV_UVMT_PATH             = $(CORE_V_VERIF)/tb/uvmt
 export DV_UVME_PATH             = $(CORE_V_VERIF)/env/uvme
 export DV_UVML_HRTBT_PATH       = $(CV_VERIF_PKG)/lib/uvm_libs/uvml_hrtbt
@@ -215,9 +223,8 @@ export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl
 RTLSRC_HOME   := $(CV_CORE_PKG)/rtl
 RTLSRC_INCDIR := $(RTLSRC_HOME)/include
 
+
 # CORE-V-VERIF
-#CV_VERIF_PKG        := $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/openhwgroup_core-v-verif
-#export CV_VERIF_PKG  = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/openhwgroup_core-v-verif
 CV_VERIF_PKG        := $(CORE_V_VERIF)/vendor_lib/openhwgroup_core-v-verif
 export CV_VERIF_PKG  = $(CORE_V_VERIF)/vendor_lib/openhwgroup_core-v-verif
 
diff --git a/tests/uvmt/firmware-tests/uvmt_cv32e20_general_purpose_test.sv b/tests/uvmt/firmware-tests/uvmt_cv32e20_general_purpose_test.sv
index 76f3c89..b24c975 100644
--- a/tests/uvmt/firmware-tests/uvmt_cv32e20_general_purpose_test.sv
+++ b/tests/uvmt/firmware-tests/uvmt_cv32e20_general_purpose_test.sv
@@ -87,25 +87,25 @@ task uvmt_cv32e20_general_purpose_test_c::run_phase(uvm_phase phase);
 
    // The RVFI Agent needs to be writting to it AP, otherwise the reference
    // model and ISA functional coverage model have nothing to proces.
-   env.rvfi_agent.instr_monitor.cfg.ap_write_en = 1;
-   `uvm_info("TEST", "Writing to RVFI Agent's instruction monitor Analysis Port enabled", UVM_NONE)
+   env.rvfi_agent.instr_monitor.cfg.ap_write_en = env.cfg.cov_model_enabled || env.cfg.scoreboard_enabled;
+   `uvm_info("TEST", $sformatf("Writing to RVFI Agent's instruction monitor Analysis Port enabled: %0b", env.rvfi_agent.instr_monitor.cfg.ap_write_en), UVM_NONE)
 
    if ($test$plusargs("gen_random_debug")) begin
-    fork
-      random_debug();
-    join_none
+      fork
+         random_debug();
+      join_none
    end
 
    if ($test$plusargs("gen_irq_noise")) begin
-    fork
-      irq_noise();
-    join_none
+      fork
+         irq_noise();
+      join_none
    end
 
    if ($test$plusargs("random_fetch_toggle")) begin
-     fork
-       random_fetch_toggle();
-     join_none
+      fork
+         random_fetch_toggle();
+      join_none
    end
 
    if ($test$plusargs("reset_debug")) begin
@@ -158,8 +158,13 @@ endtask
 function void uvmt_cv32e20_general_purpose_test_c::build_phase(uvm_phase phase);
        super.build_phase(phase);
 
-       `uvm_info("TEST", "Overriding Reference Model with Spike", UVM_NONE)
-       set_type_override_by_type(uvmc_rvfi_reference_model#()::get_type(),uvmc_rvfi_spike#()::get_type());
+       if (!$test$plusargs("NO_ISS")) begin
+          `uvm_info("TEST", "Overriding Reference Model with Spike", UVM_NONE)
+          set_type_override_by_type(uvmc_rvfi_reference_model#()::get_type(),uvmc_rvfi_spike#()::get_type());
+       end
+       else begin
+          `uvm_info("TEST", "Skipping Reference Model override (NO_ISS set)", UVM_NONE)
+       end
 
 endfunction : build_phase