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4 changes: 4 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
[submodule "external/act4"]
path = external/act4
url = https://github.com/riscv-non-isa/riscv-arch-test.git
branch = act4
1 change: 1 addition & 0 deletions bsp/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ SRC = crt0.S handlers.S syscalls.c vectors.S
OBJ = crt0.o handlers.o syscalls.o vectors.o
LIBCV-VERIF = libcv-verif.a
CFLAGS ?= -Os -g -static -mabi=ilp32 -march=$(CV_SW_MARCH) -Wall -pedantic
CV_SW_MARCH ?= rv32imc_zicsr_zifencei #TODO(Ateeb): Temporary, remove after debug

all: $(LIBCV-VERIF)

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3 changes: 2 additions & 1 deletion bsp/link.ld
Original file line number Diff line number Diff line change
Expand Up @@ -47,13 +47,14 @@ SECTIONS
} >dbg

/* CORE-V: we want a fixed entry point */
PROVIDE(__boot_address = 0x000);
PROVIDE(__boot_address = 0x100);
PROVIDE(_debugger_exception_start = 0x1A140000);


/* CORE-V: crt0 init code */
.init (ORIGIN(ram)):
{
. = 0x100;
KEEP (*(SORT_NONE(.init)))
KEEP (*(.text.start))
} >ram
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1 change: 1 addition & 0 deletions external/act4
Submodule act4 added at 6e4bfb
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