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DEM-UART: Initial implementation for FIFOs
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‎modules/dem_uart/common/fifo_singleclock_fwft.sv‎

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/* Copyright (c) 2017 by the author(s)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* =============================================================================
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*
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* Synchronous First-Word Fall-Through (FWFT) FIFO
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*
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* This FIFO implementation wraps the FIFO with standard read characteristics
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* to have first-word fall-through read characteristics.
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*
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* Author(s):
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* Philipp Wagner <[email protected]>
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*/
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module fifo_singleclock_fwft #(
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parameter WIDTH = 8,
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parameter DEPTH = 32,
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parameter PROG_FULL = (DEPTH / 2)
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)(
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input clk,
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input rst,
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input [(WIDTH-1):0] din,
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input wr_en,
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output full,
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output prog_full,
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output reg [(WIDTH-1):0] dout,
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input rd_en,
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output empty,
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output [$clog2(DEPTH)-1:0] count
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);
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reg fifo_valid, middle_valid, dout_valid;
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reg [(WIDTH-1):0] middle_dout;
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wire [(WIDTH-1):0] fifo_dout;
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wire fifo_empty, fifo_rd_en;
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wire will_update_middle, will_update_dout;
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// synchronous FIFO with standard (non-FWFT) read characteristics
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fifo_singleclock_standard
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#(.WIDTH(WIDTH),
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.DEPTH(DEPTH),
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.PROG_FULL(PROG_FULL))
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u_fifo (
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.rst(rst),
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.clk(clk),
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.rd_en(fifo_rd_en),
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.dout(fifo_dout),
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.empty(fifo_empty),
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.wr_en(wr_en),
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.din(din),
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.full(full),
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.prog_full(prog_full),
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.count(count)
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);
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// create FWFT FIFO out of non-FWFT FIFO
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// public domain code from Eli Billauer
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// see http://www.billauer.co.il/reg_fifo.html
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assign will_update_middle = fifo_valid && (middle_valid == will_update_dout);
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assign will_update_dout = (middle_valid || fifo_valid) && (rd_en || !dout_valid);
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assign fifo_rd_en = (!fifo_empty) && !(middle_valid && dout_valid && fifo_valid);
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assign empty = !dout_valid;
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always_ff @(posedge clk) begin
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if (rst) begin
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fifo_valid <= 0;
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middle_valid <= 0;
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dout_valid <= 0;
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dout <= 0;
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middle_dout <= 0;
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end else begin
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if (will_update_middle)
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middle_dout <= fifo_dout;
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if (will_update_dout)
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dout <= middle_valid ? middle_dout : fifo_dout;
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if (fifo_rd_en)
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fifo_valid <= 1;
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else if (will_update_middle || will_update_dout)
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fifo_valid <= 0;
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if (will_update_middle)
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middle_valid <= 1;
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else if (will_update_dout)
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middle_valid <= 0;
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if (will_update_dout)
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dout_valid <= 1;
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else if (rd_en)
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dout_valid <= 0;
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end
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end
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endmodule

‎modules/dem_uart/common/fifo_singleclock_standard.sv‎

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/* Copyright (c) 2017 by the author(s)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* =============================================================================
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*
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* Synchronous Standard FIFO (one clock)
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*
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* The memory block in this FIFO is following the "RAM HDL Coding Guidelines"
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* of Xilinx (UG901) to enable placing the FIFO memory into block ram during
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* synthesis.
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*
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* Author(s):
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* Philipp Wagner <[email protected]>
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*/
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module fifo_singleclock_standard #(
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parameter WIDTH = 8,
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parameter DEPTH = 32,
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parameter PROG_FULL = DEPTH / 2
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)(
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input clk,
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input rst,
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input [(WIDTH-1):0] din,
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input wr_en,
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output full,
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output prog_full,
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output reg [(WIDTH-1):0] dout,
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input rd_en,
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output empty,
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output [$clog2(DEPTH) - 1:0] count
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);
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localparam AW = $clog2(DEPTH);
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// ensure that parameters are set to allowed values
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initial begin
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if ((1 << $clog2(DEPTH)) != DEPTH) begin
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$fatal("fifo_singleclock_standard: the DEPTH must be a power of two.");
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end
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end
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reg [AW-1:0] wr_addr;
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reg [AW-1:0] rd_addr;
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wire fifo_read;
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wire fifo_write;
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reg [AW-1:0] rd_count;
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// generate control signals
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assign empty = (rd_count[AW-1:0] == 0);
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assign prog_full = (rd_count[AW-1:0] >= PROG_FULL);
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assign full = (rd_count[AW-1:0] == (DEPTH-1));
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assign fifo_read = rd_en & ~empty;
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assign fifo_write = wr_en & ~full;
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assign count = rd_count;
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// address logic
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always_ff @(posedge clk) begin
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if (rst) begin
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wr_addr[AW-1:0] <= 'd0;
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rd_addr[AW-1:0] <= 'b0;
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rd_count[AW-1:0] <= 'b0;
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end else begin
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if (fifo_write & fifo_read) begin
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wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
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rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
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end else if (fifo_write) begin
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wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
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rd_count[AW-1:0]<= rd_count[AW-1:0] + 'd1;
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end else if (fifo_read) begin
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rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
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rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1;
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end
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end
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end
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// generic dual-port, single clock memory
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reg [WIDTH-1:0] ram [DEPTH-1:0];
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// write
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always_ff @(posedge clk) begin
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if (fifo_write) begin
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ram[wr_addr] <= din;
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end
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end
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// read
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always_ff @(posedge clk) begin
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if (fifo_read) begin
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dout <= ram[rd_addr];
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end
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end
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endmodule

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