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@EE156 Board Level Design

@finnhittson
finn finnhittson
@rohan-karunaratne
Rohan Karunaratne rohan-karunaratne
Stanford Engineering; FPGAs, Verilog, Python ML (SK-Learn, TensorFlow)
@ashkumr
ashkumr
@annwuhoo
Ann Wu annwuhoo

Palo Alto, CA

@maryannbferns
maryannbferns
@EvelynANutt
EvelynANutt
@lyujunrui
Junrui Lyu lyujunrui
BS in EE@UESTC MS in EE@Stanford PhD in EE@Stanford (Ongoing)