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Allow 12 bit ADC values (feature request) #28
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Hello and Merry Christmas,
The reason i was asking was because i created a circuit with 2 inverting OpAmps to map an input from -15V to +15V to an output of 0 to 3.3V for the ADC. |
Using DMA transfers for 12bit reads should work just fine as long as the DMA fifo is configured to not discard 4 bits. You found the official documentation, but the unofficial reason for not supporting more resolution was that I ran out of time trying to get everything else working and figured I'd wait to see if anyone cared about higher resolution. It is also looking like I might get this repo merged to mainline sigrok repo so that will take priority, but I'll keep this open and think about supporting higher resolution. Merry Christmas. |
Thank you very much for clarifying that. |
ok. With my first commit getting accepted around a year ago I can't use that as an excuse anymore ;). |
So the current relased code of sigrok does support the parsing of multi-bytes per sample analog encodings. |
Hello,
this is more of a feature request than an issue.
First of all, i really love that project and was going a little through the code.
I would really love to have access to the full 12 bit ADC values.
As far as limitations go i think it shouldn't impact the sampling or transfer rates a lot.
I know it would require to change the driver and obviously the firmware.
I am not yet confident enough to do the PIO and DMA stuff for myself, but I would be willing to learn it.
Well, my actual questions are, can it be done? do i have to do it myself? and is there something i am not seeing and i would run straight into a wall?
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