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Commit 3434731

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cothancothan
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Signed-off-by: Duc Tri Nguyen <[email protected]>
1 parent c3fe366 commit 3434731

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2 files changed

+87
-89
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2 files changed

+87
-89
lines changed

‎hal/hal-opencm3.c

+87-88
Original file line numberDiff line numberDiff line change
@@ -70,14 +70,13 @@ const struct rcc_clock_scale benchmarkclock = {
7070

7171
/* Patched function for newer PLL not yet supported by opencm3 */
7272
void _rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp,
73-
uint32_t pllq, uint32_t pllr)
74-
{
75-
RCC_PLLCFGR = (RCC_PLLCFGR_PLLM(pllm) << RCC_PLLCFGR_PLLM_SHIFT) |
76-
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
77-
((pllp & 0x1Fu) << 27u) | /* NEWER PLLP */
78-
(source << RCC_PLLCFGR_PLLSRC_SHIFT) |
79-
(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
80-
(pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN;
73+
uint32_t pllq, uint32_t pllr) {
74+
RCC_PLLCFGR = (RCC_PLLCFGR_PLLM(pllm) << RCC_PLLCFGR_PLLM_SHIFT) |
75+
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
76+
((pllp & 0x1Fu) << 27u) | /* NEWER PLLP */
77+
(source << RCC_PLLCFGR_PLLSRC_SHIFT) |
78+
(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
79+
(pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN;
8180
}
8281

8382
#else
@@ -181,69 +180,69 @@ static void clock_setup(enum clock_mode clock) {
181180
# else
182181
# error Unsupported STM32F2 Board
183182
# endif
184-
#elif defined(NUCLEO_L4R5_BOARD)
185-
rcc_periph_clock_enable(RCC_PWR);
186-
rcc_periph_clock_enable(RCC_SYSCFG);
187-
pwr_set_vos_scale(PWR_SCALE1);
188-
/* The L4R5ZI chip also needs the R1MODE bit in PWR_CR5 register set, but
189-
OpenCM3 doesn't support this yet. But luckily the default value for the bit
190-
is 1. */
191-
switch (clock) {
192-
case CLOCK_BENCHMARK:
193-
/* Benchmark straight from the HSI16 without prescaling */
194-
rcc_osc_on(RCC_HSI16);
195-
rcc_wait_for_osc_ready(RCC_HSI16);
196-
rcc_ahb_frequency = 20000000;
197-
rcc_apb1_frequency = 20000000;
198-
rcc_apb2_frequency = 20000000;
199-
_clock_freq = 20000000;
200-
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
201-
rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
202-
rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
203-
rcc_osc_off(RCC_PLL);
204-
while(rcc_is_osc_ready(RCC_PLL));
205-
/* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 20MHz). */
206-
_rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 10, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV8);
207-
/* Enable PLL oscillator and wait for it to stabilize. */
208-
rcc_osc_on(RCC_PLL);
209-
flash_dcache_enable();
210-
flash_icache_enable();
211-
flash_set_ws(FLASH_ACR_LATENCY_0WS);
212-
flash_prefetch_enable();
213-
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
214-
rcc_wait_for_sysclk_status(RCC_PLL);
215-
break;
216-
case CLOCK_FAST:
217-
default:
218-
rcc_osc_on(RCC_HSI16);
219-
rcc_wait_for_osc_ready(RCC_HSI16);
220-
rcc_ahb_frequency = 120000000;
221-
rcc_apb1_frequency = 120000000;
222-
rcc_apb2_frequency = 120000000;
223-
_clock_freq = 120000000;
224-
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
225-
rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
226-
rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
227-
rcc_osc_off(RCC_PLL);
228-
while(rcc_is_osc_ready(RCC_PLL));
229-
/* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 120MHz). */
230-
_rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 15, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV2);
231-
/* Enable PLL oscillator and wait for it to stabilize. */
232-
rcc_osc_on(RCC_PLL);
233-
rcc_wait_for_osc_ready(RCC_PLL);
234-
flash_dcache_enable();
235-
flash_icache_enable();
236-
flash_set_ws(0x05);
237-
flash_prefetch_enable();
238-
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
239-
rcc_wait_for_sysclk_status(RCC_PLL);
240-
break;
241-
}
242-
rcc_osc_on(RCC_HSI48); /* HSI48 must always be on for RNG */
243-
rcc_wait_for_osc_ready(RCC_HSI48);
244-
rcc_periph_clock_enable(RCC_RNG);
245-
rcc_set_clock48_source(RCC_CCIPR_CLK48SEL_HSI48);
246-
rng_enable();
183+
#elif defined(NUCLEO_L4R5_BOARD)
184+
rcc_periph_clock_enable(RCC_PWR);
185+
rcc_periph_clock_enable(RCC_SYSCFG);
186+
pwr_set_vos_scale(PWR_SCALE1);
187+
/* The L4R5ZI chip also needs the R1MODE bit in PWR_CR5 register set, but
188+
OpenCM3 doesn't support this yet. But luckily the default value for the bit
189+
is 1. */
190+
switch (clock) {
191+
case CLOCK_BENCHMARK:
192+
/* Benchmark straight from the HSI16 without prescaling */
193+
rcc_osc_on(RCC_HSI16);
194+
rcc_wait_for_osc_ready(RCC_HSI16);
195+
rcc_ahb_frequency = 20000000;
196+
rcc_apb1_frequency = 20000000;
197+
rcc_apb2_frequency = 20000000;
198+
_clock_freq = 20000000;
199+
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
200+
rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
201+
rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
202+
rcc_osc_off(RCC_PLL);
203+
while (rcc_is_osc_ready(RCC_PLL));
204+
/* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 20MHz). */
205+
_rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 10, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV8);
206+
/* Enable PLL oscillator and wait for it to stabilize. */
207+
rcc_osc_on(RCC_PLL);
208+
flash_dcache_enable();
209+
flash_icache_enable();
210+
flash_set_ws(FLASH_ACR_LATENCY_0WS);
211+
flash_prefetch_enable();
212+
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
213+
rcc_wait_for_sysclk_status(RCC_PLL);
214+
break;
215+
case CLOCK_FAST:
216+
default:
217+
rcc_osc_on(RCC_HSI16);
218+
rcc_wait_for_osc_ready(RCC_HSI16);
219+
rcc_ahb_frequency = 120000000;
220+
rcc_apb1_frequency = 120000000;
221+
rcc_apb2_frequency = 120000000;
222+
_clock_freq = 120000000;
223+
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
224+
rcc_set_ppre1(RCC_CFGR_PPRE_NODIV);
225+
rcc_set_ppre2(RCC_CFGR_PPRE_NODIV);
226+
rcc_osc_off(RCC_PLL);
227+
while (rcc_is_osc_ready(RCC_PLL));
228+
/* Configure the PLL oscillator (use CUBEMX tool -> scale HSI16 to 120MHz). */
229+
_rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_HSI16, 1, 15, 2, RCC_PLLCFGR_PLLQ_DIV2, RCC_PLLCFGR_PLLR_DIV2);
230+
/* Enable PLL oscillator and wait for it to stabilize. */
231+
rcc_osc_on(RCC_PLL);
232+
rcc_wait_for_osc_ready(RCC_PLL);
233+
flash_dcache_enable();
234+
flash_icache_enable();
235+
flash_set_ws(0x05);
236+
flash_prefetch_enable();
237+
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
238+
rcc_wait_for_sysclk_status(RCC_PLL);
239+
break;
240+
}
241+
rcc_osc_on(RCC_HSI48); /* HSI48 must always be on for RNG */
242+
rcc_wait_for_osc_ready(RCC_HSI48);
243+
rcc_periph_clock_enable(RCC_RNG);
244+
rcc_set_clock48_source(RCC_CCIPR_CLK48SEL_HSI48);
245+
rng_enable();
247246
#else
248247
#error Unsupported platform
249248
#endif
@@ -259,23 +258,23 @@ void usart_setup() {
259258
#elif defined(NUCLEO_BOARD)
260259
rcc_periph_clock_enable(RCC_GPIOA);
261260
rcc_periph_clock_enable(RCC_USART2);
262-
#elif defined(NUCLEO_L4R5_BOARD)
263-
rcc_periph_clock_enable(RCC_GPIOG);
264-
rcc_periph_clock_enable(RCC_LPUART1);
265-
266-
PWR_CR2 |= PWR_CR2_IOSV;
267-
gpio_set_output_options(SERIAL_GPIO, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, SERIAL_PINS);
268-
gpio_set_af(SERIAL_GPIO, GPIO_AF8, SERIAL_PINS);
269-
gpio_mode_setup(SERIAL_GPIO, GPIO_MODE_AF, GPIO_PUPD_NONE, SERIAL_PINS);
270-
usart_set_baudrate(SERIAL_USART, SERIAL_BAUD);
271-
usart_set_databits(SERIAL_USART, 8);
272-
usart_set_stopbits(SERIAL_USART, USART_STOPBITS_1);
273-
usart_set_mode(SERIAL_USART, USART_MODE_TX_RX);
274-
usart_set_parity(SERIAL_USART, USART_PARITY_NONE);
275-
usart_set_flow_control(SERIAL_USART, USART_FLOWCONTROL_NONE);
276-
usart_disable_rx_interrupt(SERIAL_USART);
277-
usart_disable_tx_interrupt(SERIAL_USART);
278-
usart_enable(SERIAL_USART);
261+
#elif defined(NUCLEO_L4R5_BOARD)
262+
rcc_periph_clock_enable(RCC_GPIOG);
263+
rcc_periph_clock_enable(RCC_LPUART1);
264+
265+
PWR_CR2 |= PWR_CR2_IOSV;
266+
gpio_set_output_options(SERIAL_GPIO, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, SERIAL_PINS);
267+
gpio_set_af(SERIAL_GPIO, GPIO_AF8, SERIAL_PINS);
268+
gpio_mode_setup(SERIAL_GPIO, GPIO_MODE_AF, GPIO_PUPD_NONE, SERIAL_PINS);
269+
usart_set_baudrate(SERIAL_USART, SERIAL_BAUD);
270+
usart_set_databits(SERIAL_USART, 8);
271+
usart_set_stopbits(SERIAL_USART, USART_STOPBITS_1);
272+
usart_set_mode(SERIAL_USART, USART_MODE_TX_RX);
273+
usart_set_parity(SERIAL_USART, USART_PARITY_NONE);
274+
usart_set_flow_control(SERIAL_USART, USART_FLOWCONTROL_NONE);
275+
usart_disable_rx_interrupt(SERIAL_USART);
276+
usart_disable_tx_interrupt(SERIAL_USART);
277+
usart_enable(SERIAL_USART);
279278
#else
280279
#error Unsupported platform
281280
#endif

‎scripts/tests

-1
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,6 @@ platform_map = RecursiveNamespace(
157157
f"{PLATFORM.NUCLEO_L4R5ZI}": {
158158
"openocd_cfg": f"{ROOT}/hal/nucleo_l4r5.cfg",
159159
},
160-
161160
}
162161
)
163162

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