[RV64_DYNAREC] Optimize some opcodes by removing redundant some vsetvli (#4588)

When VLMUL, TU, and MU remain unchanged:

For `vmv.s.x`, if SEW stays unchanged, the vector configuration does not need
to change.

For `vmv.v.v`, if the width stays unchanged, the vector configuration does not
need to change.

Author: zengdage

src/dynarec/rv64/dynarec_rv64_avx_0f_vector.c

@@ -88,9 +88,8 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
                 INST_NAME("VMOVLPS Gx, Vx, Ex");
                 SMREAD();
                 addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 1, 0);
-                if (fixedaddress) { ADDI(x4, ed, fixedaddress); ed = x4; fixedaddress = 0; }
-                vector_vsetvli(dyn, ninst, x1, VECTOR_SEW64, VECTOR_LMUL1, 0.5);
-                VLE64_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1);
+                LD(x4, ed, fixedaddress);
+                VMV_S_X(q1, x4);
             }
             GETGY_empty_vector(v0);
             q2 = fpu_get_scratch(dyn);
@@ -158,9 +157,8 @@ uintptr_t dynarec64_AVX_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t
                 INST_NAME("VMOVHPS Gx, Vx, Ex");
                 SMREAD();
                 addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 1, 0);
-                if (fixedaddress) { ADDI(x4, ed, fixedaddress); ed = x4; fixedaddress = 0; }
-                vector_vsetvli(dyn, ninst, x1, VECTOR_SEW64, VECTOR_LMUL1, 0.5);
-                VLE64_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1);
+                LD(x4, ed, fixedaddress);
+                VMV_S_X(q1, x4);
             }
             GETGY_empty_vector(v0);
             avx_set_vector_width(dyn, ninst, x1, VECTOR_SEW64, 16);

src/dynarec/rv64/dynarec_rv64_avx_66_0f38_vector.c

@@ -1780,7 +1780,6 @@ uintptr_t dynarec64_AVX_66_0F38_vector(dynarec_rv64_t* dyn, uintptr_t addr, uint
             OR(x4, x4, x5);
             vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 1);
             VXOR_VV(v0, v0, v0, VECTOR_UNMASKED);
-            vector_vsetvli(dyn, ninst, x1, VECTOR_SEW32, VECTOR_LMUL1, 0.25f);
             VMV_S_X(v0, x4);
             avx_store_reg_vector(dyn, ninst, x1, v0, gd, 16, VECTOR_SEW32);
             break;

src/dynarec/rv64/dynarec_rv64_avx_66_0f3a_vector.c

@@ -118,9 +118,7 @@ uintptr_t dynarec64_AVX_66_0F3A_vector(dynarec_rv64_t* dyn, uintptr_t addr, uint
             VEC_SRC_KEEP(q0, v0);
             q1 = fpu_get_scratch(dyn);
             MOV64x(x4, (uint64_t)(u8 & 1) | ((uint64_t)((u8 >> 1) & 1) << 16) | ((uint64_t)(((u8 >> 2) & 1) + 2) << 32) | ((uint64_t)(((u8 >> 3) & 1) + 2) << 48));
-            vector_vsetvli(dyn, ninst, x1, VECTOR_SEW64, VECTOR_LMUL1, 1);
             VMV_S_X(q1, x4);
-            avx_set_vector_width(dyn, ninst, x1, VECTOR_SEW64, 16 << vex.l);
             VRGATHEREI16_VV(v0, q0, q1, VECTOR_UNMASKED);
             PUTGY_vector(v0, VECTOR_SEW64);
             break;

src/dynarec/rv64/dynarec_rv64_avx_66_0f_vector.c

@@ -132,9 +132,8 @@ uintptr_t dynarec64_AVX_66_0F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintpt
             } else {
                 SMREAD();
                 addr = geted(dyn, addr, ninst, nextop, &ed, x2, x3, &fixedaddress, rex, NULL, 1, 0);
-                if (fixedaddress) { ADDI(x4, ed, fixedaddress); ed = x4; fixedaddress = 0; }
-                vector_vsetvli(dyn, ninst, x1, VECTOR_SEW64, VECTOR_LMUL1, 0.5);
-                VLE64_V(q1, ed, VECTOR_UNMASKED, VECTOR_NFIELD1);
+                LD(x4, ed, fixedaddress);
+                VMV_S_X(q1, x4);
             }
             GETGY_empty_vector(v0);
             avx_set_vector_width(dyn, ninst, x1, VECTOR_SEW64, 16);

src/dynarec/rv64/dynarec_rv64_helper.c

@@ -3055,7 +3055,7 @@ void avx_store_reg_vector(dynarec_rv64_t* dyn, int ninst, int s1, int vreg, int
         dyn->insts[ninst].vec_write_full |= 1u << a;
     int cache = sse_get_reg_empty_vector(dyn, ninst, s1, a);
     if (cache != vreg) {
-        avx_set_vector_width(dyn, ninst, s1, VECTOR_SEW8, width);
+        avx_set_vector_width(dyn, ninst, s1, sew, width);
         VMV_V_V(cache, vreg);
     }
     if (cpuext.vlen >= 32) {