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<!DOCTYPE html>
<!-- saved from url=(0045)http://3dvision.princeton.edu/people/shurans/ ; partially based on Linnan Wang's blog-->
<html class="gr__3dvision_princeton_edu"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<title>Biwei Xie</title>
<link rel="stylesheet" type="text/css" href="pvg.css">
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<body data-gr-c-s-loaded="true">
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<h1> Biwei Xie (解壁伟)</h1>
<p>
office at 1011F,<br>
NO. 6, Kexueyuan South Road, Zhongguancun, <br>
Haidian district, Beijing, P.R.China 100190 <br>
Email: xiebiwei(at)ict(dot)ac(dot)cn
</p>
<p>
<a href="https://scholar.google.com/citations?user=KSIiidMAAAAJ&hl=en">
<b> Google Scholar </b>
</a>
|
<a href="https://github.com/puckbee">
<b> GitHub </b>
</a>
|
<a href="cv.pdf">
<b> Curriculum Vitae </b>
</a>
</p>
</td>
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</tbody>
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<h2>My Mission:</h2>
<p>
My Mission is to bridge the gap between hardware and software, which means, to help the workloads understand the underlying hardware better and vice versa.
I do research on the characteristics of workloads(ML algorithms, HPC applications, CNN, graph and etc.) and the advanced features of emerging/existing hardware(Xeon Phi, high-end GPU, ARM-neon, and etc), and try my best to squeeze the last ounce of performance.
<br><br>
I'm an assistant professor working with <a href="http://acs.ict.ac.cn/baoyg/"><b>Prof. Yungang Bao</b></a> in the <a href="http://acs.ict.ac.cn"><u>Center for Advanced Computer Systems (ACS)</u></a> at Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
I received my Ph.D degree in 2018 at ICT, supervised by <a href="http://www.cs.utah.edu/~lizhang/"><b>Prof. Lixin Zhang</b></a> and <a href="http://prof.ict.ac.cn/jfzhan/"><b>Prof. Jianfeng Zhan</b></a>, and my master degree at Beijing University of Technology in 2012, supervised by <a href="https://www.linkedin.com/in/jingsha-he-2a073182/"><b>Prof. Jingsha He</b></a>.
I acquired my bachelor degree at Hebei University of Science and Technology in 2009.
In addition to my advisor, I also work closely with <a href="http://www.cs.wm.edu/~xl10/"><b>Prof. Xu Liu</b></a>, <a href="https://scholar.google.com/citations?user=aMUhz_oAAAAJ"><b>Prof. Sally A.McKee</b></a>, and <a href="http://www.cs.princeton.edu/~zhenj/"><b>Dr. Zhen Jia</b></a><br><br>
In the following several years, I will focus on studying computer architecuture and chip design.
I'm fresh to computer architecuture, but always keep moving with great enthusiasm.
I believe that my background, which is also my advantage, on workloads characterization and performance optimizatin will provide me novel perspectives in computer architecture design.
<br><br>
My research interests include: benchmarking, workload characterization, performance optimization, operating system, and computer architecture design.
</p>
<h2>Projects:</h2>
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<b>PhiBench</b> <br>
(2014~2016)
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<tr> Understanding the workloads on x86 based many-core processors.
<tr><td style="width: 100%; text-align: left;">
My Mission is to bridge the gap between hardware and software, which means, to help the workloads understand the underlying hardware, and help the hardware to know what the workloads needs.<br><br>
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<b> HPConv: high performance winograd-based convolution (2017 ~ Now) </b>
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This project aims at a high performance implementation of winograd-based convolution, considering sparse, cross-layer data fusion, and strassen based matrix multiplication(MM).
HPConv is preliminary designed for inference-convolution and will be extended to traing-convolution in the future.
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<b>SparseLib: high performance library for sparse problems (2017 ~ Now) </b>
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Numerous applications rely on sparse linear algebra methods or can be cast as sparse problems.
SparseLib focuses on exploiting architectural advances on emerging hardware (wider SIMD lane on Xeon Phi; more processing unit on GPU;...) for various sparse related basic operations, like SpMV, SpMM, sparseFFT, and etc.
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<b>PhiBench: Understanding the data analytics workloads on x86 based many-core processors (2014 ~ 2016) </b>
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The first release of PhiBench consists of eight data analytics workloads, which are delicately optimized on Intel Xeon Phi, an x86 based many-core processor.
We hope that PhiBench is useful for researchers that are interested in understanding data analytics workloads on Intel Xeon Phi.
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<b>mobile-Tracking: optimizing body-tracking algorithms on mobile platform (2014 ~ 2015)</b>
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In this project, we optimize a HOG+FFT based tracking algorithm on NVIDIA TK1. The raw code is written in C/Matlab. We need to investigate the hotspot and accelerate it through parallelization and vectorization.
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<b>xMem: Enlarging the memory on co-processors with host memory (2013 ~ 2015)</b>
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Memory capacity on many co-processors is limited, and unlike host memory, it's hard to increase. In this project, rarely used data on co-processors will be swapped to host memory. Different from classical swap mechanism, swap partition in this project is writable, and can be used for communication between host and co-processors.
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<b>pQEMU: Parallel version of QEMU (2012 ~ 2013)</b>
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QEMU is serial, even when it emulates multiple processors and runs on a multi-core processor. pQEMU aims at accelerating QEMU through multi-threading.
</td>
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<h2>in Preparation:</h2>
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<p>
<b>Biwei Xie</b>, Zhen Jia, Wanling Gao, Jianfeng Zhan, and Yungang Bao <br>
<b>The Impact of Data Pattern on SpMV performance</b> <br>
<br>
</p>
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</td>
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<td><img src="7.png" height = "270" width = "400" ></td>
<td>
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<p>
Xinhui Tian, <b>Biwei Xie</b>, and Jianfeng Zhan <br>
<b>Cymbalo: An Efficient Graph ProcessingFramework for Machine Learning</b> <br>
<br>
</p>
</td><td style="width: 10px;">
</td>
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<h2>Publications:</h2>
<b>2018</b>
<table id="pubList" border="0" cellpadding="0" width="100%" style="border-spacing: 0 6px; line-height:14pt;">
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<td><img src="6.png" height = "270" width = "400"></td>
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<table style="width: 100%;"><tbody><tr><td style="width: 100%; text-align: left;">
<p>
Wanling Gao, Jianfeng Zhan, Lei Wang, Chunjie Luo, Daoyi Zheng, Fei Tang, <b>Biwei Xie</b>, Chen Zheng, Xu Wen, Xiwen He, Hainan Ye, and Rui Ren<br>
<b>Data Motifs: A Lens Towards Fully Understanding Big Data and AI Workloads</b><br>
In Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques(<b>PACT2018</b>)<br>
</p>
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<p>
Changxi Liu, <b>Biwei Xie</b>, Xin Liu, Wei Xue, Hailong Yang, and Xu Liu <br>
<a href="http://ics2018.ict.ac.cn/essay/ics18-final141.pdf"> <b> Towards efficient SpMV on sunway many-core architectures</b> </a> <br>
In Proceedings of the 2018 International Conference on Supercomputing (<b>ICS2018</b>)<br>
<a href="http://ics2018.ict.ac.cn/essay/ics18-final141.pdf">Paper</a> ·
<a href="sunway_ICS18.pptx">slides</a>
</p>
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</td>
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</tbody></table>
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<td><img src="3.png" height = "270" width = "400"></td>
<td>
<table style="width: 100%;"><tbody><tr><td style="width: 100%; text-align: left;">
<b>Biwei Xie</b>, Jianfeng Zhan, Xu Liu, Wanling Gao, Zhen Jia, Xiwen He, and Lixin Zhang <br>
<a href="https://dl.acm.org/citation.cfm?id=3168818"> <b>CVR: efficient vectorization of SpMV on x86 processors</b></a><br>
In Proceedings of the 2018 International Symposium on Code Generation and Optimization (<b>CGO2018</b>)<br>
<a href="https://dl.acm.org/citation.cfm?id=3168818">Paper</a> ·
<a href="CVR_CGO18.pptx">slides</a> ·
<a href="https://github.com/puckbee/CVR">Code</a>
</p>
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<b>2016</b>
<table id="pubList" border="0" cellpadding="0" width="100%" style="border-spacing: 0 6px; line-height:14pt;">
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<tr style="border-width: 1px">
<td><img src="2.png" height = "270" width = "400"></td>
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<table style="width: 100%;"><tbody><tr><td style="width: 100%; text-align: left;">
<p> <b>Biwei Xie</b>, Xu Liu, Sally A McKee, Jianfeng Zhan, Zhen Jia, Lei Wang, and Lixin Zhang<br>
<a href="https://ieeexplore.ieee.org/document/7828380">
<b>Understanding Data Analytics Workloads on Intel Xeon Phi</b></a><br>
In Proceedings of the 18th International Conference on High-Performance Computing and Communications(<b>HPCC2016</b>)<br>
<a href="https://ieeexplore.ieee.org/document/7828380/">Paper</a> ·
<a href="https://github.com/puckbee/PhiBench">Code</a>
</p>
</td><td style="width: 10px;">
</td>
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<b>2015</b>
<table id="pubList" border="0" cellpadding="0" width="100%" style="border-spacing: 0 6px; line-height:14pt;">
<tbody>
<tr style="border-width: 1px">
<td><img src="1.png" height = "270" width = "400"></td>
<td>
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<p><b>Biwei Xie</b>, Xu Liu, Jianfeng Zhan, Zhen Jia, Yuqing Zhu, Lei Wang, and Lixin Zhang <br>
<b>Characterizing Data Analytics Workloads on Intel Xeon Phi</b><br>
In Proceedings of the 2015 IEEE International Symposium on Workload Characterization, short paper (<b>IISWC2015</b>)<br>
</p>
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<h2>Patents:</h2>
<ul>
<li><a href="https://patents.google.com/patent/EP3104275A4/en"> EP3104275A4</a>, Data processing method, device and system; Lixin Zhang and <b>Biwei Xie</b>; Huawei Technologies Co., Ltd.
</li>
</ul>
<h2>Professional Services:</h2>
<ul>
<li>Sponsorship Chair of Benchmarking, Measuring, and Optimizing (Bench), 2018 </li>
<li>External Reviewer of Parallel Architectures and Compilation Techniques (PACT), 2018</li>
<li>Reviewer of Transactions on Parallel and Distributed Systems (TPDS), 2018</li>
</ul>
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