hw: Improve parametrization, rename cluster tile (#14)

* cfg(floogen): Add description for address ranges

* make: Adapt to new `floogen` CLI

* deps: Bump dependencies

* hw: Improve parametrization

* hw: Rename `sparta_tile` to `cluster_tile`

* pd: Bump commit

* deps: Bump FlooNoC

* hw(pkg): Fix mesh output width of `get_mesh_dim` function

* deps: Bump FlooNoC

Author: fischeti

Bender.lock

@@ -24,8 +24,8 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
-    version: 0.2.1
+    revision: 59bb8a681347e1133f11a82190fbf4bc11900d9e
+    version: 0.2.2
     source:
       Git: https://github.com/pulp-platform/axi_llc.git
     dependencies:
@@ -120,8 +120,8 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
-    version: 1.37.0
+    revision: 9afda9abb565971649c2aa0985639c096f351171
+    version: 1.38.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -151,7 +151,7 @@ packages:
     dependencies:
     - axi
   floo_noc:
-    revision: 5c2762f2e02017d50b5a35ee2d076a23af4b2d07
+    revision: 38a1b70fa9f94a85da5910defdd0e60fea9ab4c0
     version: null
     source:
       Git: https://github.com/pulp-platform/FlooNoC.git
@@ -233,11 +233,12 @@ packages:
     - common_cells
     - tech_cells_generic
   scm:
-    revision: 998466d2a3c2d7d572e43d2666d93c4f767d8d60
-    version: 1.1.1
+    revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
+    version: 1.2.0
     source:
       Git: https://github.com/pulp-platform/scm.git
-    dependencies: []
+    dependencies:
+    - tech_cells_generic
   serial_link:
     revision: c55df03a1da06b00e567cf968b1b1a5f40c9f802
     version: 1.1.2

Bender.yml

@@ -20,11 +20,11 @@ sources:
   # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
   # levels 1 and 0, etc. Files within a level are ordered alphabetically.
   # Level 0
-  - .generated/floo_picobello_noc.sv
+  - .generated/floo_picobello_noc_pkg.sv
   # Level 1
   - hw/picobello_pkg.sv
   # Level 2
-  - hw/sparta_tile.sv
+  - hw/cluster_tile.sv
   - hw/cheshire_tile.sv
   - hw/mem_tile.sv
   # Level 3

Makefile

@@ -67,12 +67,12 @@ FLOO_ROOT = $(shell $(BENDER) path floo_noc)
 FLOO_GEN	?= floogen
 FLOO_CFG = $(PB_ROOT)/cfg/picobello_noc.yml
 
-floo-hw-all: $(PB_GEN_DIR)/floo_picobello_noc.sv
-$(PB_GEN_DIR)/floo_picobello_noc.sv: $(FLOO_CFG) | $(PB_GEN_DIR)
-	$(FLOO_GEN) -c $(FLOO_CFG) -o $(PB_GEN_DIR) $(FLOO_GEN_ARGS)
+floo-hw-all: $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
+$(PB_GEN_DIR)/floo_picobello_noc_pkg.sv: $(FLOO_CFG) | $(PB_GEN_DIR)
+	$(FLOO_GEN) -c $(FLOO_CFG) -o $(PB_GEN_DIR) --only-pkg
 
 floo-clean:
-	rm -rf $(PB_GEN_DIR)/floo_picobello_noc.sv
+	rm -rf $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
 
 .PHONY: floo-install-floogen
 floo-install-floogen:
@@ -83,7 +83,7 @@ floo-install-floogen:
 ###################
 
 PD_REMOTE ?= [email protected]:picobello/picobello-pd.git
-PD_COMMIT ?= cd9f7dd2be136b02a620a99126c3e0c2c659e98f
+PD_COMMIT ?= b1a84dd3a762ce8d3837c540d9afd8605b1d05e7
 PD_DIR = $(PB_ROOT)/pd
 
 .PHONY: init-pd clean-pd
@@ -105,7 +105,7 @@ clean-pd:
 PB_HW_ALL += $(CHS_HW_ALL)
 PB_HW_ALL += $(CHS_SIM_ALL)
 PB_HW_ALL += $(SN_GEN_DIR)/snitch_cluster_wrapper.sv
-PB_HW_ALL += $(PB_GEN_DIR)/floo_picobello_noc.sv
+PB_HW_ALL += $(PB_GEN_DIR)/floo_picobello_noc_pkg.sv
 
 .PHONY: picobello-hw-all picobello-clean clean
 

cfg/picobello_noc.yml

@@ -56,8 +56,10 @@ endpoints:
     addr_range:
       - start: 0x0000_0000
         end: 0x2000_0000
+        desc: "internal"
       - start: 0x8000_0000
         end: 0x2_0000_0000
+        desc: "external"
     mgr_port_protocol:
       - "narrow_in"
     sbr_port_protocol:

hw/sparta_tile.sv hw/cluster_tile.sv

@@ -6,7 +6,7 @@
 
 `include "axi/assign.svh"
 
-module sparta_tile
+module cluster_tile
   import floo_pkg::*;
   import floo_picobello_noc_pkg::*;
   import picobello_pkg::*;

hw/picobello_pkg.sv

@@ -19,16 +19,32 @@ package picobello_pkg;
   //  FlooNoC  //
   ///////////////
 
-  // TODO: make this better parametrizable
-  localparam int unsigned NumXMesh = 3;
-  localparam int unsigned NumYMesh = 2;
+  typedef struct packed {
+    int unsigned x;
+    int unsigned y;
+  } mesh_dim_t;
+
+  function automatic mesh_dim_t get_mesh_dim();
+    mesh_dim_t tile_id_max = '{x: 0, y: 0};
+    mesh_dim_t tile_id_min = '{x: '1, y: '1};
+    for (int i = 0; i < SamNumRules; i++) begin
+      tile_id_max.x = max(tile_id_max.x, int'(Sam[i].idx.x));
+      tile_id_max.y = max(tile_id_max.y, int'(Sam[i].idx.y));
+      tile_id_min.x = min(tile_id_min.x, int'(Sam[i].idx.x));
+      tile_id_min.y = min(tile_id_min.y, int'(Sam[i].idx.y));
+    end
+    return '{x: tile_id_max.x - tile_id_min.x + 1,
+             y: tile_id_max.y - tile_id_min.y + 1};
+  endfunction
+
+  localparam mesh_dim_t MeshDim = get_mesh_dim();
+  localparam int unsigned NumTiles = MeshDim.x * MeshDim.y;
   localparam int unsigned NumClusters = Cheshire - ClusterX0Y0;
-  localparam int unsigned NumTiles = NumXMesh * NumYMesh;
 
   // Whether the connection is a tie-off or a valid neighbor
   function automatic bit is_tie_off(int x, int y, route_direction_e dir);
-    return (x == 0 && dir == West) || (x == NumXMesh-1 && dir == East) ||
-           (y == 0 && dir == South) || (y == NumYMesh-1 && dir == North);
+    return (x == 0 && dir == West) || (x == MeshDim.x-1 && dir == East) ||
+           (y == 0 && dir == South) || (y == MeshDim.y-1 && dir == North);
   endfunction
 
   // Returns the X-coordinate of the neighbor in the given direction
@@ -47,7 +63,7 @@ package picobello_pkg;
   endfunction
 
   // Returns the address size of a FlooNoC endpoint
-  function automatic int unsigned ep_addr_size(ep_id_e ep);
+  function automatic int unsigned ep_addr_size(sam_idx_e ep);
     return Sam[ep].end_addr - Sam[ep].start_addr;
   endfunction
 
@@ -91,8 +107,7 @@ package picobello_pkg;
   //  Mem Tile  //
   ////////////////
 
-  // TODO(fischeti): Fix the index in FlooGen
   // The L2 SPM memory size of every mem tile
-  localparam int unsigned MemTileSize = ep_addr_size(ep_id_e'(L2Spm+1));
+  localparam int unsigned MemTileSize = ep_addr_size(L2SpmSamIdx);
 
 endpackage

hw/picobello_top.sv

@@ -59,16 +59,13 @@ module picobello_top
   output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0]  slink_o
 );
 
-  localparam int unsigned NumClusters = Cheshire - ClusterX0Y0;
+  floo_req_t [MeshDim.x-1:0][MeshDim.y-1:0][West:North] floo_req_in, floo_req_out;
+  floo_rsp_t [MeshDim.x-1:0][MeshDim.y-1:0][West:North] floo_rsp_in, floo_rsp_out;
+  floo_wide_t [MeshDim.x-1:0][MeshDim.y-1:0][West:North] floo_wide_in, floo_wide_out;
 
-  floo_req_t [NumXMesh-1:0][NumYMesh-1:0][West:North] floo_req_in, floo_req_out;
-  floo_rsp_t [NumXMesh-1:0][NumYMesh-1:0][West:North] floo_rsp_in, floo_rsp_out;
-  floo_wide_t [NumXMesh-1:0][NumYMesh-1:0][West:North] floo_wide_in, floo_wide_out;
-
-
-  //////////////////
-  // SPARTA tiles //
-  //////////////////
+  ///////////////////
+  // Cluster tiles //
+  ///////////////////
 
   logic [NumClusters-1:0][NrCores-1:0] debug_req, meip, mtip, msip;
 
@@ -78,13 +75,16 @@ module picobello_top
   assign mtip = '0;
   assign msip = '0;
 
-  for (genvar c = int'(ClusterX0Y0); c < ClusterX0Y0 + NumClusters; c++) begin : gen_clusters
+  for (genvar c = 0; c < NumClusters; c++) begin : gen_clusters
 
-    localparam int X = int'(Sam[c].idx.x);
-    localparam int Y = int'(Sam[c].idx.y);
-    localparam int unsigned HartBaseId = (c - ClusterX0Y0) * NrCores;
+    localparam int ClusterSamIdx = c + ClusterX0Y0SamIdx;
+    localparam id_t ClusterId = Sam[ClusterSamIdx].idx;
+    localparam int X = int'(ClusterId.x);
+    localparam int Y = int'(ClusterId.y);
+    localparam int unsigned HartBaseId = c * NrCores;
+    localparam axi_wide_in_addr_t ClusterBaseAddr = Sam[ClusterSamIdx].start_addr;
 
-    sparta_tile i_sparta_tile (
+    cluster_tile i_cluster_tile (
       .clk_i,
       .rst_ni,
       .test_enable_i        ( test_mode_i         ),
@@ -93,8 +93,8 @@ module picobello_top
       .mtip_i               ( mtip[c]             ),
       .msip_i               ( msip[c]             ),
       .hart_base_id_i       ( HartBaseId[9:0]     ),
-      .cluster_base_addr_i  ( Sam[c].start_addr   ),
-      .id_i                 ( Sam[c].idx          ),
+      .cluster_base_addr_i  ( ClusterBaseAddr     ),
+      .id_i                 ( ClusterId           ),
       .floo_req_o           ( floo_req_out[X][Y]  ),
       .floo_rsp_i           ( floo_rsp_in[X][Y]   ),
       .floo_wide_o          ( floo_wide_out[X][Y] ),
@@ -113,7 +113,7 @@ module picobello_top
   logic [iomsb(CheshireCfg.NumExtIrqHarts):0]             mtip_ext;
   logic [iomsb(CheshireCfg.NumExtIrqHarts):0]             msip_ext;
 
-  localparam id_t CheshireId = Sam[Cheshire].idx;
+  localparam id_t CheshireId = Sam[CheshireInternalSamIdx].idx;
 
   cheshire_tile i_cheshire_tile (
     .clk_i,
@@ -166,12 +166,12 @@ module picobello_top
     .floo_rsp_o     (floo_rsp_out[CheshireId.x][CheshireId.y]),
     .floo_wide_i    (floo_wide_in[CheshireId.x][CheshireId.y])
   );
+
   //////////////
   // Mem tile //
   //////////////
 
-  // TODO(fischeti): Make this better parametrizable
-  localparam id_t MemTileId = Sam[L2Spm+1].idx;
+  localparam id_t MemTileId = Sam[L2SpmSamIdx].idx;
 
   mem_tile i_mem_tile (
     .clk_i,
@@ -190,8 +190,8 @@ module picobello_top
   // NoC Connections //
   /////////////////////
 
-  for (genvar x = 0; x < NumXMesh; x++) begin : gen_x
-    for (genvar y = 0; y < NumYMesh; y++) begin : gen_y
+  for (genvar x = 0; x < MeshDim.x; x++) begin : gen_x
+    for (genvar y = 0; y < MeshDim.y; y++) begin : gen_y
       for (genvar d = int'(North); d <= int'(West); d++) begin : gen_dir
         localparam route_direction_e Dir = route_direction_e'(d);
         if (is_tie_off(x, y, Dir)) begin : gen_tie_off