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hw: Generalize DMMCAST and CSR_MCAST and adapt user field transmission
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20 files changed

+137
-82
lines changed

20 files changed

+137
-82
lines changed

‎hw/reqrsp_interface/include/reqrsp_interface/typedef.svh‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,15 @@
88
`ifndef REQRSP_INTERFACE_TYPEDEF_SVH_
99
`define REQRSP_INTERFACE_TYPEDEF_SVH_
1010

11-
`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t) \
11+
`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \
1212
typedef struct packed { \
13-
__addr_t addr; \
14-
__addr_t mask; \
15-
logic write; \
16-
reqrsp_pkg::amo_op_e amo; \
17-
__data_t data; \
18-
__strb_t strb; \
19-
reqrsp_pkg::size_t size; \
13+
__addr_t addr; \
14+
logic write; \
15+
reqrsp_pkg::amo_op_e amo; \
16+
__data_t data; \
17+
__strb_t strb; \
18+
__user_t user; \
19+
reqrsp_pkg::size_t size; \
2020
} __req_chan_t;
2121

2222
`define REQRSP_TYPEDEF_RSP_CHAN_T(__rsp_chan_t, __data_t) \
@@ -39,8 +39,8 @@
3939
logic q_ready; \
4040
} __rsp_t;
4141

42-
`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \
43-
`REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t) \
42+
`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __user_t) \
43+
`REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \
4444
`REQRSP_TYPEDEF_RSP_CHAN_T(__name``_rsp_chan_t, __data_t) \
4545
`REQRSP_TYPEDEF_REQ_T(__name``_req_t, __name``_req_chan_t) \
4646
`REQRSP_TYPEDEF_RSP_T(__name``_rsp_t, __name``_rsp_chan_t)

‎hw/reqrsp_interface/src/axi_to_reqrsp.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -448,7 +448,7 @@ module axi_to_reqrsp_intf #(
448448
typedef logic [IdWidth-1:0] id_t;
449449
typedef logic [UserWidth-1:0] user_t;
450450

451-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
451+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
452452

453453
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
454454
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)

‎hw/reqrsp_interface/src/reqrsp_cut.sv‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@ module reqrsp_cut #(
1212
parameter int unsigned AddrWidth = 0,
1313
/// Data width of the interface.
1414
parameter int unsigned DataWidth = 0,
15+
/// User width of the interface.
16+
parameter int unsigned UserWidth = 0,
1517
/// Request type.
1618
parameter type req_t = logic,
1719
/// Response type.
@@ -32,8 +34,9 @@ module reqrsp_cut #(
3234
typedef logic [AddrWidth-1:0] addr_t;
3335
typedef logic [DataWidth-1:0] data_t;
3436
typedef logic [DataWidth/8-1:0] strb_t;
37+
typedef logic [UserWidth-1:0] user_t;
3538

36-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
39+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
3740

3841
spill_register #(
3942
.T (reqrsp_req_chan_t),
@@ -74,6 +77,8 @@ module reqrsp_cut_intf #(
7477
parameter int unsigned AddrWidth = 0,
7578
/// Data width of the interface.
7679
parameter int unsigned DataWidth = 0,
80+
/// User width of the interface.
81+
parameter int unsigned UserWidth = 0,
7782
/// Bypass request channel.
7883
parameter bit BypassReq = 0,
7984
/// Bypass Response channel.
@@ -88,15 +93,17 @@ module reqrsp_cut_intf #(
8893
typedef logic [AddrWidth-1:0] addr_t;
8994
typedef logic [DataWidth-1:0] data_t;
9095
typedef logic [DataWidth/8-1:0] strb_t;
96+
typedef logic [UserWidth-1:0] user_t;
9197

92-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
98+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
9399

94100
reqrsp_req_t reqrsp_slv_req, reqrsp_mst_req;
95101
reqrsp_rsp_t reqrsp_slv_rsp, reqrsp_mst_rsp;
96102

97103
reqrsp_cut #(
98104
.AddrWidth (AddrWidth),
99105
.DataWidth (DataWidth),
106+
.UserWidth (UserWidth),
100107
.req_t (reqrsp_req_t),
101108
.rsp_t (reqrsp_rsp_t),
102109
.BypassReq (BypassReq),

‎hw/reqrsp_interface/src/reqrsp_demux.sv‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,8 @@ module reqrsp_demux_intf #(
104104
parameter int unsigned AddrWidth = 0,
105105
/// Data width of the interface.
106106
parameter int unsigned DataWidth = 0,
107+
/// User width of the interface.
108+
parameter int unsigned UserWidth = 0,
107109
/// Amount of outstanding responses. Determines the FIFO size.
108110
parameter int unsigned RespDepth = 8,
109111
// Dependent parameters, DO NOT OVERRIDE!
@@ -120,8 +122,9 @@ module reqrsp_demux_intf #(
120122
typedef logic [AddrWidth-1:0] addr_t;
121123
typedef logic [DataWidth-1:0] data_t;
122124
typedef logic [DataWidth/8-1:0] strb_t;
125+
typedef logic [UserWidth-1:0] user_t;
123126

124-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
127+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
125128

126129
reqrsp_req_t reqrsp_slv_req;
127130
reqrsp_rsp_t reqrsp_slv_rsp;

‎hw/reqrsp_interface/src/reqrsp_iso.sv‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@ module reqrsp_iso #(
1414
parameter int unsigned AddrWidth = 0,
1515
/// Data width of the interface.
1616
parameter int unsigned DataWidth = 0,
17+
/// User width of the interface.
18+
parameter int unsigned UserWidth = 0,
1719
/// Request type.
1820
parameter type req_t = logic,
1921
/// Response type.
@@ -43,8 +45,9 @@ module reqrsp_iso #(
4345
typedef logic [AddrWidth-1:0] addr_t;
4446
typedef logic [DataWidth-1:0] data_t;
4547
typedef logic [DataWidth/8-1:0] strb_t;
48+
typedef logic [UserWidth-1:0] user_t;
4649

47-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
50+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
4851

4952
isochronous_spill_register #(
5053
.T (reqrsp_req_chan_t),
@@ -89,6 +92,8 @@ module reqrsp_iso_intf #(
8992
parameter int unsigned AddrWidth = 0,
9093
/// Data width of the interface.
9194
parameter int unsigned DataWidth = 0,
95+
/// User width of the interface.
96+
parameter int unsigned UserWidth = 0,
9297
/// Bypass.
9398
parameter bit BypassReq = 0,
9499
parameter bit BypassRsp = 0
@@ -110,15 +115,17 @@ module reqrsp_iso_intf #(
110115
typedef logic [AddrWidth-1:0] addr_t;
111116
typedef logic [DataWidth-1:0] data_t;
112117
typedef logic [DataWidth/8-1:0] strb_t;
118+
typedef logic [UserWidth-1:0] user_t;
113119

114-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
120+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
115121

116122
reqrsp_req_t reqrsp_src_req, reqrsp_dst_req;
117123
reqrsp_rsp_t reqrsp_src_rsp, reqrsp_dst_rsp;
118124

119125
reqrsp_iso #(
120126
.AddrWidth (AddrWidth),
121127
.DataWidth (DataWidth),
128+
.UserWidth (UserWidth),
122129
.req_t (reqrsp_req_t),
123130
.rsp_t (reqrsp_rsp_t),
124131
.BypassReq (BypassReq),

‎hw/reqrsp_interface/src/reqrsp_mux.sv‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@ module reqrsp_mux #(
1414
parameter int unsigned AddrWidth = 0,
1515
/// Data width of the interface.
1616
parameter int unsigned DataWidth = 0,
17+
/// User width of the interface.
18+
parameter int unsigned UserWidth = 0,
1719
/// Request type.
1820
parameter type req_t = logic,
1921
/// Response type.
@@ -39,8 +41,9 @@ module reqrsp_mux #(
3941
typedef logic [AddrWidth-1:0] addr_t;
4042
typedef logic [DataWidth-1:0] data_t;
4143
typedef logic [DataWidth/8-1:0] strb_t;
44+
typedef logic [UserWidth-1:0] user_t;
4245

43-
`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t)
46+
`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t, user_t)
4447

4548
localparam int unsigned LogNrPorts = cf_math_pkg::idx_width(NrPorts);
4649

@@ -159,6 +162,8 @@ module reqrsp_mux_intf #(
159162
parameter int unsigned AddrWidth = 0,
160163
/// Data width of the interface.
161164
parameter int unsigned DataWidth = 0,
165+
/// User width of the interface.
166+
parameter int unsigned UserWidth = 0,
162167
/// Amount of outstanding responses. Determines the FIFO size.
163168
parameter int unsigned RespDepth = 8,
164169
/// Cut timing paths on the request path. Incurs a cycle additional latency.
@@ -175,8 +180,9 @@ module reqrsp_mux_intf #(
175180
typedef logic [AddrWidth-1:0] addr_t;
176181
typedef logic [DataWidth-1:0] data_t;
177182
typedef logic [DataWidth/8-1:0] strb_t;
183+
typedef logic [UserWidth-1:0] user_t;
178184

179-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
185+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
180186

181187
reqrsp_req_t [NrPorts-1:0] reqrsp_slv_req;
182188
reqrsp_rsp_t [NrPorts-1:0] reqrsp_slv_rsp;
@@ -188,6 +194,7 @@ module reqrsp_mux_intf #(
188194
.NrPorts (NrPorts),
189195
.AddrWidth (AddrWidth),
190196
.DataWidth (DataWidth),
197+
.UserWidth (UserWidth),
191198
.req_t (reqrsp_req_t),
192199
.rsp_t (reqrsp_rsp_t),
193200
.RespDepth (RespDepth),

‎hw/reqrsp_interface/src/reqrsp_to_axi.sv‎

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -48,15 +48,13 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
4848
parameter int unsigned ID = 0,
4949
/// Data width of bus, must be 32 or 64.
5050
parameter int unsigned DataWidth = 32'b0,
51-
parameter int unsigned UserWidth = 32'b0,
5251
parameter type reqrsp_req_t = logic,
5352
parameter type reqrsp_rsp_t = logic,
5453
parameter type axi_req_t = logic,
5554
parameter type axi_rsp_t = logic
5655
) (
5756
input logic clk_i,
5857
input logic rst_ni,
59-
input logic [UserWidth-1:0] user_i,
6058
input reqrsp_req_t reqrsp_req_i,
6159
output reqrsp_rsp_t reqrsp_rsp_o,
6260
output axi_req_t axi_req_o,
@@ -175,7 +173,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
175173
assign axi_req_o.ar.lock = (reqrsp_req_i.q.amo == AMOLR);
176174
assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE;
177175
assign axi_req_o.ar.id = $unsigned(ID);
178-
assign axi_req_o.ar.user = user_i;
176+
assign axi_req_o.ar.user = reqrsp_req_i.q.user;
179177
assign axi_req_o.ar_valid = q_valid_read;
180178
assign q_ready_read = axi_rsp_i.ar_ready;
181179

@@ -190,11 +188,11 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
190188
assign axi_req_o.aw.lock = (reqrsp_req_i.q.amo == AMOSC);
191189
assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE;
192190
assign axi_req_o.aw.id = $unsigned(ID);
193-
assign axi_req_o.aw.user = user_i;
191+
assign axi_req_o.aw.user = reqrsp_req_i.q.user;
194192
assign axi_req_o.w.data = write_data;
195193
assign axi_req_o.w.strb = reqrsp_req_i.q.strb;
196194
assign axi_req_o.w.last = 1'b1;
197-
assign axi_req_o.w.user = user_i;
195+
assign axi_req_o.w.user = reqrsp_req_i.q.user;
198196

199197
// Both channels need to handshake (independently).
200198
stream_fork #(
@@ -305,12 +303,11 @@ module reqrsp_to_axi_intf #(
305303
parameter int unsigned AddrWidth = 32'd0,
306304
/// AXI and REQRSP data width.
307305
parameter int unsigned DataWidth = 32'd0,
308-
/// AXI user width.
309-
parameter int unsigned AxiUserWidth = 32'd0
306+
/// AXI and REQRSP user width.
307+
parameter int unsigned UserWidth = 32'd0
310308
) (
311309
input logic clk_i,
312310
input logic rst_ni,
313-
input logic [AxiUserWidth-1:0] user_i,
314311
REQRSP_BUS reqrsp,
315312
AXI_BUS axi
316313
);
@@ -319,9 +316,9 @@ module reqrsp_to_axi_intf #(
319316
typedef logic [DataWidth-1:0] data_t;
320317
typedef logic [DataWidth/8-1:0] strb_t;
321318
typedef logic [AxiIdWidth-1:0] id_t;
322-
typedef logic [AxiUserWidth-1:0] user_t;
319+
typedef logic [UserWidth-1:0] user_t;
323320

324-
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
321+
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)
325322

326323
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
327324
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
@@ -347,7 +344,6 @@ module reqrsp_to_axi_intf #(
347344
) i_reqrsp_to_axi (
348345
.clk_i,
349346
.rst_ni,
350-
.user_i,
351347
.reqrsp_req_i (reqrsp_req),
352348
.reqrsp_rsp_o (reqrsp_rsp),
353349
.axi_req_o (axi_req),

‎hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,11 +58,10 @@ module reqrsp_to_axi_tb import reqrsp_pkg::*; #(
5858
.AxiIdWidth (IW),
5959
.AddrWidth (AW),
6060
.DataWidth (DW),
61-
.AxiUserWidth (UW)
61+
.UserWidth (UW)
6262
) i_reqrsp_to_axi (
6363
.clk_i (clk),
6464
.rst_ni (rst_n),
65-
.user_i ('0),
6665
.reqrsp (master),
6766
.axi (slave)
6867
);

‎hw/snitch/src/riscv_instr.sv‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ package riscv_instr;
327327
localparam logic [31:0] DMSTAT = 32'b0000101?????00000000?????0101011;
328328
localparam logic [31:0] DMSTR = 32'b0000110??????????000000000101011;
329329
localparam logic [31:0] DMREP = 32'b000011100000?????000000000101011;
330-
localparam logic [31:0] DMMCAST = 32'b000100000000?????000000000101011;
330+
localparam logic [31:0] DMUSER = 32'b0001000??????????000000000101011;
331331
localparam logic [31:0] FREP_O = 32'b????????????????????????10001011;
332332
localparam logic [31:0] IREP = 32'b?????????????????????????0111111;
333333
localparam logic [31:0] SCFGRI = 32'b????????????00000001?????0101011;
@@ -1140,7 +1140,8 @@ package riscv_instr;
11401140
localparam logic [11:0] CSR_FPMODE = 12'h7c1;
11411141
localparam logic [11:0] CSR_BARRIER = 12'h7c2;
11421142
localparam logic [11:0] CSR_SC = 12'h7c3;
1143-
localparam logic [11:0] CSR_MCAST = 12'h7c4;
1143+
localparam logic [11:0] CSR_USER_LOW = 12'h7c4;
1144+
localparam logic [11:0] CSR_USER_HIGH = 12'h7c5;
11441145
localparam logic [11:0] CSR_HTIMEDELTAH = 12'h615;
11451146
localparam logic [11:0] CSR_CYCLEH = 12'hc80;
11461147
localparam logic [11:0] CSR_TIMEH = 12'hc81;

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