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| 1 | +// Copyright 2025 ETH Zurich and University of Bologna. |
| 2 | +// Solderpad Hardware License, Version 0.51, see LICENSE for details. |
| 3 | +// SPDX-License-Identifier: SHL-0.51 |
| 4 | + |
| 5 | +// Author: Luca Colagrande <[email protected]> |
| 6 | + |
| 7 | +`include "reqrsp_interface/typedef.svh" |
| 8 | + |
| 9 | +/// Multiplex multiple generic `reqrsp`-like ports onto one, based on arbitration. |
| 10 | +module generic_reqrsp_mux #( |
| 11 | + /// Number of input ports. |
| 12 | + parameter int unsigned NrPorts = 2, |
| 13 | + /// Request channel type. |
| 14 | + parameter type req_chan_t = logic, |
| 15 | + /// Response channel type. |
| 16 | + parameter type rsp_chan_t = logic, |
| 17 | + /// Amount of outstanding responses. Determines the FIFO size. |
| 18 | + parameter int unsigned RspDepth = 8, |
| 19 | + /// Cut timing paths on the request path. Incurs a cycle additional latency. |
| 20 | + /// Registers are inserted at the slave side. |
| 21 | + parameter bit [NrPorts-1:0] RegisterReq = '0, |
| 22 | + /// Externally provide routing information for responses. Can be used when |
| 23 | + /// storing response routes externally, e.g. as a source tag passed along a |
| 24 | + /// pipeline, i.e. when RspDepth == 0. |
| 25 | + parameter bit ExtRspRoute = 1'b0, |
| 26 | + /// Dependent parameters *do not override* |
| 27 | + /// Width of the arbitrated index. |
| 28 | + localparam int unsigned IdxWidth = cf_math_pkg::idx_width(NrPorts), |
| 29 | + localparam type req_t = `GENERIC_REQRSP_REQ_STRUCT(req_chan_t), |
| 30 | + localparam type rsp_t = `GENERIC_REQRSP_RSP_STRUCT(rsp_chan_t) |
| 31 | +) ( |
| 32 | + input logic clk_i, |
| 33 | + input logic rst_ni, |
| 34 | + input req_t [NrPorts-1:0] slv_req_i, |
| 35 | + output rsp_t [NrPorts-1:0] slv_rsp_o, |
| 36 | + output req_t mst_req_o, |
| 37 | + input rsp_t mst_rsp_i, |
| 38 | + // Route responses should follow when using external routing. |
| 39 | + input logic [IdxWidth-1:0] rsp_route_i, |
| 40 | + // Request port select by the arbitration logic. |
| 41 | + output logic [IdxWidth-1:0] idx_o |
| 42 | +); |
| 43 | + |
| 44 | + logic [NrPorts-1:0] req_valid_masked, req_ready_masked; |
| 45 | + logic [IdxWidth-1:0] idx, idx_rsp; |
| 46 | + logic full; |
| 47 | + |
| 48 | + req_chan_t [NrPorts-1:0] req_payload_q; |
| 49 | + logic [NrPorts-1:0] req_valid_q, req_ready_q; |
| 50 | + |
| 51 | + // Unforunately we need this signal otherwise the simulator complains about |
| 52 | + // multiple driven signals, because some other signals are driven from an |
| 53 | + // `always_comb` block. |
| 54 | + logic [NrPorts-1:0] slv_rsp_q_ready; |
| 55 | + |
| 56 | + // Optionally cut the incoming paths |
| 57 | + for (genvar i = 0; i < NrPorts; i++) begin : gen_cuts |
| 58 | + spill_register #( |
| 59 | + .T (req_chan_t), |
| 60 | + .Bypass (!RegisterReq[i]) |
| 61 | + ) i_spill_register_req ( |
| 62 | + .clk_i, |
| 63 | + .rst_ni, |
| 64 | + .valid_i (slv_req_i[i].q_valid), |
| 65 | + .ready_o (slv_rsp_q_ready[i]), |
| 66 | + .data_i (slv_req_i[i].q), |
| 67 | + .valid_o (req_valid_q[i]), |
| 68 | + .ready_i (req_ready_masked[i]), |
| 69 | + .data_o (req_payload_q[i]) |
| 70 | + ); |
| 71 | + end |
| 72 | + |
| 73 | + // We need to silence the handshake in case the fifo is full and we can't |
| 74 | + // accept more transactions. |
| 75 | + for (genvar i = 0; i < NrPorts; i++) begin : gen_req_valid_masked |
| 76 | + assign req_valid_masked[i] = req_valid_q[i] & ~full; |
| 77 | + assign req_ready_masked[i] = req_ready_q[i] & ~full; |
| 78 | + end |
| 79 | + |
| 80 | + /// Arbitrate requests |
| 81 | + rr_arb_tree #( |
| 82 | + .NumIn (NrPorts), |
| 83 | + .DataType (req_chan_t), |
| 84 | + .AxiVldRdy (1'b1), |
| 85 | + .LockIn (1'b1) |
| 86 | + ) i_q_mux ( |
| 87 | + .clk_i, |
| 88 | + .rst_ni, |
| 89 | + .flush_i (1'b0), |
| 90 | + .rr_i ('0), |
| 91 | + .req_i (req_valid_masked), |
| 92 | + .gnt_o (req_ready_q), |
| 93 | + .data_i (req_payload_q), |
| 94 | + .gnt_i (mst_rsp_i.q_ready), |
| 95 | + .req_o (mst_req_o.q_valid), |
| 96 | + .data_o (mst_req_o.q), |
| 97 | + .idx_o (idx_o) |
| 98 | + ); |
| 99 | + |
| 100 | + // De-generate version does not need a fifo. We always know where to route |
| 101 | + // back the responses. |
| 102 | + if (NrPorts == 1) begin : gen_single_port |
| 103 | + assign idx_rsp = 0; |
| 104 | + assign full = 1'b0; |
| 105 | + end else begin : gen_multi_port |
| 106 | + if (ExtRspRoute) begin : gen_no_rsp_fifo |
| 107 | + // Alternatively select route based on externally provided information. |
| 108 | + assign idx_rsp = rsp_route_i; |
| 109 | + assign full = 1'b0; |
| 110 | + end else begin : gen_rsp_fifo |
| 111 | + // For the "normal" case we need to save the arbitration decision. We do so |
| 112 | + // by converting the handshake into a binary signal which we save for |
| 113 | + // response routing. |
| 114 | + onehot_to_bin #( |
| 115 | + .ONEHOT_WIDTH (NrPorts) |
| 116 | + ) i_onehot_to_bin ( |
| 117 | + .onehot (req_valid_q & req_ready_q), |
| 118 | + .bin (idx) |
| 119 | + ); |
| 120 | + // Save the arbitration decision. |
| 121 | + fifo_v3 #( |
| 122 | + .DATA_WIDTH (IdxWidth), |
| 123 | + .DEPTH (RspDepth) |
| 124 | + ) i_rsp_fifo ( |
| 125 | + .clk_i, |
| 126 | + .rst_ni, |
| 127 | + .flush_i (1'b0), |
| 128 | + .testmode_i (1'b0), |
| 129 | + .full_o (full), |
| 130 | + .empty_o (), |
| 131 | + .usage_o (), |
| 132 | + .data_i (idx), |
| 133 | + .push_i (mst_req_o.q_valid & mst_rsp_i.q_ready), |
| 134 | + .data_o (idx_rsp), |
| 135 | + .pop_i (mst_req_o.p_ready & mst_rsp_i.p_valid) |
| 136 | + ); |
| 137 | + end |
| 138 | + end |
| 139 | + |
| 140 | + // Output Mux |
| 141 | + always_comb begin |
| 142 | + for (int i = 0; i < NrPorts; i++) begin |
| 143 | + slv_rsp_o[i].p_valid = '0; |
| 144 | + slv_rsp_o[i].q_ready = slv_rsp_q_ready[i]; |
| 145 | + slv_rsp_o[i].p = mst_rsp_i.p; |
| 146 | + end |
| 147 | + slv_rsp_o[idx_rsp].p_valid = mst_rsp_i.p_valid; |
| 148 | + end |
| 149 | + |
| 150 | + assign mst_req_o.p_ready = slv_req_i[idx_rsp].p_ready; |
| 151 | + |
| 152 | +endmodule |
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