[treewide] initial support for X Interface

Author: Andrea Belano

hw/snitch/src/snitch.sv

@@ -51,6 +51,12 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   parameter type         acc_resp_t = logic,
   parameter type         pa_t       = logic,
   parameter type         l0_pte_t   = logic,
+  // XIF parameters
+  parameter int unsigned XifIdWidth = 4,
+  // XIF port types
+  parameter type         x_issue_req_t  = logic,
+  parameter type         x_issue_resp_t = logic,
+  parameter type         x_result_t     = logic,
   parameter int unsigned NumIntOutstandingLoads = 0,
   parameter int unsigned NumIntOutstandingMem = 0,
   parameter int unsigned NumDTLBEntries = 0,
@@ -91,6 +97,15 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   input  acc_resp_t     acc_prsp_i,
   input  logic          acc_pvalid_i,
   output logic          acc_pready_o,
+  // X Interface - Issue ports
+  output x_issue_req_t  x_issue_req_o,
+  input  x_issue_resp_t x_issue_resp_i,
+  output logic          x_issue_valid_o,
+  input  logic          x_issue_ready_i,
+  // X Interface - Result ports
+  input  x_result_t     x_result_i,
+  input  logic          x_result_valid_i,
+  output logic          x_result_ready_o,
   /// TCDM Data Interface
   /// Write transactions do not return data on the `P Channel`
   /// Transactions need to be handled strictly in-order.
@@ -148,15 +163,15 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   assign simm = $signed({inst_data_i[31:25], inst_data_i[11:7]});
   /* verilator lint_on WIDTH */
 
-  logic [31:0] opa, opb;
+  logic [31:0] opa, opb, opc;
   logic [32:0] adder_result;
   logic [31:0] alu_result;
 
-  logic [RegWidth-1:0] rd, rs1, rs2;
-  logic stall, lsu_stall, acc_stall, nonacc_stall, fence_stall;
+  logic [RegWidth-1:0] rd, rs1, rs2, rs3;
+  logic stall, lsu_stall, acc_stall, nonacc_stall, fence_stall, x_stall;
   // Register connections
-  logic [1:0][RegWidth-1:0] gpr_raddr;
-  logic [1:0][31:0]         gpr_rdata;
+  logic [2:0][RegWidth-1:0] gpr_raddr;
+  logic [2:0][31:0]         gpr_rdata;
   logic [0:0][RegWidth-1:0] gpr_waddr;
   logic [0:0][31:0]         gpr_wdata;
   logic [0:0]               gpr_we;
@@ -209,6 +224,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   logic retire_load; // retire a load instruction
   logic retire_i; // retire the rest of the base instruction set
   logic retire_acc; // retire an instruction we offloaded
+  logic retire_x; // retire a XIF-offloaded instruction
 
   logic valid_instr;
   logic exception;
@@ -227,7 +243,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   typedef enum logic [3:0] {
     None, Reg, IImmediate, UImmediate, JImmediate, SImmediate, SFImmediate, PC, CSR, CSRImmmediate
   } op_select_e;
-  op_select_e opa_select, opb_select;
+  op_select_e opa_select, opb_select, opc_select;
 
   logic write_rd; // write destination this cycle
   logic uses_rd;
@@ -338,6 +354,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   `FFAR(sb_q, sb_d, '0, clk_i, rst_i)
   `FFAR(fcsr_q, fcsr_d, '0, clk_i, rst_i)
 
+  // TODO(abelano) Should we add a performance counter for the XIF?
   // performance counter
   `ifdef SNITCH_ENABLE_PERF
   logic [63:0] cycle_q;
@@ -374,6 +391,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   // operand C is currently only used for load/store instructions
   assign acc_qreq_o.data_argc = ls_paddr;
 
+  // XIF ID counter
+  logic [XifIdWidth-1:0] xif_offload_counter_q;
+  `FFLAR(xif_offload_counter_q, xif_offload_counter_q + 1, x_issue_ready_i & x_issue_valid_o, '0, clk_i, rst_i)
+
   // ---------
   // L0 ITLB
   // ---------
@@ -441,13 +462,17 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     sb_d = sb_q;
     if (retire_load) sb_d[lsu_rd] = 1'b0;
     // only place the reservation if we actually executed the load or offload instruction
-    if ((is_load | acc_register_rd) && !stall && !exception) sb_d[rd] = 1'b1;
+    if ((is_load | acc_register_rd | x_issue_valid_o & x_issue_ready_i & x_issue_resp_i.writeback) && !stall && !exception) sb_d[rd] = 1'b1;
     if (retire_acc) sb_d[acc_prsp_i.id[RegWidth-1:0]] = 1'b0;
+    if (retire_x) sb_d[x_result_i.rd] = 1'b0;
     sb_d[0] = 1'b0;
   end
   // TODO(zarubaf): This can probably be described a bit more efficient
   assign opa_ready = (opa_select != Reg) | ~sb_q[rs1];
   assign opb_ready = (opb_select != Reg & opb_select != SImmediate) | ~sb_q[rs2];
+  assign opc_ready = (opc_select != Reg) | ~sb_q[rs3];
+
+  // Here we do not use the opc_ready signal
   assign operands_ready = opa_ready & opb_ready;
   // either we are not using the destination register or we need to make
   // sure that its destination operand is not marked busy in the scoreboard.
@@ -460,14 +485,16 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
                       & ((itlb_valid & itlb_ready) | ~trans_active);
   // the accelerator interface stalled us. Also wait for CAQ if this is an FP load/store.
   assign acc_stall = acc_qvalid_o & ~acc_qready_i | (caq_ena & ~caq_qready);
+  // the coprocessor is not ready yet
+  assign x_stall = x_issue_valid_o & ~x_issue_ready_i;
   // the LSU Interface didn't accept our request yet
   assign lsu_stall = lsu_tlb_qvalid & ~lsu_tlb_qready;
   // Stall the stage if we either didn't get a valid instruction, the LSU is not ready
   // or we are waiting on a fence instruction.
   // We do not include accelerator stalls in this signal for loop-free CAQ enable control.
   assign nonacc_stall = ~valid_instr | lsu_stall | fence_stall;
   // To get the signal for all stall conditions, add the accelerator stalls.
-  assign stall = nonacc_stall | acc_stall;
+  assign stall = nonacc_stall | acc_stall | x_stall;
 
   // --------------------
   // Instruction Frontend
@@ -510,6 +537,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   assign rd = inst_data_i[7 + RegWidth - 1:7];
   assign rs1 = inst_data_i[15 + RegWidth - 1:15];
   assign rs2 = inst_data_i[20 + RegWidth - 1:20];
+  assign rs3 = inst_data_i[27 + RegWidth - 1:20];
 
   always_comb begin
     illegal_inst = 1'b0;
@@ -518,6 +546,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     alu_op = Add;
     opa_select = None;
     opb_select = None;
+    opc_select = None;
+
+    x_issue_req_o    = '0;
+    x_issue_valid_o  = '0;
 
     flush_i_valid_o = 1'b0;
     tlb_flush = 1'b0;
@@ -2268,8 +2300,27 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
         end else illegal_inst = 1'b1;
       end
 
-      default: begin
-        illegal_inst = 1'b1;
+      default: begin // Offload the instruction to the coprocessor
+        opa_select = Reg;
+        opb_select = Reg;
+        opc_select = Reg;
+
+        x_issue_req_o.instr     = inst_data_i;
+        x_issue_req_o.mode      = priv_lvl_q;
+        x_issue_req_o.id        = xif_offload_counter_q;
+        x_issue_req_o.rs        = {rs3, rs2, rs1};
+        x_issue_req_o.rs_valid  = {~sb_q[rs3], ~sb_q[rs2], ~sb_q[rs1]};
+        x_issue_req_o.ecs       = '0; // Not implemented
+        x_issue_req_o.ecs_valid = '0; // Not implemented
+
+        // Since we canno know whether a source register will be used or not by the processor,
+        // here we do not use valid_instr as in the other instructions
+        x_issue_valid_o         = inst_ready_i
+                                & inst_valid_o
+                                & ((itlb_valid & itlb_ready) | ~trans_active);
+
+        // Flag the instruction as illegal if not accepted by the coprocessor or if it requests an unsupported operation
+        illegal_inst = x_issue_ready_i & x_issue_valid_o & (~x_issue_resp_i.accept | |{x_issue_resp_i.dualwrite, x_issue_resp_i.dualread, x_issue_resp_i.loadstore, x_issue_resp_i.ecswrite});
       end
     endcase
 
@@ -2691,7 +2742,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
 
   snitch_regfile #(
     .DataWidth    ( 32       ),
-    .NrReadPorts  ( 2        ),
+    .NrReadPorts  ( 3        ),
     .NrWritePorts ( 1        ),
     .ZeroRegZero  ( 1        ),
     .AddrWidth    ( RegWidth )
@@ -2731,8 +2782,18 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     endcase
   end
 
+  // The C operand is currently only used for XIF instructions
+  always_comb begin
+    unique case (opc_select)
+      None: opc = '0;
+      Reg: opc = gpr_rdata[2];
+      default: opc = '0;
+    endcase
+  end
+
   assign gpr_raddr[0] = rs1;
   assign gpr_raddr[1] = rs2;
+  assign gpr_raddr[2] = rs3;
 
   // --------------------
   // ALU
@@ -2985,8 +3046,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     // external interfaces
     lsu_pready = 1'b0;
     acc_pready_o = 1'b0;
+    // Always assert x_result_ready if the coprocessor does not request a write
+    x_result_ready_o = ~x_result_i.we;
     retire_acc = 1'b0;
     retire_load = 1'b0;
+    retire_x = 1'b0;
 
     if (retire_i) begin
       gpr_we[0] = 1'b1;
@@ -3003,6 +3067,12 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       gpr_waddr[0] = acc_prsp_i.id;
       gpr_wdata[0] = acc_prsp_i.data[31:0];
       acc_pready_o = 1'b1;
+    end else if (x_result_valid_i & x_result_i.we) begin
+      retire_x = 1'b1;
+      gpr_we[0] = 1'b1;
+      gpr_waddr[0] = x_result_i.rd;
+      gpr_wdata[0] = x_result_i.data[31:0];
+      x_result_ready_o = 1'b1;
     end
   end
 

hw/snitch_cluster/src/snitch_cc.sv

@@ -45,6 +45,12 @@ module snitch_cc #(
   parameter type         acc_req_t          = logic,
   parameter type         acc_resp_t         = logic,
   parameter type         dma_events_t       = logic,
+  // XIF parameters
+  parameter int unsigned XifIdWidth         = 4,
+  // XIF port types
+  parameter type         x_issue_req_t      = logic,
+  parameter type         x_issue_resp_t     = logic,
+  parameter type         x_result_t         = logic,
   parameter fpnew_pkg::fpu_implementation_t FPUImplementation = '0,
   /// Boot address of core.
   parameter logic [31:0] BootAddr           = 32'h0000_1000,
@@ -133,7 +139,15 @@ module snitch_cc #(
   // TCDM Streamer Ports
   output tcdm_req_t [TCDMPorts-1:0]         tcdm_req_o,
   input  tcdm_rsp_t [TCDMPorts-1:0]         tcdm_rsp_i,
-  // Accelerator Offload port
+  // X Interface - Issue ports
+  output x_issue_req_t                      x_issue_req_o,
+  input  x_issue_resp_t                     x_issue_resp_i,
+  output logic                              x_issue_valid_o,
+  input  logic                              x_issue_ready_i,
+  // X Interface - Result ports
+  input  x_result_t                         x_result_i,
+  input  logic                              x_result_valid_i,
+  output logic                              x_result_ready_o,
   // DMA ports
   output axi_req_t    [DMANumChannels-1:0]  axi_dma_req_o,
   input  axi_rsp_t    [DMANumChannels-1:0]  axi_dma_res_i,
@@ -222,6 +236,10 @@ module snitch_cc #(
     .drsp_t (drsp_t),
     .pa_t (pa_t),
     .l0_pte_t (l0_pte_t),
+    .XifIdWidth (XifIdWidth),
+    .x_issue_req_t (x_issue_req_t),
+    .x_issue_resp_t (x_issue_resp_t),
+    .x_result_t (x_result_t),
     .BootAddr (BootAddr),
     .SnitchPMACfg (SnitchPMACfg),
     .NumIntOutstandingLoads (NumIntOutstandingLoads),
@@ -266,6 +284,13 @@ module snitch_cc #(
     .acc_prsp_i ( acc_demux_snitch ),
     .acc_pvalid_i ( acc_demux_snitch_valid ),
     .acc_pready_o ( acc_demux_snitch_ready ),
+    .x_issue_req_o ( x_issue_req_o ),
+    .x_issue_resp_i ( x_issue_resp_i ),
+    .x_issue_valid_o ( x_issue_valid_o ),
+    .x_issue_ready_i ( x_issue_ready_i ),
+    .x_result_i ( x_result_i ),
+    .x_result_valid_i ( x_result_valid_i ),
+    .x_result_ready_o ( x_result_ready_o ),
     .caq_pvalid_i ( caq_pvalid_q ),
     .data_req_o ( snitch_dreq_d ),
     .data_rsp_i ( snitch_drsp_d ),

hw/snitch_cluster/src/snitch_cluster.sv

@@ -206,6 +206,12 @@ module snitch_cluster
   // Memory configuration input types; these vary depending on implementation.
   parameter type         sram_cfg_t        = logic,
   parameter type         sram_cfgs_t       = logic,
+  // XIF parameters
+  parameter int unsigned XifIdWidth        = 4,
+  // XIF port types
+  parameter type         x_issue_req_t     = logic,
+  parameter type         x_issue_resp_t    = logic,
+  parameter type         x_result_t        = logic,
   // Memory latency parameter. Most of the memories have a read latency of 1. In
   // case you have memory macros which are pipelined you want to adjust this
   // value here. This only applies to the TCDM. The instruction cache macros will break!
@@ -270,6 +276,15 @@ module snitch_cluster
   /// AXI DMA cluster in-port.
   input  wide_in_req_t                            wide_in_req_i,
   output wide_in_resp_t                           wide_in_resp_o,
+  // X Interface - Issue ports
+  output x_issue_req_t [NrCores-1:0]              x_issue_req_o,
+  input  x_issue_resp_t [NrCores-1:0]             x_issue_resp_i,
+  output logic [NrCores-1:0]                      x_issue_valid_o,
+  input  logic [NrCores-1:0]                      x_issue_ready_i,
+  // X Interface - Result ports
+  input  x_result_t [NrCores-1:0]                 x_result_i,
+  input  logic [NrCores-1:0]                      x_result_valid_i,
+  output logic [NrCores-1:0]                      x_result_ready_o,
   // An additional AXI Core cluster out-port, used e.g. to connect
   // to the configuration interface of an external accelerator.
   // Compared to the `narrow_out` interface, the address space of
@@ -1035,6 +1050,10 @@ module snitch_cluster
         .acc_req_t (acc_req_t),
         .acc_resp_t (acc_resp_t),
         .dma_events_t (dma_events_t),
+        .XifIdWidth (XifIdWidth),
+        .x_issue_req_t (x_issue_req_t),
+        .x_issue_resp_t (x_issue_resp_t),
+        .x_result_t (x_result_t),
         .BootAddr (BootAddrInternal),
         .RVE (RVE[i]),
         .RVF (RVF[i]),
@@ -1094,6 +1113,13 @@ module snitch_cluster
         .data_rsp_i (core_rsp[i]),
         .tcdm_req_o (tcdm_req_wo_user),
         .tcdm_rsp_i (tcdm_rsp[TcdmPortsOffs+:TcdmPorts]),
+        .x_issue_req_o (x_issue_req_o[i]),
+        .x_issue_resp_i (x_issue_resp_i[i]),
+        .x_issue_valid_o (x_issue_valid_o[i]),
+        .x_issue_ready_i (x_issue_ready_i[i]),
+        .x_result_i (x_result_i[i]),
+        .x_result_valid_i (x_result_valid_i[i]),
+        .x_result_ready_o (x_result_ready_o[i]),
         .axi_dma_req_o (axi_dma_req),
         .axi_dma_res_i (axi_dma_res),
         .axi_dma_busy_o (),

hw/snitch_cluster/src/snitch_cluster_pkg.sv.tpl

@@ -67,6 +67,8 @@ package ${cfg['cluster']['name']}_pkg;
   localparam int unsigned ICacheLineCount [NrHives] = '{${icache_cfg('depth')}};
   localparam int unsigned ICacheWays [NrHives] = '{${icache_cfg('ways')}};
 
+  localparam int unsigned XifIdWidth = ${cfg['cluster']['xif_id_width']};
+
   localparam int unsigned Hive [NrCores] = '{${core_cfg('hive')}};
 
   localparam int unsigned TcdmAddrWidth = $clog2(TcdmSize*1024);
@@ -104,6 +106,40 @@ package ${cfg['cluster']['name']}_pkg;
 
   `TCDM_TYPEDEF_ALL(tcdm_dma, tcdm_addr_t, data_dma_t, strb_dma_t, logic)
 
+  typedef struct packed {
+    logic [31:0]           instr;
+    logic [1:0]            mode;
+    logic [XifIdWidth-1:0] id;
+    logic [2:0][31:0]      rs;
+    logic [2:0]            rs_valid;
+    logic [5:0]            ecs;
+    logic                  ecs_valid;
+  } x_issue_req_t;
+
+  typedef struct packed {
+    logic       accept;
+    logic       writeback;
+    logic       dualwrite;
+    logic [2:0] dualread;
+    logic       loadstore;
+    logic       ecswrite;
+    logic       exc;
+  } x_issue_resp_t;
+
+  typedef struct packed {
+    logic [XifIdWidth-1:0] id;
+    logic [31:0]           data;
+    logic [4:0]            rd;
+    logic                  we;
+    logic [5:0]            ecsdata;
+    logic [2:0]            ecswe;
+    logic                  exc;
+    logic [5:0]            exccode;
+    logic                  err;
+    logic                  dbg;
+  } x_result_t;
+
+
   function automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] get_cached_regions();
     automatic snitch_pma_pkg::rule_t [snitch_pma_pkg::NrMaxRules-1:0] cached_regions;
     cached_regions = '{default: '0};