idma: Streamline TCDM connection, enable multi-channel operation

---------

Co-authored-by: Lucia Luzi <[email protected]>

Author: thommythomaso

Bender.lock

@@ -71,7 +71,7 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 7829f71691a62c1e2e5e3230f370f222c7a83087
+    revision: 9e352db1b70bc87e88670e1ef359aa3fd8bad5f6
     version: null
     source:
       Git: https://github.com/pulp-platform/iDMA.git

Bender.yml

@@ -27,7 +27,7 @@ dependencies:
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.13      }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0       }
   cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 }
-  idma:               { git: https://github.com/pulp-platform/iDMA.git,           rev: __deploy__bebefa3__master }
+  idma:               { git: https://github.com/pulp-platform/iDMA,               rev: 9e352db1b70bc87e88670e1ef359aa3fd8bad5f6 }
 
 export_include_dirs:
   - hw/reqrsp_interface/include
@@ -79,6 +79,7 @@ sources:
       - hw/tcdm_interface/src/tcdm_interface.sv
       # Level 1
       - hw/tcdm_interface/src/axi_to_tcdm.sv
+      - hw/tcdm_interface/src/obi_to_tcdm.sv
       - hw/tcdm_interface/src/reqrsp_to_tcdm.sv
       - hw/tcdm_interface/src/tcdm_mux.sv
   - target: simulation

hw/snitch/src/riscv_instr.sv

@@ -328,6 +328,7 @@ package riscv_instr;
   localparam logic [31:0] DMSTR              = 32'b0000110??????????000000000101011;
   localparam logic [31:0] DMREP              = 32'b000011100000?????000000000101011;
   localparam logic [31:0] DMMCAST            = 32'b000100000000?????000000000101011;
+  localparam logic [31:0] DMINIT             = 32'b0001001??????????000?????0101011;
   localparam logic [31:0] FREP_O             = 32'b????????????????????????10001011;
   localparam logic [31:0] IREP               = 32'b?????????????????????????0111111;
   localparam logic [31:0] SCFGRI             = 32'b????????????00000001?????0101011;

hw/snitch/src/snitch.sv

@@ -2163,7 +2163,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
           illegal_inst = 1'b1;
         end
       end
-      DMCPYI: begin
+      DMCPYI,
+      DMINIT: begin
         if (Xdma) begin
           acc_qreq_o.addr     = DMA_SS;
           opa_select      = Reg;

hw/snitch/src/snitch_pkg.sv

@@ -141,16 +141,18 @@ package snitch_pkg;
 
   // Slaves on Cluster DMA AXI Bus
   typedef enum int unsigned {
-    TCDMDMA    = 0,
-    SoCDMAOut  = 1,
-    ZeroMemory = 2,
-    BootRom    = 3
+    SoCDMAOut   = 0,
+    BootRom     = 1
   } cluster_slave_dma_e;
 
+  typedef enum logic {
+    TCDMDMA   = 0,
+    ToSoC     = 1
+  } dma_e;
+
   typedef enum int unsigned {
-    SoCDMAIn = 32'd0,
-    SDMAMst  = 32'd1,
-    ICache   = 32'd2
+    SDMAMst  = 32'd0,
+    ICache   = 32'd1
   } cluster_master_dma_e;
 
   /// Possible interconnect implementations.

hw/snitch_cluster/src/snitch_cc.sv

@@ -40,6 +40,14 @@ module snitch_cc #(
   parameter type         axi_aw_chan_t      = logic,
   parameter type         axi_req_t          = logic,
   parameter type         axi_rsp_t          = logic,
+  parameter type         init_req_chan_t    = logic,
+  parameter type         init_rsp_chan_t    = logic,
+  parameter type         init_req_t         = logic,
+  parameter type         init_rsp_t         = logic,
+  parameter type         obi_a_chan_t       = logic,
+  parameter type         obi_r_chan_t       = logic,
+  parameter type         obi_req_t          = logic,
+  parameter type         obi_rsp_t          = logic,
   parameter type         hive_req_t         = logic,
   parameter type         hive_rsp_t         = logic,
   parameter type         acc_req_t          = logic,
@@ -116,7 +124,8 @@ module snitch_cc #(
   /// Derived parameter *Do not override*
   parameter int unsigned TCDMPorts = (NumSsrs > 1 ? NumSsrs : 1),
   parameter type addr_t = logic [AddrWidth-1:0],
-  parameter type data_t = logic [DataWidth-1:0]
+  parameter type data_t = logic [DataWidth-1:0],
+  parameter type addr_rule_t = axi_pkg::xbar_rule_64_t
 ) (
   input  logic                              clk_i,
   input  logic                              clk_d2_i,
@@ -137,14 +146,18 @@ module snitch_cc #(
   // DMA ports
   output axi_req_t    [DMANumChannels-1:0]  axi_dma_req_o,
   input  axi_rsp_t    [DMANumChannels-1:0]  axi_dma_res_i,
+  output obi_req_t    [DMANumChannels-1:0]  obi_dma_req_o,
+  input  obi_rsp_t    [DMANumChannels-1:0]  obi_dma_res_i,
   output logic        [DMANumChannels-1:0]  axi_dma_busy_o,
   output dma_events_t [DMANumChannels-1:0]  axi_dma_events_o,
   // Core event strobes
   output snitch_pkg::core_events_t          core_events_o,
   input  addr_t                             tcdm_addr_base_i,
   // Cluster HW barrier
   output logic                              barrier_o,
-  input  logic                              barrier_i
+  input  logic                              barrier_i,
+  // address decode map
+  input  addr_rule_t [TCDMAliasEnable:0]    dma_addr_rule_i
 );
 
   // FMA architecture is "merged" -> mulexp and macexp instructions are supported
@@ -391,20 +404,32 @@ module snitch_cc #(
       .NumAxInFlight (DMANumAxInFlight),
       .DMAReqFifoDepth (DMAReqFifoDepth),
       .NumChannels (DMANumChannels),
+      .TCDMAliasEnable (TCDMAliasEnable),
       .DMATracing (1),
       .axi_ar_chan_t (axi_ar_chan_t),
       .axi_aw_chan_t (axi_aw_chan_t),
       .axi_req_t (axi_req_t),
       .axi_res_t (axi_rsp_t),
+      .init_req_chan_t (init_req_chan_t),
+      .init_rsp_chan_t (init_rsp_chan_t),
+      .init_req_t (init_req_t),
+      .init_rsp_t (init_rsp_t),
+      .obi_a_chan_t (obi_a_chan_t),
+      .obi_r_chan_t (obi_r_chan_t),
+      .obi_req_t (obi_req_t),
+      .obi_res_t (obi_rsp_t),
       .acc_req_t (acc_req_t),
       .acc_res_t (acc_resp_t),
-      .dma_events_t (dma_events_t)
+      .dma_events_t (dma_events_t),
+      .addr_rule_t (addr_rule_t)
     ) i_idma_inst64_top (
       .clk_i,
       .rst_ni,
       .testmode_i      ( 1'b0             ),
       .axi_req_o       ( axi_dma_req_o    ),
       .axi_res_i       ( axi_dma_res_i    ),
+      .obi_req_o       ( obi_dma_req_o    ),
+      .obi_res_i       ( obi_dma_res_i    ),
       .busy_o          ( axi_dma_busy_o   ),
       .acc_req_i       ( acc_snitch_req   ),
       .acc_req_valid_i ( dma_qvalid       ),
@@ -413,7 +438,8 @@ module snitch_cc #(
       .acc_res_valid_o ( dma_pvalid       ),
       .acc_res_ready_i ( dma_pready       ),
       .hart_id_i       ( hart_id_i        ),
-      .events_o        ( axi_dma_events_o )
+      .events_o        ( axi_dma_events_o ),
+      .addr_map_i      ( dma_addr_rule_i  )
     );
 
   // no DMA instanciated