From 7b4b8a9537a8aab9084f146573ba9a434434da13 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Sun, 8 Dec 2024 23:49:02 +0100 Subject: [PATCH 01/21] Update boot2_w25q080.S Send release power-down (0xAB) instruction, to revive flash, that might be in power-down state --- src/rp2350/boot_stage2/boot2_w25q080.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/rp2350/boot_stage2/boot2_w25q080.S b/src/rp2350/boot_stage2/boot2_w25q080.S index 9d37e5f5a..71da8a1cb 100644 --- a/src/rp2350/boot_stage2/boot2_w25q080.S +++ b/src/rp2350/boot_stage2/boot2_w25q080.S @@ -81,6 +81,7 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG +#define CMD_RELEASE_POWERDOWN 0xAB #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 @@ -176,6 +177,12 @@ program_sregs: lw a1, QMI_DIRECT_CSR_OFFSET(a3) andi a1, a1, QMI_DIRECT_CSR_BUSY_BITS bnez a1, 1b + + // Send release power-down command, discard RX + li a0, CMD_RELEASE_POWERDOWN + sw a0, QMI_DIRECT_TX_OFFSET(a3) + jal wait_qmi_ready + lw a0, QMI_DIRECT_RX_OFFSET(a3) // Check whether SR needs updating li a0, CMD_READ_STATUS2 @@ -268,6 +275,12 @@ program_sregs: ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET] tst r0, #QMI_DIRECT_CSR_BUSY_BITS bne 1b + + // Send release power-down command, discard RX + movs r0, #CMD_RELEASE_POWERDOWN + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + bl wait_qmi_ready + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] // Check whether SR needs updating movs r0, #CMD_READ_STATUS2 From 9233fef02ed1dc291929c6818b60f1a152bde2e4 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Sun, 8 Dec 2024 23:49:32 +0100 Subject: [PATCH 02/21] Update boot2_generic_03h.S Send release power-down (0xAB) instruction, to revive flash, that might be in power-down state --- src/rp2350/boot_stage2/boot2_generic_03h.S | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/src/rp2350/boot_stage2/boot2_generic_03h.S b/src/rp2350/boot_stage2/boot2_generic_03h.S index 4e14a4c7b..f7a836f11 100644 --- a/src/rp2350/boot_stage2/boot2_generic_03h.S +++ b/src/rp2350/boot_stage2/boot2_generic_03h.S @@ -46,6 +46,7 @@ #error "RX delay greater than maximum" #endif +#define CMD_RELEASE_POWERDOWN 0xAB #define CMD_READ 0x03 // ---------------------------------------------------------------------------- @@ -60,6 +61,15 @@ // CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min // deassertion, or page boundary burst breaks. +// Need to use direct serial mode to send SR commands. Choose a +// conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) +// since the XIP-mode divisor may be unsafe without an RX delay. +#define INIT_DIRECT_CSR (\ + 30 << QMI_DIRECT_CSR_CLKDIV_LSB | \ + QMI_DIRECT_CSR_EN_BITS | \ + QMI_DIRECT_CSR_AUTO_CS0N_BITS | \ +0) + #define INIT_M0_TIMING (\ 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB |\ @@ -100,6 +110,25 @@ regular_func _stage2_boot sw a0, QMI_M0_RCMD_OFFSET(a3) li a0, INIT_M0_RFMT sw a0, QMI_M0_RFMT_OFFSET(a3) + + // Need to use direct serial mode to send commands. + li a1, INIT_DIRECT_CSR + sw a1, QMI_DIRECT_CSR_OFFSET(a3) + // Wait for cooldown on last XIP transfer to expire, by polling BUSY +1: + lw a1, QMI_DIRECT_CSR_OFFSET(a3) + andi a1, a1, QMI_DIRECT_CSR_BUSY_BITS + bnez a1, 1b + + // Send release power-down command, discard RX + li a0, CMD_RELEASE_POWERDOWN + sw a0, QMI_DIRECT_TX_OFFSET(a3) + jal wait_qmi_ready + lw a0, QMI_DIRECT_RX_OFFSET(a3) + + // Disable direct mode + andi a1, a1, ~QMI_DIRECT_CSR_EN_BITS + sw a1, QMI_DIRECT_CSR_OFFSET(a3) #else push {lr} ldr r3, =XIP_QMI_BASE @@ -109,11 +138,33 @@ regular_func _stage2_boot str r0, [r3, #QMI_M0_RCMD_OFFSET] ldr r0, =INIT_M0_RFMT str r0, [r3, #QMI_M0_RFMT_OFFSET] + + // Need to use direct serial mode to send commands. + ldr r1, =INIT_DIRECT_CSR + str r1, [r3, #QMI_DIRECT_CSR_OFFSET] + // Wait for cooldown on last XIP transfer to expire, by polling BUSY +1: + ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET] + tst r0, #QMI_DIRECT_CSR_BUSY_BITS + bne 1b + + // Send release power-down command, discard RX + movs r0, #CMD_RELEASE_POWERDOWN + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + bl wait_qmi_ready + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + + // Disable direct mode + bics r1, #QMI_DIRECT_CSR_EN_BITS + str r1, [r3, #QMI_DIRECT_CSR_OFFSET] #endif // Pull in standard exit routine #include "boot2_helpers/exit_from_boot2.S" +// Common functions +#include "boot2_helpers/wait_qmi_ready.S" + #ifndef __riscv .global literals literals: From 0d446b42fe02ba27ccda4580186f5f3792634351 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:35:28 +0100 Subject: [PATCH 03/21] Update boot2_generic_03h.S Add `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN` definition, to conditionally execute `0xAB` command --- src/rp2350/boot_stage2/boot2_generic_03h.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/rp2350/boot_stage2/boot2_generic_03h.S b/src/rp2350/boot_stage2/boot2_generic_03h.S index f7a836f11..08df0ae12 100644 --- a/src/rp2350/boot_stage2/boot2_generic_03h.S +++ b/src/rp2350/boot_stage2/boot2_generic_03h.S @@ -46,7 +46,9 @@ #error "RX delay greater than maximum" #endif +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN #define CMD_RELEASE_POWERDOWN 0xAB +#endif #define CMD_READ 0x03 // ---------------------------------------------------------------------------- @@ -61,6 +63,7 @@ // CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min // deassertion, or page boundary burst breaks. +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Need to use direct serial mode to send SR commands. Choose a // conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) // since the XIP-mode divisor may be unsafe without an RX delay. @@ -69,6 +72,7 @@ QMI_DIRECT_CSR_EN_BITS | \ QMI_DIRECT_CSR_AUTO_CS0N_BITS | \ 0) +#endif #define INIT_M0_TIMING (\ 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ @@ -111,6 +115,7 @@ regular_func _stage2_boot li a0, INIT_M0_RFMT sw a0, QMI_M0_RFMT_OFFSET(a3) +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Need to use direct serial mode to send commands. li a1, INIT_DIRECT_CSR sw a1, QMI_DIRECT_CSR_OFFSET(a3) @@ -129,6 +134,7 @@ regular_func _stage2_boot // Disable direct mode andi a1, a1, ~QMI_DIRECT_CSR_EN_BITS sw a1, QMI_DIRECT_CSR_OFFSET(a3) +#endif #else push {lr} ldr r3, =XIP_QMI_BASE @@ -139,6 +145,7 @@ regular_func _stage2_boot ldr r0, =INIT_M0_RFMT str r0, [r3, #QMI_M0_RFMT_OFFSET] +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Need to use direct serial mode to send commands. ldr r1, =INIT_DIRECT_CSR str r1, [r3, #QMI_DIRECT_CSR_OFFSET] @@ -158,12 +165,15 @@ regular_func _stage2_boot bics r1, #QMI_DIRECT_CSR_EN_BITS str r1, [r3, #QMI_DIRECT_CSR_OFFSET] #endif +#endif // Pull in standard exit routine #include "boot2_helpers/exit_from_boot2.S" +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Common functions #include "boot2_helpers/wait_qmi_ready.S" +#endif #ifndef __riscv .global literals From 9a49f44c48e9a1471b999abc1457a4e5999ac268 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:36:31 +0100 Subject: [PATCH 04/21] Update boot2_w25q080.S Add `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN` definition, to conditionally execute `0xAB` command --- src/rp2350/boot_stage2/boot2_w25q080.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/rp2350/boot_stage2/boot2_w25q080.S b/src/rp2350/boot_stage2/boot2_w25q080.S index 71da8a1cb..377c1f773 100644 --- a/src/rp2350/boot_stage2/boot2_w25q080.S +++ b/src/rp2350/boot_stage2/boot2_w25q080.S @@ -81,7 +81,9 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN #define CMD_RELEASE_POWERDOWN 0xAB +#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 @@ -178,11 +180,13 @@ program_sregs: andi a1, a1, QMI_DIRECT_CSR_BUSY_BITS bnez a1, 1b +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Send release power-down command, discard RX li a0, CMD_RELEASE_POWERDOWN sw a0, QMI_DIRECT_TX_OFFSET(a3) jal wait_qmi_ready lw a0, QMI_DIRECT_RX_OFFSET(a3) +#endif // Check whether SR needs updating li a0, CMD_READ_STATUS2 @@ -276,11 +280,13 @@ program_sregs: tst r0, #QMI_DIRECT_CSR_BUSY_BITS bne 1b +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Send release power-down command, discard RX movs r0, #CMD_RELEASE_POWERDOWN str r0, [r3, #QMI_DIRECT_TX_OFFSET] bl wait_qmi_ready ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] +#endif // Check whether SR needs updating movs r0, #CMD_READ_STATUS2 From 4af2a18706686a398bd4387f2a660c96ffdc38ce Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:40:13 +0100 Subject: [PATCH 05/21] Update config.h Add `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN` definition, to conditionally execute `0xAB` command --- src/rp2350/boot_stage2/include/boot_stage2/config.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/rp2350/boot_stage2/include/boot_stage2/config.h b/src/rp2350/boot_stage2/include/boot_stage2/config.h index 61f9b9b53..90b8248ff 100644 --- a/src/rp2350/boot_stage2/include/boot_stage2/config.h +++ b/src/rp2350/boot_stage2/include/boot_stage2/config.h @@ -11,6 +11,11 @@ #include "pico/config.h" +// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=hardware_flash +#ifndef PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +#define PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN 0 +#endif + // PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, Name of the boot stage 2 if selected in the build system, group=boot_stage2 #ifdef PICO_BUILD_BOOT_STAGE2_NAME #define _BOOT_STAGE2_SELECTED From d1e4e208701e170d279fe2bd7703dccc0d7344c6 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:42:19 +0100 Subject: [PATCH 06/21] Update boot2_at25sf128a.S Conditionally (using `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN`) send release power-down (0xAB) instruction, to revive flash, that might be in power-down state --- src/rp2040/boot_stage2/boot2_at25sf128a.S | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/rp2040/boot_stage2/boot2_at25sf128a.S b/src/rp2040/boot_stage2/boot2_at25sf128a.S index 72f751ed9..5521fbe02 100644 --- a/src/rp2040/boot_stage2/boot2_at25sf128a.S +++ b/src/rp2040/boot_stage2/boot2_at25sf128a.S @@ -75,6 +75,9 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +#define CMD_RELEASE_POWERDOWN 0xAB +#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 @@ -147,10 +150,20 @@ program_sregs: ldr r1, =(CTRL0_SPI_TXRX) str r1, [r3, #SSI_CTRLR0_OFFSET] - // Enable SSI and select slave 0 + // Enable SSI and select slave 0 movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN + // Send release power-down command, discard RX + movs r1, #CMD_RELEASE_POWERDOWN + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] +#endif + // Check whether SR needs updating movs r0, #CMD_READ_STATUS2 bl read_flash_sreg From e9c2660c7fe9bb5a9dbbe1141e8c277e652ebfbc Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:42:55 +0100 Subject: [PATCH 07/21] Update boot2_generic_03h.S Conditionally (using `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN`) send release power-down (0xAB) instruction, to revive flash, that might be in power-down state --- src/rp2040/boot_stage2/boot2_generic_03h.S | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/rp2040/boot_stage2/boot2_generic_03h.S b/src/rp2040/boot_stage2/boot2_generic_03h.S index effef930b..0c4d64185 100644 --- a/src/rp2040/boot_stage2/boot2_generic_03h.S +++ b/src/rp2040/boot_stage2/boot2_generic_03h.S @@ -35,6 +35,9 @@ pico_default_asm_setup #define PICO_FLASH_SPI_CLKDIV 4 #endif +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +#define CMD_RELEASE_POWERDOWN 0xAB +#endif #define CMD_READ 0x03 // Value is number of address bits divided by 4 @@ -92,6 +95,16 @@ regular_func _stage2_boot movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN + // Send release power-down command, discard RX + movs r1, #CMD_RELEASE_POWERDOWN + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] +#endif + // We are now in XIP mode. Any bus accesses to the XIP address window will be // translated by the SSI into 03h read commands to the external flash (if cache is missed), // and the data will be returned to the bus. @@ -99,6 +112,11 @@ regular_func _stage2_boot // Pull in standard exit routine #include "boot2_helpers/exit_from_boot2.S" +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +// Common functions +#include "boot2_helpers/wait_ssi_ready.S" +#endif + .global literals literals: .ltorg From 20ed8dbba5dfd484d090dd19230d70975908e6c4 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:43:48 +0100 Subject: [PATCH 08/21] Update boot2_is25lp080.S Conditionally (using `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN`) send release power-down (0xAB) instruction, to revive flash, that might be in power-down state --- src/rp2040/boot_stage2/boot2_is25lp080.S | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/rp2040/boot_stage2/boot2_is25lp080.S b/src/rp2040/boot_stage2/boot2_is25lp080.S index fda0f992f..11f108e8b 100644 --- a/src/rp2040/boot_stage2/boot2_is25lp080.S +++ b/src/rp2040/boot_stage2/boot2_is25lp080.S @@ -71,6 +71,9 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +#define CMD_RELEASE_POWERDOWN 0xAB +#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_WRITE_STATUS 0x01 @@ -114,10 +117,20 @@ program_sregs: ldr r1, =(CTRL0_SPI_TXRX) str r1, [r3, #SSI_CTRLR0_OFFSET] - // Enable SSI and select slave 0 + // Enable SSI and select slave 0 movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN + // Send release power-down command, discard RX + movs r1, #CMD_RELEASE_POWERDOWN + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] +#endif + // Check whether SR needs updating ldr r0, =CMD_READ_STATUS bl read_flash_sreg From ad2198f45127a7b521ae76dc49d4fdf439f034fc Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:44:30 +0100 Subject: [PATCH 09/21] Update boot2_w25q080.S Conditionally (using `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN`) send release power-down (0xAB) instruction, to revive flash, that might be in power-down state --- src/rp2040/boot_stage2/boot2_w25q080.S | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/rp2040/boot_stage2/boot2_w25q080.S b/src/rp2040/boot_stage2/boot2_w25q080.S index c35fb81fa..bba06d087 100644 --- a/src/rp2040/boot_stage2/boot2_w25q080.S +++ b/src/rp2040/boot_stage2/boot2_w25q080.S @@ -76,6 +76,9 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +#define CMD_RELEASE_POWERDOWN 0xAB +#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 @@ -147,10 +150,20 @@ program_sregs: ldr r1, =(CTRL0_SPI_TXRX) str r1, [r3, #SSI_CTRLR0_OFFSET] - // Enable SSI and select slave 0 + // Enable SSI and select slave 0 movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] +#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN + // Send release power-down command, discard RX + movs r1, #CMD_RELEASE_POWERDOWN + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] +#endif + // Check whether SR needs updating movs r0, #CMD_READ_STATUS2 bl read_flash_sreg From 2c4702cc503c9a4def87d9174826ea2cd3538ecb Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 15:47:06 +0100 Subject: [PATCH 10/21] Update config.h Add `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN` definition, to conditionally execute `0xAB` command --- src/rp2040/boot_stage2/include/boot_stage2/config.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/rp2040/boot_stage2/include/boot_stage2/config.h b/src/rp2040/boot_stage2/include/boot_stage2/config.h index ba9bb1f8b..e786e7aba 100644 --- a/src/rp2040/boot_stage2/include/boot_stage2/config.h +++ b/src/rp2040/boot_stage2/include/boot_stage2/config.h @@ -11,6 +11,11 @@ #include "pico.h" +// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=hardware_flash +#ifndef PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN +#define PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN 0 +#endif + // PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, Name of the boot stage 2 if selected in the build system, group=boot_stage2 #ifdef PICO_BUILD_BOOT_STAGE2_NAME #define _BOOT_STAGE2_SELECTED From edcd080e2c28f13a9eec4d5207fb6cf2d86c4371 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 16:35:30 +0100 Subject: [PATCH 11/21] Update config.h Fixing copy-paste glitch --- src/rp2350/boot_stage2/include/boot_stage2/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rp2350/boot_stage2/include/boot_stage2/config.h b/src/rp2350/boot_stage2/include/boot_stage2/config.h index 90b8248ff..35c886c08 100644 --- a/src/rp2350/boot_stage2/include/boot_stage2/config.h +++ b/src/rp2350/boot_stage2/include/boot_stage2/config.h @@ -11,7 +11,7 @@ #include "pico/config.h" -// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=hardware_flash +// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=boot_stage2 #ifndef PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN #define PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN 0 #endif From beda4a5f082e007a0a50345bdc1bdc071d316832 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 16:36:13 +0100 Subject: [PATCH 12/21] Update config.h Fixing copy-paste glitch --- src/rp2040/boot_stage2/include/boot_stage2/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rp2040/boot_stage2/include/boot_stage2/config.h b/src/rp2040/boot_stage2/include/boot_stage2/config.h index e786e7aba..e2313aaad 100644 --- a/src/rp2040/boot_stage2/include/boot_stage2/config.h +++ b/src/rp2040/boot_stage2/include/boot_stage2/config.h @@ -11,7 +11,7 @@ #include "pico.h" -// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=hardware_flash +// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=boot_stage2 #ifndef PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN #define PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN 0 #endif From 5f715b2f1e2b5f726a0dd928607adbc040f52142 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:33:10 +0100 Subject: [PATCH 13/21] Update config.h Review change of `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN` --- src/rp2040/boot_stage2/include/boot_stage2/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rp2040/boot_stage2/include/boot_stage2/config.h b/src/rp2040/boot_stage2/include/boot_stage2/config.h index e2313aaad..c9ef5730f 100644 --- a/src/rp2040/boot_stage2/include/boot_stage2/config.h +++ b/src/rp2040/boot_stage2/include/boot_stage2/config.h @@ -11,7 +11,7 @@ #include "pico.h" -// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=boot_stage2 +// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Release the flash device from power-down state during boot stage 2, type=bool, default=0, group=boot_stage2 #ifndef PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN #define PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN 0 #endif From 4b6b03ff8bf52e15343a2c01abd5ecadbaa6a55f Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:34:24 +0100 Subject: [PATCH 14/21] Update config.h Review change of `PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN` --- src/rp2350/boot_stage2/include/boot_stage2/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rp2350/boot_stage2/include/boot_stage2/config.h b/src/rp2350/boot_stage2/include/boot_stage2/config.h index 35c886c08..408a72f9b 100644 --- a/src/rp2350/boot_stage2/include/boot_stage2/config.h +++ b/src/rp2350/boot_stage2/include/boot_stage2/config.h @@ -11,7 +11,7 @@ #include "pico/config.h" -// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Enable/disable releasing flash device from the power-down state during boot stage 2, type=bool, default=0, group=boot_stage2 +// PICO_CONFIG: PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN, Release the flash device from power-down state during boot stage 2, type=bool, default=0, group=boot_stage2 #ifndef PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN #define PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN 0 #endif From 771027fb9474f195701e0179429fe5fc302a2e1d Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:37:41 +0100 Subject: [PATCH 15/21] Update boot2_at25sf128a.S Less guards --- src/rp2040/boot_stage2/boot2_at25sf128a.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/rp2040/boot_stage2/boot2_at25sf128a.S b/src/rp2040/boot_stage2/boot2_at25sf128a.S index 5521fbe02..dcab0e197 100644 --- a/src/rp2040/boot_stage2/boot2_at25sf128a.S +++ b/src/rp2040/boot_stage2/boot2_at25sf128a.S @@ -75,14 +75,12 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN -#define CMD_RELEASE_POWERDOWN 0xAB -#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 #define CMD_WRITE_STATUS 0x01 #define CMD_WRITE_STATUS2 0x31 +#define CMD_RELEASE_POWERDOWN 0xAB #define SREG_DATA 0x02 // Enable quad-SPI mode // ---------------------------------------------------------------------------- From 7cb1bebc3d7b6e663d3be8d15accd3946d285487 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:40:28 +0100 Subject: [PATCH 16/21] Update boot2_generic_03h.S Less guards --- src/rp2040/boot_stage2/boot2_generic_03h.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/rp2040/boot_stage2/boot2_generic_03h.S b/src/rp2040/boot_stage2/boot2_generic_03h.S index 0c4d64185..047fae7b7 100644 --- a/src/rp2040/boot_stage2/boot2_generic_03h.S +++ b/src/rp2040/boot_stage2/boot2_generic_03h.S @@ -35,10 +35,8 @@ pico_default_asm_setup #define PICO_FLASH_SPI_CLKDIV 4 #endif -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN -#define CMD_RELEASE_POWERDOWN 0xAB -#endif #define CMD_READ 0x03 +#define CMD_RELEASE_POWERDOWN 0xAB // Value is number of address bits divided by 4 #define ADDR_L 6 From bd11dd43e62b69e878e5c3764ceebb9993daa6a9 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:42:22 +0100 Subject: [PATCH 17/21] Update boot2_is25lp080.S Less guards --- src/rp2040/boot_stage2/boot2_is25lp080.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/rp2040/boot_stage2/boot2_is25lp080.S b/src/rp2040/boot_stage2/boot2_is25lp080.S index 11f108e8b..e1a4e4429 100644 --- a/src/rp2040/boot_stage2/boot2_is25lp080.S +++ b/src/rp2040/boot_stage2/boot2_is25lp080.S @@ -71,12 +71,10 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN -#define CMD_RELEASE_POWERDOWN 0xAB -#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_WRITE_STATUS 0x01 +#define CMD_RELEASE_POWERDOWN 0xAB #define SREG_DATA 0x40 // Enable quad-SPI mode // ---------------------------------------------------------------------------- From e9bcc58fd906f9bdab2dadb2487afe8d9587b875 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:43:18 +0100 Subject: [PATCH 18/21] Update boot2_w25q080.S Less guards --- src/rp2040/boot_stage2/boot2_w25q080.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/rp2040/boot_stage2/boot2_w25q080.S b/src/rp2040/boot_stage2/boot2_w25q080.S index bba06d087..2ccec85a1 100644 --- a/src/rp2040/boot_stage2/boot2_w25q080.S +++ b/src/rp2040/boot_stage2/boot2_w25q080.S @@ -76,13 +76,11 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN -#define CMD_RELEASE_POWERDOWN 0xAB -#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 #define CMD_WRITE_STATUS 0x01 +#define CMD_RELEASE_POWERDOWN 0xAB #define SREG_DATA 0x02 // Enable quad-SPI mode // ---------------------------------------------------------------------------- From 752de1697a7540dec087a8e796e1572d2b1b90be Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:46:52 +0100 Subject: [PATCH 19/21] Update boot2_generic_03h.S Less guards --- src/rp2350/boot_stage2/boot2_generic_03h.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/rp2350/boot_stage2/boot2_generic_03h.S b/src/rp2350/boot_stage2/boot2_generic_03h.S index 08df0ae12..0e9b79266 100644 --- a/src/rp2350/boot_stage2/boot2_generic_03h.S +++ b/src/rp2350/boot_stage2/boot2_generic_03h.S @@ -46,10 +46,8 @@ #error "RX delay greater than maximum" #endif -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN -#define CMD_RELEASE_POWERDOWN 0xAB -#endif #define CMD_READ 0x03 +#define CMD_RELEASE_POWERDOWN 0xAB // ---------------------------------------------------------------------------- // Register initialisation values -- same in Arm/RISC-V code. From 0192d605623103cc7ca0aa183f7763f9d0063159 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:49:08 +0100 Subject: [PATCH 20/21] Update boot2_generic_03h.S Less guards --- src/rp2350/boot_stage2/boot2_generic_03h.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/rp2350/boot_stage2/boot2_generic_03h.S b/src/rp2350/boot_stage2/boot2_generic_03h.S index 0e9b79266..44c9eec9b 100644 --- a/src/rp2350/boot_stage2/boot2_generic_03h.S +++ b/src/rp2350/boot_stage2/boot2_generic_03h.S @@ -61,7 +61,6 @@ // CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min // deassertion, or page boundary burst breaks. -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN // Need to use direct serial mode to send SR commands. Choose a // conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) // since the XIP-mode divisor may be unsafe without an RX delay. @@ -70,7 +69,6 @@ QMI_DIRECT_CSR_EN_BITS | \ QMI_DIRECT_CSR_AUTO_CS0N_BITS | \ 0) -#endif #define INIT_M0_TIMING (\ 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ From 853a41455eb29e362cf3d120c2ccb6d4514556b2 Mon Sep 17 00:00:00 2001 From: matsobdev <63716661+matsobdev@users.noreply.github.com> Date: Wed, 22 Jan 2025 22:49:50 +0100 Subject: [PATCH 21/21] Update boot2_w25q080.S Less guards --- src/rp2350/boot_stage2/boot2_w25q080.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/rp2350/boot_stage2/boot2_w25q080.S b/src/rp2350/boot_stage2/boot2_w25q080.S index 377c1f773..4ab1aca7f 100644 --- a/src/rp2350/boot_stage2/boot2_w25q080.S +++ b/src/rp2350/boot_stage2/boot2_w25q080.S @@ -81,13 +81,11 @@ // A better solution is to use a volatile SR write if your device supports it. #define PROGRAM_STATUS_REG -#if PICO_BOOT_STAGE2_FLASH_RELEASE_POWERDOWN -#define CMD_RELEASE_POWERDOWN 0xAB -#endif #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS2 0x35 #define CMD_WRITE_STATUS 0x01 +#define CMD_RELEASE_POWERDOWN 0xAB #define SREG_DATA 0x02 // Enable quad-SPI mode // ----------------------------------------------------------------------------