diff --git a/verilog/sa/README.md b/verilog/sa/README.md
index a073d93..a8992da 100644
--- a/verilog/sa/README.md
+++ b/verilog/sa/README.md
@@ -33,6 +33,6 @@ Then we try swaps. When we try swaps, observe that we don't have to re-compute t
 
 The temperature schedule is: Start at a given temperature, multiply it each iteration by a constant value (about 0.9999999). Since we only ever divide by T (and division is super expensive - over 30 cycles!), we start at a given 1/T, and multiply it each iteration by 1/factor (about 1.0000001).
 
-However, we still have to do a reciprocal, and thus the latency of each iteration is on the order of a hundred cycles. Since iterations aren't pipelined (yet), the throughput is about 1 per 100 cycles.
+However, we still have to do a reciprocal, and thus the latency of each iteration is on the order of a hundred cycles. Since iterations aren't pipelined (yet), the throughput is about 1 per 30 cycles, depending on how often it computes negexp.
 
-But, for all of these problems, this code used to fit onto the Mojo chip. Post-translate it uses 157% of the LUTs, and map takes several hours so hopefully it'll fit. We'll see.
+But, for all of these problems, this code actually fits on a Mojo chip, so that's pretty cool.
diff --git a/verilog/sa/src/mojo_top.v b/verilog/sa/src/mojo_top.v
index 89d18af..565c099 100644
--- a/verilog/sa/src/mojo_top.v
+++ b/verilog/sa/src/mojo_top.v
@@ -116,7 +116,7 @@ always @(*) begin
 	if (best_distance_valid || cntdown_q == 0) begin
 		printval_d = best_distance;
 		digit_cnt_d = 8;
-		tx_data_d = "\n";
+		tx_data_d = "\r";
 		tx_new_data_d = 1;
 		cntdown_d = 100000000;
 	end
@@ -137,8 +137,7 @@ always @(posedge clk) begin
 	end
 end
 
-assign led = best_distance[7:0];//exp_debug;//floatval[7:0];//rng_out[7:0];//{tx_busy, printval_q[6:0]};
-//assign led = exp_res[7:0];
+assign led = best_distance[15:8];
 
 // these signals should be high-z when not used
 assign spi_miso = 1'bz;
diff --git a/verilog/sa/src/tsp.v b/verilog/sa/src/tsp.v
index efccf26..0f0bcb7 100644
--- a/verilog/sa/src/tsp.v
+++ b/verilog/sa/src/tsp.v
@@ -121,13 +121,8 @@ reg [PRECISION*2-1:0] city1_q, city1_d, city2_q, city2_d, city3_q, city3_d, city
 `define X(v) (v[PRECISION-1:0])
 `define Y(v) (v[PRECISION*2-1:PRECISION])
 
-assign debug = {2'b0, total_dist_q[5:0]};//total_dist_q[7:0];//string_len_q;//{state_q[2:0], has_read_prolog_q, nextstate_q[2:0], 1'b0};//nnodes_in_file_q[7:0];//((read_string_q>>((string_len_q-1)*8))&8'hFF);//{string_len_q[3:0],nnodes_in_file_q[3:0]};
+assign debug = nnodes_in_file_q[7:0];
 
-//reg [PRECISION-1:0] dx_q, dx_d, dy_q, dy_d;
-//wire [PRECISION-1:0] dx, dy, dist_squared;
-//assign dx = `X(doutb)-`X(douta);
-//assign dy = `Y(doutb)-`Y(douta);
-//assign dist_squared = dx*dx + dy*dy;
 reg [2:0] pipe_tx_ctr_q, pipe_tx_ctr_d, pipe_rx_ctr_q, pipe_rx_ctr_d;
 reg [PRECISION*4*2-1:0] pipe_tx_buf_a_q, pipe_tx_buf_a_d, pipe_tx_buf_b_q, pipe_tx_buf_b_d;
 reg [PRECISION*4-1:0] pipe_rx_buf_q, pipe_rx_buf_d;