Commit 89f0573
target/riscv: improve error messaging in case
From: Sriram Shanmuga <[email protected]>
RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
Status (`sbcs`, at 0x38)] states in `sbasize` field description:
> Width of system bus addresses in bits. (0 indicates there is no bus
access support.)
Before the patch, the error message did not include the information
about `sbcs.sbasize` being zero wich made it quite undescriptive:
```
[riscv.cpu] Turning off memory sampling because it failed.
```
Fixes #1270
Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
Signed-off-by: Sriram Shanmuga <[email protected]>
Signed-off-by: Evgeniy Naydanov <[email protected]>sbasize is zero1 parent 6f84e90 commit 89f0573
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