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This adds the section tree to the tags JSON output, including which tags are in each section and the section IDs. For example for the RISC-V Privileged spec it outputs:
```
{
"tags": {
"norm:ext:Sm:highest_priv_mode": "machine-mode (M-mode), which is the highest privilege mode in a RISC-V\nhart.",
"norm:ext:Sm:mode_at_reset": "M-mode is used for low-level access to a hardware platform and\nis the first mode entered at reset.",
"norm:ext:Sm:access_all_lower_priv_CSRs": "M-mode code can access all CSRs at lower privilege levels.",
...
"norm:csr:mstatus:sz_rw": "The mstatus register is an MXLEN-bit read/write register formatted as\nshown in <<mstatusreg-rv32>> for RV32 and <<mstatusreg>> for RV64.",
"norm:csr:mstatush:sz_rw_rv32": "For RV32 only, mstatush is a 32-bit read/write register formatted as shown in <<mstatushreg>>.",
"norm:csr:mstatush:encoding": "Bits 30:4 of mstatush generally contain the same fields found in bits 62:36 of mstatus for RV64. Fields SD, SXL, and UXL do not exist in mstatush."
},
"sections": {
"title": "",
"id": "",
"children": [
{
"title": "Preface",
"id": "_preface",
"children": [],
"tags": []
},
...
{
"title": "Machine-Level ISA, Version 1.13",
"id": "machine",
"children": [
{
"title": "Machine-Level CSRs",
"id": "_machine_level_csrs",
"children": [
{
"title": "Machine ISA (misa) Register",
"id": "misa",
"children": [],
"tags": [
"norm:csr:misa:sw_rw",
"norm:csr:misa:always_readable",
"norm:param:MISA_CSR_IMPLEMENTED:can_be_zero",
...
"norm:csrfld:misa:e:not_i",
"norm:csrfld:misa:extensions:dependencies",
"norm:csr:misa:inc_ialign"
]
},
{
"title": "Machine Vendor ID (mvendorid) Register",
"id": "_machine_vendor_id_mvendorid_register",
"children": [],
"tags": [
"norm:csr:mvendorid:sz_ro_meaning",
"norm:csr:mvendorid:always_readable",
"norm:csr:mvendorid:encoding",
"norm:csr:mvendorid:bank_1_less_than_JEDEC"
]
},
```
Signed-off-by: Tim Hutt <[email protected]>
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