Remove code setting IC_DATA_CMD.RESTART bit

According to the datasheet, a restart is automatically triggered "if
the transfer direction is changing from the previous command". The
RESTART bit is only needed to trigger an unconditional RESTART sequence.

According to the contract of I2c::transaction, "Data from
adjacent operations of the same type are sent after each other without
an SP or SR" and "Between adjacent operations of a different type an SR
and SAD+R/W is sent". This looks like it is exactly what the hardware
provides out of the box.

(See: https://docs.rs/embedded-hal/1.0.0/ebedded_hal/i2c/trait.I2c.html#tymethod.transaction)

Author: jannic

rp2040-hal/src/i2c/controller.rs

@@ -227,21 +227,13 @@ impl<T: Deref<Target = Block>, PINS> I2C<T, PINS, Controller> {
         )?;
 
         let lastindex = buffer.len() - 1;
-        let mut first_byte = true;
         for (i, byte) in buffer.iter_mut().enumerate() {
             let last_byte = i == lastindex;
 
             // wait until there is space in the FIFO to write the next byte
             while self.i2c.ic_status().read().tfnf().bit_is_clear() {}
 
             self.i2c.ic_data_cmd().write(|w| {
-                if first_byte {
-                    if !first_transaction {
-                        w.restart().enable();
-                    }
-                    first_byte = false;
-                }
-
                 w.stop().bit(do_stop && last_byte);
                 w.cmd().read()
             });
@@ -270,7 +262,6 @@ impl<T: Deref<Target = Block>, PINS> I2C<T, PINS, Controller> {
         )?;
 
         let mut abort_reason = Ok(());
-        let mut first_byte = true;
         'outer: while let Some(byte) = peekable.next() {
             if self.tx_fifo_full() {
                 // wait for more room in the fifo
@@ -289,12 +280,6 @@ impl<T: Deref<Target = Block>, PINS> I2C<T, PINS, Controller> {
             // else enqueue
             let last = peekable.peek().is_none();
             self.i2c.ic_data_cmd().write(|w| {
-                if first_byte {
-                    if !first_transaction {
-                        w.restart().enable();
-                    }
-                    first_byte = false;
-                }
                 w.stop().bit(do_stop && last);
                 unsafe { w.dat().bits(byte) }
             });

rp2040-hal/src/i2c/controller/non_blocking.rs

@@ -120,7 +120,6 @@ where
         )?;
 
         let lastindex = buffer.len() - 1;
-        let mut first_byte = true;
         for (i, byte) in buffer.iter_mut().enumerate() {
             let last_byte = i == lastindex;
 
@@ -135,13 +134,6 @@ where
             .await;
 
             self.i2c.ic_data_cmd().write(|w| {
-                if first_byte {
-                    if !first_transaction {
-                        w.restart().enable();
-                    }
-                    first_byte = false;
-                }
-
                 w.stop().bit(do_stop && last_byte);
                 w.cmd().read()
             });
@@ -174,7 +166,6 @@ where
         )?;
 
         let mut abort_reason = Ok(());
-        let mut first_byte = true;
         while let Some(byte) = peekable.next() {
             if self.tx_fifo_full() {
                 // wait for more room in the fifo
@@ -193,12 +184,6 @@ where
             // else enqueue
             let last = peekable.peek().is_none();
             self.i2c.ic_data_cmd().write(|w| {
-                if first_byte {
-                    if !first_transaction {
-                        w.restart().enable();
-                    }
-                    first_byte = false;
-                }
                 w.stop().bit(do_stop && last);
                 unsafe { w.dat().bits(byte) }
             });