diff --git a/.cargo/config.toml b/.cargo/config.toml index 1d43fc3..d406d74 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -16,12 +16,21 @@ runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nogr [target.armv7a-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel" +[target.armv6-none-eabihf] +runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel" + +[target.armv6-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel" + [target.armv5te-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" [target.armv4t-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" +[target.thumbv6-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel" + [target.thumbv5te-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" diff --git a/aarch32-cpu/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs index 8fab4af..718f0e3 100644 --- a/aarch32-cpu/src/register/cpsr.rs +++ b/aarch32-cpu/src/register/cpsr.rs @@ -75,7 +75,11 @@ impl Cpsr { /// `thumb*` targets, as Thumb-1 cannot do an MRS. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] pub fn read() -> Self { @@ -108,7 +112,11 @@ impl Cpsr { /// `thumb*` targets, as Thumb-1 cannot do an MSR. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] pub unsafe fn write(_value: Self) { diff --git a/aarch32-cpu/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs index 7dac1a3..f8ba885 100644 --- a/aarch32-cpu/src/register/mod.rs +++ b/aarch32-cpu/src/register/mod.rs @@ -225,7 +225,11 @@ pub trait SysRegRead: SysReg { /// may have side-effects. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] unsafe fn read_raw() -> u32 { @@ -261,7 +265,11 @@ pub trait SysRegWrite: SysReg { /// writing valid data here. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] unsafe fn write_raw(_value: u32) { diff --git a/arm-targets/src/lib.rs b/arm-targets/src/lib.rs index 259e4e5..fcc0829 100644 --- a/arm-targets/src/lib.rs +++ b/arm-targets/src/lib.rs @@ -224,7 +224,10 @@ impl Arch { Some(Arch::Armv7A) } else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") { Some(Arch::Armv8A) - } else if target.starts_with("arm-") { + } else if target.starts_with("arm-") + || target.starts_with("armv6-") + || target.starts_with("thumbv6-") + { // If not specified, assume Armv6 Some(Arch::Armv6) } else { @@ -409,6 +412,26 @@ mod test { assert_eq!(target_info.abi(), Some(Abi::Eabi)); } + #[test] + fn armv6_none_eabi() { + let target = "armv6-none-eabi"; + let target_info = process_target(target); + assert_eq!(target_info.isa(), Some(Isa::A32)); + assert_eq!(target_info.arch(), Some(Arch::Armv6)); + assert_eq!(target_info.profile(), Some(Profile::Legacy)); + assert_eq!(target_info.abi(), Some(Abi::Eabi)); + } + + #[test] + fn armv6_none_eabihf() { + let target = "armv6-none-eabihf"; + let target_info = process_target(target); + assert_eq!(target_info.isa(), Some(Isa::A32)); + assert_eq!(target_info.arch(), Some(Arch::Armv6)); + assert_eq!(target_info.profile(), Some(Profile::Legacy)); + assert_eq!(target_info.abi(), Some(Abi::EabiHf)); + } + #[test] fn arm_unknown_linux_gnueabi() { let target = "arm-unknown-linux-gnueabi"; diff --git a/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv6-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv6-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv6-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv6-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv6-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv6-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/fpu-test-armv6-none-eabi.out b/examples/versatileab/reference/fpu-test-armv6-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-armv6-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) 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...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-thumbv6-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv6-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv6-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/hello-armv6-none-eabi.out b/examples/versatileab/reference/hello-armv6-none-eabi.out new file mode 100644 index 0000000..0d377af --- /dev/null +++ b/examples/versatileab/reference/hello-armv6-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 18, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-armv6-none-eabihf.out b/examples/versatileab/reference/hello-armv6-none-eabihf.out new file mode 100644 index 0000000..0d377af --- /dev/null +++ b/examples/versatileab/reference/hello-armv6-none-eabihf.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 18, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-thumbv6-none-eabi.out b/examples/versatileab/reference/hello-thumbv6-none-eabi.out new file mode 100644 index 0000000..0d377af --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv6-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 18, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/interrupt-armv6-none-eabi.out b/examples/versatileab/reference/interrupt-armv6-none-eabi.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-armv6-none-eabi.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-armv6-none-eabihf.out b/examples/versatileab/reference/interrupt-armv6-none-eabihf.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-armv6-none-eabihf.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-thumbv6-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv6-none-eabi.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv6-none-eabi.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv6-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv6-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv6-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv6-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/registers-armv6-none-eabi.out b/examples/versatileab/reference/registers-armv6-none-eabi.out new file mode 100644 index 0000000..f24dd0c --- /dev/null +++ b/examples/versatileab/reference/registers-armv6-none-eabi.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(410fb767) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-armv6-none-eabihf.out b/examples/versatileab/reference/registers-armv6-none-eabihf.out new file mode 100644 index 0000000..f24dd0c --- /dev/null +++ b/examples/versatileab/reference/registers-armv6-none-eabihf.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(410fb767) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-thumbv6-none-eabi.out b/examples/versatileab/reference/registers-thumbv6-none-eabi.out new file mode 100644 index 0000000..f24dd0c --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv6-none-eabi.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(410fb767) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/svc-a32-armv6-none-eabi.out b/examples/versatileab/reference/svc-a32-armv6-none-eabi.out new file mode 100644 index 0000000..aa7cc28 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-armv6-none-eabi.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-a32.rs", + line: 22, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..aa7cc28 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-a32.rs", + line: 22, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-a32-thumbv6-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv6-none-eabi.out new file mode 100644 index 0000000..aa7cc28 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv6-none-eabi.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-a32.rs", + line: 22, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-t32-armv6-none-eabi.out b/examples/versatileab/reference/svc-t32-armv6-none-eabi.out new file mode 100644 index 0000000..3476848 --- /dev/null +++ b/examples/versatileab/reference/svc-t32-armv6-none-eabi.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-t32.rs", + line: 23, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..3476848 --- /dev/null +++ b/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-t32.rs", + line: 23, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-t32-thumbv6-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv6-none-eabi.out new file mode 100644 index 0000000..3476848 --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv6-none-eabi.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-t32.rs", + line: 23, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv6-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv6-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv6-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv6-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv6-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv6-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/src/bin/prefetch-exception-a32.rs b/examples/versatileab/src/bin/prefetch-exception-a32.rs index 0dd67aa..b1c913a 100644 --- a/examples/versatileab/src/bin/prefetch-exception-a32.rs +++ b/examples/versatileab/src/bin/prefetch-exception-a32.rs @@ -63,7 +63,8 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize { if cfg!(not(any( arm_architecture = "v4t", - arm_architecture = "v5te" + arm_architecture = "v5te", + arm_architecture = "v6" ))) { let ifar = Ifar::read(); println!("IFAR (Faulting Address Register): {:?}", ifar); diff --git a/examples/versatileab/src/bin/prefetch-exception-t32.rs b/examples/versatileab/src/bin/prefetch-exception-t32.rs index ab9631c..996b5f9 100644 --- a/examples/versatileab/src/bin/prefetch-exception-t32.rs +++ b/examples/versatileab/src/bin/prefetch-exception-t32.rs @@ -63,7 +63,8 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize { if cfg!(not(any( arm_architecture = "v4t", - arm_architecture = "v5te" + arm_architecture = "v5te", + arm_architecture = "v6" ))) { let ifar = Ifar::read(); println!("IFAR (Faulting Address Register): {:?}", ifar); diff --git a/examples/versatileab/src/bin/svc-a32.rs b/examples/versatileab/src/bin/svc-a32.rs index 3a24519..eea88c9 100644 --- a/examples/versatileab/src/bin/svc-a32.rs +++ b/examples/versatileab/src/bin/svc-a32.rs @@ -33,7 +33,11 @@ fn svc_handler(arg: u32) { } #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] fn do_svc1() { @@ -41,7 +45,11 @@ fn do_svc1() { } #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] fn do_svc2() {